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/* |
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* mon_z80.cpp - Z80 disassembler |
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* |
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* cxmon (C) 1997-2002 Christian Bauer, Marc Hellwig |
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* cxmon (C) 1997-2007 Christian Bauer, Marc Hellwig |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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A_COND, // condition code (bits 3..5 of opcode) |
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A_COND2, // condition code (bits 3..4 of opcode) |
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A_BIT, // bit number (bits 3..5 of opcode) |
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A_BIT_REG1, // bit number (bits 3..5 of opcode) followed by 8-bit register (bits 0..2 of opcode) |
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A_RST, // restart |
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A_BC_IND, // (bc) |
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A_DE_IND, // (de) |
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A_HL_IND, // (hl) or (ix) or (iy) |
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A_XY_IND, // (ix+d) or (iy+d) |
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A_SP_IND, // (sp) |
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A_DE_HL, // de,hl |
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A_AF_AF, // af,af' |
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break; |
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case A_REL: |
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mon_sprintf(f, "$%04x", (adr + 2 + (int8)mon_read_byte(adr)) & 0xffff); adr++; |
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mon_sprintf(f, "$%04x", (adr + 1 + (int8)mon_read_byte(adr)) & 0xffff); adr++; |
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break; |
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case A_A: |
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if (reg == 6) { |
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if (ix || iy) { |
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mon_sprintf(f, "(%s+$%02x)", ix ? "ix" : "iy", mon_read_byte(adr)); adr++; |
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} else |
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} else { |
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mon_sprintf(f, "(hl)"); |
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} else if (mode == A_REG1) |
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} |
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} else if (mode == A_REG1) { |
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mon_sprintf(f, "%s", ix ? reg_name_ix[reg] : (iy ? reg_name_iy[reg] : reg_name[reg])); |
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else |
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} else { |
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mon_sprintf(f, "%s", reg_name[reg]); |
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} |
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break; |
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} |
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if (reg == 6) { |
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if (ix || iy) { |
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mon_sprintf(f, "(%s+$%02x)", ix ? "ix" : "iy", mon_read_byte(adr)); adr++; |
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} else |
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} else { |
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mon_sprintf(f, "(hl)"); |
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} else if (mode == A_REG2) |
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} |
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} else if (mode == A_REG2) { |
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mon_sprintf(f, "%s", ix ? reg_name_ix[reg] : (iy ? reg_name_iy[reg] : reg_name[reg])); |
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else |
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} else { |
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mon_sprintf(f, "%s", reg_name[reg]); |
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} |
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break; |
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} |
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case A_REG3: |
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mon_sprintf(f, reg_name_16[(op >> 4) & 3]); |
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case A_REG3: { |
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int reg = (op >> 4) & 3; |
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if (reg == 2 && (ix || iy)) { |
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mon_sprintf(f, ix ? "ix" : "iy"); |
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} else { |
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mon_sprintf(f, reg_name_16[reg]); |
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} |
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break; |
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} |
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case A_REG4: |
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mon_sprintf(f, reg_name_16_2[(op >> 4) & 3]); |
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case A_REG4: { |
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int reg = (op >> 4) & 3; |
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if (reg == 2 && (ix || iy)) { |
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mon_sprintf(f, ix ? "ix" : "iy"); |
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} else { |
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mon_sprintf(f, reg_name_16_2[reg]); |
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} |
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break; |
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} |
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case A_COND: |
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mon_sprintf(f, cond_name[(op >> 3) & 7]); |
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mon_sprintf(f, "%d", (op >> 3) & 7); |
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break; |
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case A_BIT_REG1: { // undoc |
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int reg = op & 7; |
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if (reg == 6) { |
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mon_sprintf(f, "%d", (op >> 3) & 7); |
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} else { |
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mon_sprintf(f, "%d,%s", (op >> 3) & 7, reg_name[reg]); |
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} |
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break; |
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} |
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|
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case A_RST: |
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mon_sprintf(f, "$%02x", op & 0x38); |
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break; |
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mon_sprintf(f, ix ? "(ix)" : (iy ? "(iy)" : "(hl)")); |
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break; |
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case A_XY_IND: // undoc |
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mon_sprintf(f, "(%s+$%02x)", ix ? "ix" : "iy", mon_read_byte(adr)); adr++; |
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break; |
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|
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case A_SP_IND: |
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mon_sprintf(f, "(sp)"); |
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break; |
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char mnem = M_ILLEGAL, dst_mode = A_IMPL, src_mode = A_IMPL; |
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switch (op & 0xc0) { |
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case 0x00: |
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dst_mode = A_REG1; |
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dst_mode = A_REG1X; |
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if ((ix || iy) && ((op & 7) != 6)) |
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src_mode = A_XY_IND; |
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switch ((op >> 3) & 7) { |
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case 0: mnem = M_RLC; break; |
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case 1: mnem = M_RRC; break; |
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case 3: mnem = M_RR; break; |
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case 4: mnem = M_SLA; break; |
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case 5: mnem = M_SRA; break; |
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case 6: mnem = M_SL1; break; |
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case 6: mnem = M_SL1; break; // undoc |
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case 7: mnem = M_SRL; break; |
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} |
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break; |
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case 0x40: |
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mnem = M_BIT; dst_mode = A_BIT; src_mode = A_REG1; |
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mnem = M_BIT; dst_mode = A_BIT; |
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if (ix || iy) |
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src_mode = A_XY_IND; |
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else |
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src_mode = A_REG1; |
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break; |
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case 0x80: |
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mnem = M_RES; dst_mode = A_BIT; src_mode = A_REG1; |
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mnem = M_RES; |
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if (ix || iy) { |
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dst_mode = A_BIT_REG1; |
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src_mode = A_XY_IND; |
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} else { |
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dst_mode = A_BIT; |
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src_mode = A_REG1; |
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} |
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break; |
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case 0xc0: |
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mnem = M_SET; dst_mode = A_BIT; src_mode = A_REG1; |
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mnem = M_SET; |
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if (ix || iy) { |
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dst_mode = A_BIT_REG1; |
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src_mode = A_XY_IND; |
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} else { |
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dst_mode = A_BIT; |
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src_mode = A_REG1; |
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} |
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break; |
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} |
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case 0x60: |
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case 0x68: |
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case 0x78: |
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mon_sprintf(f, "in\t%s,(c)", reg_name[(op >> 3) & 7]); |
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mon_sprintf(f, "in %s,(c)", reg_name[(op >> 3) & 7]); |
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return 1; |
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case 0x70: |
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mon_sprintf(f, "in\t(c)"); |
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mon_sprintf(f, "in (c)"); |
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return 1; |
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case 0x41: |
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case 0x61: |
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case 0x69: |
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case 0x79: |
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mon_sprintf(f, "out\t(c),%s", reg_name[(op >> 3) & 7]); |
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mon_sprintf(f, "out (c),%s", reg_name[(op >> 3) & 7]); |
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return 1; |
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case 0x71: // undoc |
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mon_sprintf(f, "out\t(c),0"); |
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mon_sprintf(f, "out (c),0"); |
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return 1; |
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case 0x42: |
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break; |
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case 0x47: |
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mon_sprintf(f, "ld\ti,a"); |
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mon_sprintf(f, "ld i,a"); |
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return 1; |
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case 0x4f: |
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mon_sprintf(f, "ld\tr,a"); |
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mon_sprintf(f, "ld r,a"); |
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return 1; |
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case 0x57: |
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mon_sprintf(f, "ld\ta,i"); |
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mon_sprintf(f, "ld a,i"); |
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return 1; |
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case 0x5f: |
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mon_sprintf(f, "ld\ta,r"); |
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mon_sprintf(f, "ld a,r"); |
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return 1; |
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case 0x67: mnem = M_RRD; break; |
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case 0xbb: mnem = M_OTDR; break; |
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default: |
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mnem = M_ILLEGAL; |
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mnem = M_NOP; |
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break; |
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} |
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