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gbeauche |
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/* Print mips instructions for GDB, the GNU debugger, or for objdump. |
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Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
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2000, 2001, 2002, 2003, 2005 |
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Free Software Foundation, Inc. |
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Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). |
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This file is part of GDB, GAS, and the GNU binutils. |
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This program is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 2 of the License, or |
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(at your option) any later version. |
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This program is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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You should have received a copy of the GNU General Public License |
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along with this program; if not, write to the Free Software |
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
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MA 02110-1301, USA. */ |
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#include "dis-asm.h" |
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#include "mips.h" |
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#include "opintl.h" |
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#define EMBEDDED_ENV 1 |
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/* FIXME: the following code snippets are not part of the original |
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binutils disassembler and should be moved elsewhere. */ |
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#ifndef ARRAY_SIZE |
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#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) |
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#endif |
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static bfd_vma |
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bfd_getb16 (const void *p) |
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{ |
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const bfd_byte *addr = p; |
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return (addr[0] << 8) | addr[1]; |
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} |
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static bfd_vma |
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bfd_getl16 (const void *p) |
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{ |
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const bfd_byte *addr = p; |
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return (addr[1] << 8) | addr[0]; |
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} |
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static bfd_vma |
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bfd_getb32 (const void *p) |
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{ |
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const bfd_byte *addr = p; |
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unsigned long v; |
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v = (unsigned long) addr[0] << 24; |
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v |= (unsigned long) addr[1] << 16; |
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v |= (unsigned long) addr[2] << 8; |
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v |= (unsigned long) addr[3]; |
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return v; |
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} |
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static bfd_vma |
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bfd_getl32 (const void *p) |
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{ |
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const bfd_byte *addr = p; |
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unsigned long v; |
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v = (unsigned long) addr[0]; |
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v |= (unsigned long) addr[1] << 8; |
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v |= (unsigned long) addr[2] << 16; |
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v |= (unsigned long) addr[3] << 24; |
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return v; |
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} |
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/* FIXME: These are needed to figure out if the code is mips16 or |
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not. The low bit of the address is often a good indicator. No |
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symbol table is available when this code runs out in an embedded |
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system as when it is used for disassembler support in a monitor. */ |
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#if !defined(EMBEDDED_ENV) |
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#define SYMTAB_AVAILABLE 1 |
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#include "elf-bfd.h" |
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#include "elf/mips.h" |
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#endif |
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/* Mips instructions are at maximum this many bytes long. */ |
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#define INSNLEN 4 |
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/* FIXME: These should be shared with gdb somehow. */ |
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struct mips_cp0sel_name |
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{ |
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unsigned int cp0reg; |
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unsigned int sel; |
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const char * const name; |
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}; |
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/* The mips16 registers. */ |
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static const unsigned int mips16_to_32_reg_map[] = |
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{ |
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16, 17, 2, 3, 4, 5, 6, 7 |
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}; |
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#define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]] |
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static const char * const mips_gpr_names_numeric[32] = |
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{ |
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"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", |
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"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", |
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"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", |
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"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" |
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}; |
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static const char * const mips_gpr_names_oldabi[32] = |
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{ |
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"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
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"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", |
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"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
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"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" |
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}; |
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static const char * const mips_gpr_names_newabi[32] = |
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{ |
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"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
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"a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", |
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"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
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"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" |
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}; |
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static const char * const mips_fpr_names_numeric[32] = |
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{ |
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"$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", |
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"$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", |
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"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", |
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"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" |
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}; |
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static const char * const mips_fpr_names_32[32] = |
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{ |
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"fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", |
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"ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", |
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"ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", |
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"fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" |
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}; |
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static const char * const mips_fpr_names_n32[32] = |
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{ |
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"fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", |
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"ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", |
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"fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", |
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"fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" |
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}; |
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static const char * const mips_fpr_names_64[32] = |
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{ |
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"fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", |
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"ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", |
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"fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", |
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"fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" |
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}; |
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static const char * const mips_cp0_names_numeric[32] = |
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{ |
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"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", |
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"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", |
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"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", |
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"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" |
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}; |
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static const char * const mips_cp0_names_mips3264[32] = |
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{ |
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"c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", |
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"c0_context", "c0_pagemask", "c0_wired", "$7", |
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"c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", |
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"c0_status", "c0_cause", "c0_epc", "c0_prid", |
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"c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", |
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"c0_xcontext", "$21", "$22", "c0_debug", |
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"c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", |
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"c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", |
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}; |
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static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = |
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{ |
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{ 16, 1, "c0_config1" }, |
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{ 16, 2, "c0_config2" }, |
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{ 16, 3, "c0_config3" }, |
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{ 18, 1, "c0_watchlo,1" }, |
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{ 18, 2, "c0_watchlo,2" }, |
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{ 18, 3, "c0_watchlo,3" }, |
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{ 18, 4, "c0_watchlo,4" }, |
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{ 18, 5, "c0_watchlo,5" }, |
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{ 18, 6, "c0_watchlo,6" }, |
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{ 18, 7, "c0_watchlo,7" }, |
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{ 19, 1, "c0_watchhi,1" }, |
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{ 19, 2, "c0_watchhi,2" }, |
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{ 19, 3, "c0_watchhi,3" }, |
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{ 19, 4, "c0_watchhi,4" }, |
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{ 19, 5, "c0_watchhi,5" }, |
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{ 19, 6, "c0_watchhi,6" }, |
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{ 19, 7, "c0_watchhi,7" }, |
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{ 25, 1, "c0_perfcnt,1" }, |
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{ 25, 2, "c0_perfcnt,2" }, |
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{ 25, 3, "c0_perfcnt,3" }, |
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{ 25, 4, "c0_perfcnt,4" }, |
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{ 25, 5, "c0_perfcnt,5" }, |
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{ 25, 6, "c0_perfcnt,6" }, |
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{ 25, 7, "c0_perfcnt,7" }, |
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{ 27, 1, "c0_cacheerr,1" }, |
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{ 27, 2, "c0_cacheerr,2" }, |
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{ 27, 3, "c0_cacheerr,3" }, |
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{ 28, 1, "c0_datalo" }, |
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{ 29, 1, "c0_datahi" } |
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}; |
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static const char * const mips_cp0_names_mips3264r2[32] = |
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{ |
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"c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", |
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"c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", |
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"c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", |
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"c0_status", "c0_cause", "c0_epc", "c0_prid", |
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"c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", |
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"c0_xcontext", "$21", "$22", "c0_debug", |
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"c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", |
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"c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", |
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}; |
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static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = |
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{ |
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{ 4, 1, "c0_contextconfig" }, |
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{ 0, 1, "c0_mvpcontrol" }, |
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{ 0, 2, "c0_mvpconf0" }, |
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{ 0, 3, "c0_mvpconf1" }, |
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{ 1, 1, "c0_vpecontrol" }, |
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{ 1, 2, "c0_vpeconf0" }, |
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{ 1, 3, "c0_vpeconf1" }, |
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{ 1, 4, "c0_yqmask" }, |
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{ 1, 5, "c0_vpeschedule" }, |
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{ 1, 6, "c0_vpeschefback" }, |
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{ 2, 1, "c0_tcstatus" }, |
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{ 2, 2, "c0_tcbind" }, |
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{ 2, 3, "c0_tcrestart" }, |
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{ 2, 4, "c0_tchalt" }, |
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{ 2, 5, "c0_tccontext" }, |
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{ 2, 6, "c0_tcschedule" }, |
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{ 2, 7, "c0_tcschefback" }, |
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{ 5, 1, "c0_pagegrain" }, |
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{ 6, 1, "c0_srsconf0" }, |
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{ 6, 2, "c0_srsconf1" }, |
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{ 6, 3, "c0_srsconf2" }, |
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{ 6, 4, "c0_srsconf3" }, |
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{ 6, 5, "c0_srsconf4" }, |
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{ 12, 1, "c0_intctl" }, |
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{ 12, 2, "c0_srsctl" }, |
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{ 12, 3, "c0_srsmap" }, |
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{ 15, 1, "c0_ebase" }, |
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{ 16, 1, "c0_config1" }, |
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{ 16, 2, "c0_config2" }, |
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{ 16, 3, "c0_config3" }, |
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{ 18, 1, "c0_watchlo,1" }, |
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{ 18, 2, "c0_watchlo,2" }, |
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{ 18, 3, "c0_watchlo,3" }, |
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{ 18, 4, "c0_watchlo,4" }, |
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{ 18, 5, "c0_watchlo,5" }, |
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{ 18, 6, "c0_watchlo,6" }, |
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{ 18, 7, "c0_watchlo,7" }, |
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{ 19, 1, "c0_watchhi,1" }, |
| 273 |
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{ 19, 2, "c0_watchhi,2" }, |
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{ 19, 3, "c0_watchhi,3" }, |
| 275 |
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{ 19, 4, "c0_watchhi,4" }, |
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{ 19, 5, "c0_watchhi,5" }, |
| 277 |
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{ 19, 6, "c0_watchhi,6" }, |
| 278 |
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{ 19, 7, "c0_watchhi,7" }, |
| 279 |
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{ 23, 1, "c0_tracecontrol" }, |
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{ 23, 2, "c0_tracecontrol2" }, |
| 281 |
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{ 23, 3, "c0_usertracedata" }, |
| 282 |
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{ 23, 4, "c0_tracebpc" }, |
| 283 |
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{ 25, 1, "c0_perfcnt,1" }, |
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{ 25, 2, "c0_perfcnt,2" }, |
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{ 25, 3, "c0_perfcnt,3" }, |
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{ 25, 4, "c0_perfcnt,4" }, |
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{ 25, 5, "c0_perfcnt,5" }, |
| 288 |
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{ 25, 6, "c0_perfcnt,6" }, |
| 289 |
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{ 25, 7, "c0_perfcnt,7" }, |
| 290 |
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{ 27, 1, "c0_cacheerr,1" }, |
| 291 |
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{ 27, 2, "c0_cacheerr,2" }, |
| 292 |
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{ 27, 3, "c0_cacheerr,3" }, |
| 293 |
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{ 28, 1, "c0_datalo" }, |
| 294 |
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{ 28, 2, "c0_taglo1" }, |
| 295 |
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{ 28, 3, "c0_datalo1" }, |
| 296 |
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{ 28, 4, "c0_taglo2" }, |
| 297 |
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{ 28, 5, "c0_datalo2" }, |
| 298 |
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{ 28, 6, "c0_taglo3" }, |
| 299 |
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{ 28, 7, "c0_datalo3" }, |
| 300 |
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{ 29, 1, "c0_datahi" }, |
| 301 |
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{ 29, 2, "c0_taghi1" }, |
| 302 |
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{ 29, 3, "c0_datahi1" }, |
| 303 |
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|
{ 29, 4, "c0_taghi2" }, |
| 304 |
|
|
{ 29, 5, "c0_datahi2" }, |
| 305 |
|
|
{ 29, 6, "c0_taghi3" }, |
| 306 |
|
|
{ 29, 7, "c0_datahi3" }, |
| 307 |
|
|
}; |
| 308 |
|
|
|
| 309 |
|
|
/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ |
| 310 |
|
|
static const char * const mips_cp0_names_sb1[32] = |
| 311 |
|
|
{ |
| 312 |
|
|
"c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", |
| 313 |
|
|
"c0_context", "c0_pagemask", "c0_wired", "$7", |
| 314 |
|
|
"c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", |
| 315 |
|
|
"c0_status", "c0_cause", "c0_epc", "c0_prid", |
| 316 |
|
|
"c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", |
| 317 |
|
|
"c0_xcontext", "$21", "$22", "c0_debug", |
| 318 |
|
|
"c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", |
| 319 |
|
|
"c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", |
| 320 |
|
|
}; |
| 321 |
|
|
|
| 322 |
|
|
static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = |
| 323 |
|
|
{ |
| 324 |
|
|
{ 16, 1, "c0_config1" }, |
| 325 |
|
|
{ 18, 1, "c0_watchlo,1" }, |
| 326 |
|
|
{ 19, 1, "c0_watchhi,1" }, |
| 327 |
|
|
{ 22, 0, "c0_perftrace" }, |
| 328 |
|
|
{ 23, 3, "c0_edebug" }, |
| 329 |
|
|
{ 25, 1, "c0_perfcnt,1" }, |
| 330 |
|
|
{ 25, 2, "c0_perfcnt,2" }, |
| 331 |
|
|
{ 25, 3, "c0_perfcnt,3" }, |
| 332 |
|
|
{ 25, 4, "c0_perfcnt,4" }, |
| 333 |
|
|
{ 25, 5, "c0_perfcnt,5" }, |
| 334 |
|
|
{ 25, 6, "c0_perfcnt,6" }, |
| 335 |
|
|
{ 25, 7, "c0_perfcnt,7" }, |
| 336 |
|
|
{ 26, 1, "c0_buserr_pa" }, |
| 337 |
|
|
{ 27, 1, "c0_cacheerr_d" }, |
| 338 |
|
|
{ 27, 3, "c0_cacheerr_d_pa" }, |
| 339 |
|
|
{ 28, 1, "c0_datalo_i" }, |
| 340 |
|
|
{ 28, 2, "c0_taglo_d" }, |
| 341 |
|
|
{ 28, 3, "c0_datalo_d" }, |
| 342 |
|
|
{ 29, 1, "c0_datahi_i" }, |
| 343 |
|
|
{ 29, 2, "c0_taghi_d" }, |
| 344 |
|
|
{ 29, 3, "c0_datahi_d" }, |
| 345 |
|
|
}; |
| 346 |
|
|
|
| 347 |
|
|
static const char * const mips_hwr_names_numeric[32] = |
| 348 |
|
|
{ |
| 349 |
|
|
"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", |
| 350 |
|
|
"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", |
| 351 |
|
|
"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", |
| 352 |
|
|
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" |
| 353 |
|
|
}; |
| 354 |
|
|
|
| 355 |
|
|
static const char * const mips_hwr_names_mips3264r2[32] = |
| 356 |
|
|
{ |
| 357 |
|
|
"hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", |
| 358 |
|
|
"$4", "$5", "$6", "$7", |
| 359 |
|
|
"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", |
| 360 |
|
|
"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", |
| 361 |
|
|
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" |
| 362 |
|
|
}; |
| 363 |
|
|
|
| 364 |
|
|
struct mips_abi_choice |
| 365 |
|
|
{ |
| 366 |
|
|
const char * name; |
| 367 |
|
|
const char * const *gpr_names; |
| 368 |
|
|
const char * const *fpr_names; |
| 369 |
|
|
}; |
| 370 |
|
|
|
| 371 |
|
|
struct mips_abi_choice mips_abi_choices[] = |
| 372 |
|
|
{ |
| 373 |
|
|
{ "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, |
| 374 |
|
|
{ "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, |
| 375 |
|
|
{ "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, |
| 376 |
|
|
{ "64", mips_gpr_names_newabi, mips_fpr_names_64 }, |
| 377 |
|
|
}; |
| 378 |
|
|
|
| 379 |
|
|
struct mips_arch_choice |
| 380 |
|
|
{ |
| 381 |
|
|
const char *name; |
| 382 |
|
|
int bfd_mach_valid; |
| 383 |
|
|
unsigned long bfd_mach; |
| 384 |
|
|
int processor; |
| 385 |
|
|
int isa; |
| 386 |
|
|
const char * const *cp0_names; |
| 387 |
|
|
const struct mips_cp0sel_name *cp0sel_names; |
| 388 |
|
|
unsigned int cp0sel_names_len; |
| 389 |
|
|
const char * const *hwr_names; |
| 390 |
|
|
}; |
| 391 |
|
|
|
| 392 |
|
|
const struct mips_arch_choice mips_arch_choices[] = |
| 393 |
|
|
{ |
| 394 |
|
|
{ "numeric", 0, 0, 0, 0, |
| 395 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 396 |
|
|
|
| 397 |
|
|
{ "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, |
| 398 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 399 |
|
|
{ "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, |
| 400 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 401 |
|
|
{ "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, |
| 402 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 403 |
|
|
{ "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, |
| 404 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 405 |
|
|
{ "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, |
| 406 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 407 |
|
|
{ "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, |
| 408 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 409 |
|
|
{ "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, |
| 410 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 411 |
|
|
{ "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, |
| 412 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 413 |
|
|
{ "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, |
| 414 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 415 |
|
|
{ "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, |
| 416 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 417 |
|
|
{ "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, |
| 418 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 419 |
|
|
{ "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, |
| 420 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 421 |
|
|
{ "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, |
| 422 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 423 |
|
|
{ "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, |
| 424 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 425 |
|
|
{ "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, |
| 426 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 427 |
|
|
{ "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, |
| 428 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 429 |
|
|
{ "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, |
| 430 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 431 |
|
|
{ "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, |
| 432 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 433 |
|
|
{ "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, |
| 434 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 435 |
|
|
{ "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, |
| 436 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 437 |
|
|
{ "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, |
| 438 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 439 |
|
|
|
| 440 |
|
|
/* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. |
| 441 |
|
|
Note that MIPS-3D and MDMX are not applicable to MIPS32. (See |
| 442 |
|
|
_MIPS32 Architecture For Programmers Volume I: Introduction to the |
| 443 |
|
|
MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), |
| 444 |
|
|
page 1. */ |
| 445 |
|
|
{ "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, |
| 446 |
|
|
ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS, |
| 447 |
|
|
mips_cp0_names_mips3264, |
| 448 |
|
|
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), |
| 449 |
|
|
mips_hwr_names_numeric }, |
| 450 |
|
|
|
| 451 |
|
|
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, |
| 452 |
|
|
(ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_MIPS3D |
| 453 |
|
|
| INSN_MT), |
| 454 |
|
|
mips_cp0_names_mips3264r2, |
| 455 |
|
|
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), |
| 456 |
|
|
mips_hwr_names_mips3264r2 }, |
| 457 |
|
|
|
| 458 |
|
|
/* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ |
| 459 |
|
|
{ "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, |
| 460 |
|
|
ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, |
| 461 |
|
|
mips_cp0_names_mips3264, |
| 462 |
|
|
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), |
| 463 |
|
|
mips_hwr_names_numeric }, |
| 464 |
|
|
|
| 465 |
|
|
{ "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, |
| 466 |
|
|
(ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSP64 |
| 467 |
|
|
| INSN_MT | INSN_MDMX), |
| 468 |
|
|
mips_cp0_names_mips3264r2, |
| 469 |
|
|
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), |
| 470 |
|
|
mips_hwr_names_mips3264r2 }, |
| 471 |
|
|
|
| 472 |
|
|
{ "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, |
| 473 |
|
|
ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, |
| 474 |
|
|
mips_cp0_names_sb1, |
| 475 |
|
|
mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), |
| 476 |
|
|
mips_hwr_names_numeric }, |
| 477 |
|
|
|
| 478 |
|
|
/* This entry, mips16, is here only for ISA/processor selection; do |
| 479 |
|
|
not print its name. */ |
| 480 |
|
|
{ "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16, |
| 481 |
|
|
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |
| 482 |
|
|
}; |
| 483 |
|
|
|
| 484 |
|
|
/* ISA and processor type to disassemble for, and register names to use. |
| 485 |
|
|
set_default_mips_dis_options and parse_mips_dis_options fill in these |
| 486 |
|
|
values. */ |
| 487 |
|
|
static int mips_processor; |
| 488 |
|
|
static int mips_isa; |
| 489 |
|
|
static const char * const *mips_gpr_names; |
| 490 |
|
|
static const char * const *mips_fpr_names; |
| 491 |
|
|
static const char * const *mips_cp0_names; |
| 492 |
|
|
static const struct mips_cp0sel_name *mips_cp0sel_names; |
| 493 |
|
|
static int mips_cp0sel_names_len; |
| 494 |
|
|
static const char * const *mips_hwr_names; |
| 495 |
|
|
|
| 496 |
|
|
/* Other options */ |
| 497 |
|
|
static int no_aliases; /* If set disassemble as most general inst. */ |
| 498 |
|
|
|
| 499 |
|
|
static const struct mips_abi_choice * |
| 500 |
|
|
choose_abi_by_name (const char *name, unsigned int namelen) |
| 501 |
|
|
{ |
| 502 |
|
|
const struct mips_abi_choice *c; |
| 503 |
|
|
unsigned int i; |
| 504 |
|
|
|
| 505 |
|
|
for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) |
| 506 |
|
|
if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 |
| 507 |
|
|
&& strlen (mips_abi_choices[i].name) == namelen) |
| 508 |
|
|
c = &mips_abi_choices[i]; |
| 509 |
|
|
|
| 510 |
|
|
return c; |
| 511 |
|
|
} |
| 512 |
|
|
|
| 513 |
|
|
static const struct mips_arch_choice * |
| 514 |
|
|
choose_arch_by_name (const char *name, unsigned int namelen) |
| 515 |
|
|
{ |
| 516 |
|
|
const struct mips_arch_choice *c = NULL; |
| 517 |
|
|
unsigned int i; |
| 518 |
|
|
|
| 519 |
|
|
for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) |
| 520 |
|
|
if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 |
| 521 |
|
|
&& strlen (mips_arch_choices[i].name) == namelen) |
| 522 |
|
|
c = &mips_arch_choices[i]; |
| 523 |
|
|
|
| 524 |
|
|
return c; |
| 525 |
|
|
} |
| 526 |
|
|
|
| 527 |
|
|
static const struct mips_arch_choice * |
| 528 |
|
|
choose_arch_by_number (unsigned long mach) |
| 529 |
|
|
{ |
| 530 |
|
|
static unsigned long hint_bfd_mach; |
| 531 |
|
|
static const struct mips_arch_choice *hint_arch_choice; |
| 532 |
|
|
const struct mips_arch_choice *c; |
| 533 |
|
|
unsigned int i; |
| 534 |
|
|
|
| 535 |
|
|
/* We optimize this because even if the user specifies no |
| 536 |
|
|
flags, this will be done for every instruction! */ |
| 537 |
|
|
if (hint_bfd_mach == mach |
| 538 |
|
|
&& hint_arch_choice != NULL |
| 539 |
|
|
&& hint_arch_choice->bfd_mach == hint_bfd_mach) |
| 540 |
|
|
return hint_arch_choice; |
| 541 |
|
|
|
| 542 |
|
|
for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) |
| 543 |
|
|
{ |
| 544 |
|
|
if (mips_arch_choices[i].bfd_mach_valid |
| 545 |
|
|
&& mips_arch_choices[i].bfd_mach == mach) |
| 546 |
|
|
{ |
| 547 |
|
|
c = &mips_arch_choices[i]; |
| 548 |
|
|
hint_bfd_mach = mach; |
| 549 |
|
|
hint_arch_choice = c; |
| 550 |
|
|
} |
| 551 |
|
|
} |
| 552 |
|
|
return c; |
| 553 |
|
|
} |
| 554 |
|
|
|
| 555 |
|
|
/* Check if the object uses NewABI conventions. */ |
| 556 |
|
|
|
| 557 |
|
|
#if SYMTAB_AVAILABLE |
| 558 |
|
|
static int |
| 559 |
|
|
is_newabi (Elf_Internal_Ehdr *header) |
| 560 |
|
|
{ |
| 561 |
|
|
/* There are no old-style ABIs which use 64-bit ELF. */ |
| 562 |
|
|
if (header->e_ident[EI_CLASS] == ELFCLASS64) |
| 563 |
|
|
return 1; |
| 564 |
|
|
|
| 565 |
|
|
/* If a 32-bit ELF file, n32 is a new-style ABI. */ |
| 566 |
|
|
if ((header->e_flags & EF_MIPS_ABI2) != 0) |
| 567 |
|
|
return 1; |
| 568 |
|
|
|
| 569 |
|
|
return 0; |
| 570 |
|
|
} |
| 571 |
|
|
#endif |
| 572 |
|
|
|
| 573 |
|
|
static void |
| 574 |
|
|
set_default_mips_dis_options (struct disassemble_info *info) |
| 575 |
|
|
{ |
| 576 |
|
|
const struct mips_arch_choice *chosen_arch; |
| 577 |
|
|
|
| 578 |
|
|
/* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names, |
| 579 |
|
|
and numeric FPR, CP0 register, and HWR names. */ |
| 580 |
|
|
mips_isa = ISA_MIPS3; |
| 581 |
|
|
mips_processor = CPU_R3000; |
| 582 |
|
|
mips_gpr_names = mips_gpr_names_oldabi; |
| 583 |
|
|
mips_fpr_names = mips_fpr_names_numeric; |
| 584 |
|
|
mips_cp0_names = mips_cp0_names_numeric; |
| 585 |
|
|
mips_cp0sel_names = NULL; |
| 586 |
|
|
mips_cp0sel_names_len = 0; |
| 587 |
|
|
mips_hwr_names = mips_hwr_names_numeric; |
| 588 |
|
|
no_aliases = 0; |
| 589 |
|
|
|
| 590 |
|
|
/* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ |
| 591 |
|
|
#if SYMTAB_AVAILABLE |
| 592 |
|
|
if (info->flavour == bfd_target_elf_flavour && info->section != NULL) |
| 593 |
|
|
{ |
| 594 |
|
|
Elf_Internal_Ehdr *header; |
| 595 |
|
|
|
| 596 |
|
|
header = elf_elfheader (info->section->owner); |
| 597 |
|
|
if (is_newabi (header)) |
| 598 |
|
|
mips_gpr_names = mips_gpr_names_newabi; |
| 599 |
|
|
} |
| 600 |
|
|
#endif |
| 601 |
|
|
|
| 602 |
|
|
/* Set ISA, architecture, and cp0 register names as best we can. */ |
| 603 |
|
|
#if ! SYMTAB_AVAILABLE && 0 |
| 604 |
|
|
/* This is running out on a target machine, not in a host tool. |
| 605 |
|
|
FIXME: Where does mips_target_info come from? */ |
| 606 |
|
|
mips_processor = mips_target_info.processor; |
| 607 |
|
|
mips_isa = mips_target_info.isa; |
| 608 |
|
|
#else |
| 609 |
|
|
chosen_arch = choose_arch_by_number (info->mach); |
| 610 |
|
|
if (chosen_arch != NULL) |
| 611 |
|
|
{ |
| 612 |
|
|
mips_processor = chosen_arch->processor; |
| 613 |
|
|
mips_isa = chosen_arch->isa; |
| 614 |
|
|
mips_cp0_names = chosen_arch->cp0_names; |
| 615 |
|
|
mips_cp0sel_names = chosen_arch->cp0sel_names; |
| 616 |
|
|
mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; |
| 617 |
|
|
mips_hwr_names = chosen_arch->hwr_names; |
| 618 |
|
|
} |
| 619 |
|
|
#endif |
| 620 |
|
|
} |
| 621 |
|
|
|
| 622 |
|
|
static void |
| 623 |
|
|
parse_mips_dis_option (const char *option, unsigned int len) |
| 624 |
|
|
{ |
| 625 |
|
|
unsigned int i, optionlen, vallen; |
| 626 |
|
|
const char *val; |
| 627 |
|
|
const struct mips_abi_choice *chosen_abi; |
| 628 |
|
|
const struct mips_arch_choice *chosen_arch; |
| 629 |
|
|
|
| 630 |
|
|
/* Try to match options that are simple flags */ |
| 631 |
|
|
if (CONST_STRNEQ (option, "no-aliases")) |
| 632 |
|
|
{ |
| 633 |
|
|
no_aliases = 1; |
| 634 |
|
|
return; |
| 635 |
|
|
} |
| 636 |
|
|
|
| 637 |
|
|
/* Look for the = that delimits the end of the option name. */ |
| 638 |
|
|
for (i = 0; i < len; i++) |
| 639 |
|
|
if (option[i] == '=') |
| 640 |
|
|
break; |
| 641 |
|
|
|
| 642 |
|
|
if (i == 0) /* Invalid option: no name before '='. */ |
| 643 |
|
|
return; |
| 644 |
|
|
if (i == len) /* Invalid option: no '='. */ |
| 645 |
|
|
return; |
| 646 |
|
|
if (i == (len - 1)) /* Invalid option: no value after '='. */ |
| 647 |
|
|
return; |
| 648 |
|
|
|
| 649 |
|
|
optionlen = i; |
| 650 |
|
|
val = option + (optionlen + 1); |
| 651 |
|
|
vallen = len - (optionlen + 1); |
| 652 |
|
|
|
| 653 |
|
|
if (strncmp ("gpr-names", option, optionlen) == 0 |
| 654 |
|
|
&& strlen ("gpr-names") == optionlen) |
| 655 |
|
|
{ |
| 656 |
|
|
chosen_abi = choose_abi_by_name (val, vallen); |
| 657 |
|
|
if (chosen_abi != NULL) |
| 658 |
|
|
mips_gpr_names = chosen_abi->gpr_names; |
| 659 |
|
|
return; |
| 660 |
|
|
} |
| 661 |
|
|
|
| 662 |
|
|
if (strncmp ("fpr-names", option, optionlen) == 0 |
| 663 |
|
|
&& strlen ("fpr-names") == optionlen) |
| 664 |
|
|
{ |
| 665 |
|
|
chosen_abi = choose_abi_by_name (val, vallen); |
| 666 |
|
|
if (chosen_abi != NULL) |
| 667 |
|
|
mips_fpr_names = chosen_abi->fpr_names; |
| 668 |
|
|
return; |
| 669 |
|
|
} |
| 670 |
|
|
|
| 671 |
|
|
if (strncmp ("cp0-names", option, optionlen) == 0 |
| 672 |
|
|
&& strlen ("cp0-names") == optionlen) |
| 673 |
|
|
{ |
| 674 |
|
|
chosen_arch = choose_arch_by_name (val, vallen); |
| 675 |
|
|
if (chosen_arch != NULL) |
| 676 |
|
|
{ |
| 677 |
|
|
mips_cp0_names = chosen_arch->cp0_names; |
| 678 |
|
|
mips_cp0sel_names = chosen_arch->cp0sel_names; |
| 679 |
|
|
mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; |
| 680 |
|
|
} |
| 681 |
|
|
return; |
| 682 |
|
|
} |
| 683 |
|
|
|
| 684 |
|
|
if (strncmp ("hwr-names", option, optionlen) == 0 |
| 685 |
|
|
&& strlen ("hwr-names") == optionlen) |
| 686 |
|
|
{ |
| 687 |
|
|
chosen_arch = choose_arch_by_name (val, vallen); |
| 688 |
|
|
if (chosen_arch != NULL) |
| 689 |
|
|
mips_hwr_names = chosen_arch->hwr_names; |
| 690 |
|
|
return; |
| 691 |
|
|
} |
| 692 |
|
|
|
| 693 |
|
|
if (strncmp ("reg-names", option, optionlen) == 0 |
| 694 |
|
|
&& strlen ("reg-names") == optionlen) |
| 695 |
|
|
{ |
| 696 |
|
|
/* We check both ABI and ARCH here unconditionally, so |
| 697 |
|
|
that "numeric" will do the desirable thing: select |
| 698 |
|
|
numeric register names for all registers. Other than |
| 699 |
|
|
that, a given name probably won't match both. */ |
| 700 |
|
|
chosen_abi = choose_abi_by_name (val, vallen); |
| 701 |
|
|
if (chosen_abi != NULL) |
| 702 |
|
|
{ |
| 703 |
|
|
mips_gpr_names = chosen_abi->gpr_names; |
| 704 |
|
|
mips_fpr_names = chosen_abi->fpr_names; |
| 705 |
|
|
} |
| 706 |
|
|
chosen_arch = choose_arch_by_name (val, vallen); |
| 707 |
|
|
if (chosen_arch != NULL) |
| 708 |
|
|
{ |
| 709 |
|
|
mips_cp0_names = chosen_arch->cp0_names; |
| 710 |
|
|
mips_cp0sel_names = chosen_arch->cp0sel_names; |
| 711 |
|
|
mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; |
| 712 |
|
|
mips_hwr_names = chosen_arch->hwr_names; |
| 713 |
|
|
} |
| 714 |
|
|
return; |
| 715 |
|
|
} |
| 716 |
|
|
|
| 717 |
|
|
/* Invalid option. */ |
| 718 |
|
|
} |
| 719 |
|
|
|
| 720 |
|
|
static void |
| 721 |
|
|
parse_mips_dis_options (const char *options) |
| 722 |
|
|
{ |
| 723 |
|
|
const char *option_end; |
| 724 |
|
|
|
| 725 |
|
|
if (options == NULL) |
| 726 |
|
|
return; |
| 727 |
|
|
|
| 728 |
|
|
while (*options != '\0') |
| 729 |
|
|
{ |
| 730 |
|
|
/* Skip empty options. */ |
| 731 |
|
|
if (*options == ',') |
| 732 |
|
|
{ |
| 733 |
|
|
options++; |
| 734 |
|
|
continue; |
| 735 |
|
|
} |
| 736 |
|
|
|
| 737 |
|
|
/* We know that *options is neither NUL or a comma. */ |
| 738 |
|
|
option_end = options + 1; |
| 739 |
|
|
while (*option_end != ',' && *option_end != '\0') |
| 740 |
|
|
option_end++; |
| 741 |
|
|
|
| 742 |
|
|
parse_mips_dis_option (options, option_end - options); |
| 743 |
|
|
|
| 744 |
|
|
/* Go on to the next one. If option_end points to a comma, it |
| 745 |
|
|
will be skipped above. */ |
| 746 |
|
|
options = option_end; |
| 747 |
|
|
} |
| 748 |
|
|
} |
| 749 |
|
|
|
| 750 |
|
|
static const struct mips_cp0sel_name * |
| 751 |
|
|
lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, |
| 752 |
|
|
unsigned int len, |
| 753 |
|
|
unsigned int cp0reg, |
| 754 |
|
|
unsigned int sel) |
| 755 |
|
|
{ |
| 756 |
|
|
unsigned int i; |
| 757 |
|
|
|
| 758 |
|
|
for (i = 0; i < len; i++) |
| 759 |
|
|
if (names[i].cp0reg == cp0reg && names[i].sel == sel) |
| 760 |
|
|
return &names[i]; |
| 761 |
|
|
return NULL; |
| 762 |
|
|
} |
| 763 |
|
|
|
| 764 |
|
|
/* Print insn arguments for 32/64-bit code. */ |
| 765 |
|
|
|
| 766 |
|
|
static void |
| 767 |
|
|
print_insn_args (const char *d, |
| 768 |
|
|
register unsigned long int l, |
| 769 |
|
|
bfd_vma pc, |
| 770 |
|
|
struct disassemble_info *info, |
| 771 |
|
|
const struct mips_opcode *opp) |
| 772 |
|
|
{ |
| 773 |
|
|
int op, delta; |
| 774 |
|
|
unsigned int lsb, msb, msbd; |
| 775 |
|
|
|
| 776 |
|
|
lsb = 0; |
| 777 |
|
|
|
| 778 |
|
|
for (; *d != '\0'; d++) |
| 779 |
|
|
{ |
| 780 |
|
|
switch (*d) |
| 781 |
|
|
{ |
| 782 |
|
|
case ',': |
| 783 |
|
|
case '(': |
| 784 |
|
|
case ')': |
| 785 |
|
|
case '[': |
| 786 |
|
|
case ']': |
| 787 |
|
|
(*info->fprintf_func) (info->stream, "%c", *d); |
| 788 |
|
|
break; |
| 789 |
|
|
|
| 790 |
|
|
case '+': |
| 791 |
|
|
/* Extension character; switch for second char. */ |
| 792 |
|
|
d++; |
| 793 |
|
|
switch (*d) |
| 794 |
|
|
{ |
| 795 |
|
|
case '\0': |
| 796 |
|
|
/* xgettext:c-format */ |
| 797 |
|
|
(*info->fprintf_func) (info->stream, |
| 798 |
|
|
_("# internal error, incomplete extension sequence (+)")); |
| 799 |
|
|
return; |
| 800 |
|
|
|
| 801 |
|
|
case 'A': |
| 802 |
|
|
lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT; |
| 803 |
|
|
(*info->fprintf_func) (info->stream, "0x%x", lsb); |
| 804 |
|
|
break; |
| 805 |
|
|
|
| 806 |
|
|
case 'B': |
| 807 |
|
|
msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB; |
| 808 |
|
|
(*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); |
| 809 |
|
|
break; |
| 810 |
|
|
|
| 811 |
|
|
case '1': |
| 812 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", |
| 813 |
|
|
(l >> OP_SH_UDI1) & OP_MASK_UDI1); |
| 814 |
|
|
break; |
| 815 |
|
|
|
| 816 |
|
|
case '2': |
| 817 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", |
| 818 |
|
|
(l >> OP_SH_UDI2) & OP_MASK_UDI2); |
| 819 |
|
|
break; |
| 820 |
|
|
|
| 821 |
|
|
case '3': |
| 822 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", |
| 823 |
|
|
(l >> OP_SH_UDI3) & OP_MASK_UDI3); |
| 824 |
|
|
break; |
| 825 |
|
|
|
| 826 |
|
|
case '4': |
| 827 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", |
| 828 |
|
|
(l >> OP_SH_UDI4) & OP_MASK_UDI4); |
| 829 |
|
|
break; |
| 830 |
|
|
|
| 831 |
|
|
case 'C': |
| 832 |
|
|
case 'H': |
| 833 |
|
|
msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD; |
| 834 |
|
|
(*info->fprintf_func) (info->stream, "0x%x", msbd + 1); |
| 835 |
|
|
break; |
| 836 |
|
|
|
| 837 |
|
|
case 'D': |
| 838 |
|
|
{ |
| 839 |
|
|
const struct mips_cp0sel_name *n; |
| 840 |
|
|
unsigned int cp0reg, sel; |
| 841 |
|
|
|
| 842 |
|
|
cp0reg = (l >> OP_SH_RD) & OP_MASK_RD; |
| 843 |
|
|
sel = (l >> OP_SH_SEL) & OP_MASK_SEL; |
| 844 |
|
|
|
| 845 |
|
|
/* CP0 register including 'sel' code for mtcN (et al.), to be |
| 846 |
|
|
printed textually if known. If not known, print both |
| 847 |
|
|
CP0 register name and sel numerically since CP0 register |
| 848 |
|
|
with sel 0 may have a name unrelated to register being |
| 849 |
|
|
printed. */ |
| 850 |
|
|
n = lookup_mips_cp0sel_name(mips_cp0sel_names, |
| 851 |
|
|
mips_cp0sel_names_len, cp0reg, sel); |
| 852 |
|
|
if (n != NULL) |
| 853 |
|
|
(*info->fprintf_func) (info->stream, "%s", n->name); |
| 854 |
|
|
else |
| 855 |
|
|
(*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); |
| 856 |
|
|
break; |
| 857 |
|
|
} |
| 858 |
|
|
|
| 859 |
|
|
case 'E': |
| 860 |
|
|
lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32; |
| 861 |
|
|
(*info->fprintf_func) (info->stream, "0x%x", lsb); |
| 862 |
|
|
break; |
| 863 |
|
|
|
| 864 |
|
|
case 'F': |
| 865 |
|
|
msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32; |
| 866 |
|
|
(*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); |
| 867 |
|
|
break; |
| 868 |
|
|
|
| 869 |
|
|
case 'G': |
| 870 |
|
|
msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32; |
| 871 |
|
|
(*info->fprintf_func) (info->stream, "0x%x", msbd + 1); |
| 872 |
|
|
break; |
| 873 |
|
|
|
| 874 |
|
|
case 't': /* Coprocessor 0 reg name */ |
| 875 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 876 |
|
|
mips_cp0_names[(l >> OP_SH_RT) & |
| 877 |
|
|
OP_MASK_RT]); |
| 878 |
|
|
break; |
| 879 |
|
|
|
| 880 |
|
|
case 'T': /* Coprocessor 0 reg name */ |
| 881 |
|
|
{ |
| 882 |
|
|
const struct mips_cp0sel_name *n; |
| 883 |
|
|
unsigned int cp0reg, sel; |
| 884 |
|
|
|
| 885 |
|
|
cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; |
| 886 |
|
|
sel = (l >> OP_SH_SEL) & OP_MASK_SEL; |
| 887 |
|
|
|
| 888 |
|
|
/* CP0 register including 'sel' code for mftc0, to be |
| 889 |
|
|
printed textually if known. If not known, print both |
| 890 |
|
|
CP0 register name and sel numerically since CP0 register |
| 891 |
|
|
with sel 0 may have a name unrelated to register being |
| 892 |
|
|
printed. */ |
| 893 |
|
|
n = lookup_mips_cp0sel_name(mips_cp0sel_names, |
| 894 |
|
|
mips_cp0sel_names_len, cp0reg, sel); |
| 895 |
|
|
if (n != NULL) |
| 896 |
|
|
(*info->fprintf_func) (info->stream, "%s", n->name); |
| 897 |
|
|
else |
| 898 |
|
|
(*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); |
| 899 |
|
|
break; |
| 900 |
|
|
} |
| 901 |
|
|
|
| 902 |
|
|
default: |
| 903 |
|
|
/* xgettext:c-format */ |
| 904 |
|
|
(*info->fprintf_func) (info->stream, |
| 905 |
|
|
_("# internal error, undefined extension sequence (+%c)"), |
| 906 |
|
|
*d); |
| 907 |
|
|
return; |
| 908 |
|
|
} |
| 909 |
|
|
break; |
| 910 |
|
|
|
| 911 |
|
|
case '3': |
| 912 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", |
| 913 |
|
|
(l >> OP_SH_SA3) & OP_MASK_SA3); |
| 914 |
|
|
break; |
| 915 |
|
|
|
| 916 |
|
|
case '4': |
| 917 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", |
| 918 |
|
|
(l >> OP_SH_SA4) & OP_MASK_SA4); |
| 919 |
|
|
break; |
| 920 |
|
|
|
| 921 |
|
|
case '5': |
| 922 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", |
| 923 |
|
|
(l >> OP_SH_IMM8) & OP_MASK_IMM8); |
| 924 |
|
|
break; |
| 925 |
|
|
|
| 926 |
|
|
case '6': |
| 927 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", |
| 928 |
|
|
(l >> OP_SH_RS) & OP_MASK_RS); |
| 929 |
|
|
break; |
| 930 |
|
|
|
| 931 |
|
|
case '7': |
| 932 |
|
|
(*info->fprintf_func) (info->stream, "$ac%ld", |
| 933 |
|
|
(l >> OP_SH_DSPACC) & OP_MASK_DSPACC); |
| 934 |
|
|
break; |
| 935 |
|
|
|
| 936 |
|
|
case '8': |
| 937 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", |
| 938 |
|
|
(l >> OP_SH_WRDSP) & OP_MASK_WRDSP); |
| 939 |
|
|
break; |
| 940 |
|
|
|
| 941 |
|
|
case '9': |
| 942 |
|
|
(*info->fprintf_func) (info->stream, "$ac%ld", |
| 943 |
|
|
(l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S); |
| 944 |
|
|
break; |
| 945 |
|
|
|
| 946 |
|
|
case '0': /* dsp 6-bit signed immediate in bit 20 */ |
| 947 |
|
|
delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT); |
| 948 |
|
|
if (delta & 0x20) /* test sign bit */ |
| 949 |
|
|
delta |= ~OP_MASK_DSPSFT; |
| 950 |
|
|
(*info->fprintf_func) (info->stream, "%d", delta); |
| 951 |
|
|
break; |
| 952 |
|
|
|
| 953 |
|
|
case ':': /* dsp 7-bit signed immediate in bit 19 */ |
| 954 |
|
|
delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7); |
| 955 |
|
|
if (delta & 0x40) /* test sign bit */ |
| 956 |
|
|
delta |= ~OP_MASK_DSPSFT_7; |
| 957 |
|
|
(*info->fprintf_func) (info->stream, "%d", delta); |
| 958 |
|
|
break; |
| 959 |
|
|
|
| 960 |
|
|
case '\'': |
| 961 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", |
| 962 |
|
|
(l >> OP_SH_RDDSP) & OP_MASK_RDDSP); |
| 963 |
|
|
break; |
| 964 |
|
|
|
| 965 |
|
|
case '@': /* dsp 10-bit signed immediate in bit 16 */ |
| 966 |
|
|
delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10); |
| 967 |
|
|
if (delta & 0x200) /* test sign bit */ |
| 968 |
|
|
delta |= ~OP_MASK_IMM10; |
| 969 |
|
|
(*info->fprintf_func) (info->stream, "%d", delta); |
| 970 |
|
|
break; |
| 971 |
|
|
|
| 972 |
|
|
case '!': |
| 973 |
|
|
(*info->fprintf_func) (info->stream, "%ld", |
| 974 |
|
|
(l >> OP_SH_MT_U) & OP_MASK_MT_U); |
| 975 |
|
|
break; |
| 976 |
|
|
|
| 977 |
|
|
case '$': |
| 978 |
|
|
(*info->fprintf_func) (info->stream, "%ld", |
| 979 |
|
|
(l >> OP_SH_MT_H) & OP_MASK_MT_H); |
| 980 |
|
|
break; |
| 981 |
|
|
|
| 982 |
|
|
case '*': |
| 983 |
|
|
(*info->fprintf_func) (info->stream, "$ac%ld", |
| 984 |
|
|
(l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T); |
| 985 |
|
|
break; |
| 986 |
|
|
|
| 987 |
|
|
case '&': |
| 988 |
|
|
(*info->fprintf_func) (info->stream, "$ac%ld", |
| 989 |
|
|
(l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D); |
| 990 |
|
|
break; |
| 991 |
|
|
|
| 992 |
|
|
case 'g': |
| 993 |
|
|
/* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */ |
| 994 |
|
|
(*info->fprintf_func) (info->stream, "$%ld", |
| 995 |
|
|
(l >> OP_SH_RD) & OP_MASK_RD); |
| 996 |
|
|
break; |
| 997 |
|
|
|
| 998 |
|
|
case 's': |
| 999 |
|
|
case 'b': |
| 1000 |
|
|
case 'r': |
| 1001 |
|
|
case 'v': |
| 1002 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 1003 |
|
|
mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]); |
| 1004 |
|
|
break; |
| 1005 |
|
|
|
| 1006 |
|
|
case 't': |
| 1007 |
|
|
case 'w': |
| 1008 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 1009 |
|
|
mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); |
| 1010 |
|
|
break; |
| 1011 |
|
|
|
| 1012 |
|
|
case 'i': |
| 1013 |
|
|
case 'u': |
| 1014 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", |
| 1015 |
|
|
(l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); |
| 1016 |
|
|
break; |
| 1017 |
|
|
|
| 1018 |
|
|
case 'j': /* Same as i, but sign-extended. */ |
| 1019 |
|
|
case 'o': |
| 1020 |
|
|
delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; |
| 1021 |
|
|
if (delta & 0x8000) |
| 1022 |
|
|
delta |= ~0xffff; |
| 1023 |
|
|
(*info->fprintf_func) (info->stream, "%d", |
| 1024 |
|
|
delta); |
| 1025 |
|
|
break; |
| 1026 |
|
|
|
| 1027 |
|
|
case 'h': |
| 1028 |
|
|
(*info->fprintf_func) (info->stream, "0x%x", |
| 1029 |
|
|
(unsigned int) ((l >> OP_SH_PREFX) |
| 1030 |
|
|
& OP_MASK_PREFX)); |
| 1031 |
|
|
break; |
| 1032 |
|
|
|
| 1033 |
|
|
case 'k': |
| 1034 |
|
|
(*info->fprintf_func) (info->stream, "0x%x", |
| 1035 |
|
|
(unsigned int) ((l >> OP_SH_CACHE) |
| 1036 |
|
|
& OP_MASK_CACHE)); |
| 1037 |
|
|
break; |
| 1038 |
|
|
|
| 1039 |
|
|
case 'a': |
| 1040 |
|
|
info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) |
| 1041 |
|
|
| (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); |
| 1042 |
|
|
/* For gdb disassembler, force odd address on jalx. */ |
| 1043 |
|
|
if (info->flavour == bfd_target_unknown_flavour |
| 1044 |
|
|
&& strcmp (opp->name, "jalx") == 0) |
| 1045 |
|
|
info->target |= 1; |
| 1046 |
|
|
(*info->print_address_func) (info->target, info); |
| 1047 |
|
|
break; |
| 1048 |
|
|
|
| 1049 |
|
|
case 'p': |
| 1050 |
|
|
/* Sign extend the displacement. */ |
| 1051 |
|
|
delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; |
| 1052 |
|
|
if (delta & 0x8000) |
| 1053 |
|
|
delta |= ~0xffff; |
| 1054 |
|
|
info->target = (delta << 2) + pc + INSNLEN; |
| 1055 |
|
|
(*info->print_address_func) (info->target, info); |
| 1056 |
|
|
break; |
| 1057 |
|
|
|
| 1058 |
|
|
case 'd': |
| 1059 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 1060 |
|
|
mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]); |
| 1061 |
|
|
break; |
| 1062 |
|
|
|
| 1063 |
|
|
case 'U': |
| 1064 |
|
|
{ |
| 1065 |
|
|
/* First check for both rd and rt being equal. */ |
| 1066 |
|
|
unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD; |
| 1067 |
|
|
if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) |
| 1068 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 1069 |
|
|
mips_gpr_names[reg]); |
| 1070 |
|
|
else |
| 1071 |
|
|
{ |
| 1072 |
|
|
/* If one is zero use the other. */ |
| 1073 |
|
|
if (reg == 0) |
| 1074 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 1075 |
|
|
mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); |
| 1076 |
|
|
else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) |
| 1077 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 1078 |
|
|
mips_gpr_names[reg]); |
| 1079 |
|
|
else /* Bogus, result depends on processor. */ |
| 1080 |
|
|
(*info->fprintf_func) (info->stream, "%s or %s", |
| 1081 |
|
|
mips_gpr_names[reg], |
| 1082 |
|
|
mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); |
| 1083 |
|
|
} |
| 1084 |
|
|
} |
| 1085 |
|
|
break; |
| 1086 |
|
|
|
| 1087 |
|
|
case 'z': |
| 1088 |
|
|
(*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); |
| 1089 |
|
|
break; |
| 1090 |
|
|
|
| 1091 |
|
|
case '<': |
| 1092 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", |
| 1093 |
|
|
(l >> OP_SH_SHAMT) & OP_MASK_SHAMT); |
| 1094 |
|
|
break; |
| 1095 |
|
|
|
| 1096 |
|
|
case 'c': |
| 1097 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", |
| 1098 |
|
|
(l >> OP_SH_CODE) & OP_MASK_CODE); |
| 1099 |
|
|
break; |
| 1100 |
|
|
|
| 1101 |
|
|
case 'q': |
| 1102 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", |
| 1103 |
|
|
(l >> OP_SH_CODE2) & OP_MASK_CODE2); |
| 1104 |
|
|
break; |
| 1105 |
|
|
|
| 1106 |
|
|
case 'C': |
| 1107 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", |
| 1108 |
|
|
(l >> OP_SH_COPZ) & OP_MASK_COPZ); |
| 1109 |
|
|
break; |
| 1110 |
|
|
|
| 1111 |
|
|
case 'B': |
| 1112 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", |
| 1113 |
|
|
|
| 1114 |
|
|
(l >> OP_SH_CODE20) & OP_MASK_CODE20); |
| 1115 |
|
|
break; |
| 1116 |
|
|
|
| 1117 |
|
|
case 'J': |
| 1118 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", |
| 1119 |
|
|
(l >> OP_SH_CODE19) & OP_MASK_CODE19); |
| 1120 |
|
|
break; |
| 1121 |
|
|
|
| 1122 |
|
|
case 'S': |
| 1123 |
|
|
case 'V': |
| 1124 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 1125 |
|
|
mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]); |
| 1126 |
|
|
break; |
| 1127 |
|
|
|
| 1128 |
|
|
case 'T': |
| 1129 |
|
|
case 'W': |
| 1130 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 1131 |
|
|
mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]); |
| 1132 |
|
|
break; |
| 1133 |
|
|
|
| 1134 |
|
|
case 'D': |
| 1135 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 1136 |
|
|
mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]); |
| 1137 |
|
|
break; |
| 1138 |
|
|
|
| 1139 |
|
|
case 'R': |
| 1140 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 1141 |
|
|
mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]); |
| 1142 |
|
|
break; |
| 1143 |
|
|
|
| 1144 |
|
|
case 'E': |
| 1145 |
|
|
/* Coprocessor register for lwcN instructions, et al. |
| 1146 |
|
|
|
| 1147 |
|
|
Note that there is no load/store cp0 instructions, and |
| 1148 |
|
|
that FPU (cp1) instructions disassemble this field using |
| 1149 |
|
|
'T' format. Therefore, until we gain understanding of |
| 1150 |
|
|
cp2 register names, we can simply print the register |
| 1151 |
|
|
numbers. */ |
| 1152 |
|
|
(*info->fprintf_func) (info->stream, "$%ld", |
| 1153 |
|
|
(l >> OP_SH_RT) & OP_MASK_RT); |
| 1154 |
|
|
break; |
| 1155 |
|
|
|
| 1156 |
|
|
case 'G': |
| 1157 |
|
|
/* Coprocessor register for mtcN instructions, et al. Note |
| 1158 |
|
|
that FPU (cp1) instructions disassemble this field using |
| 1159 |
|
|
'S' format. Therefore, we only need to worry about cp0, |
| 1160 |
|
|
cp2, and cp3. */ |
| 1161 |
|
|
op = (l >> OP_SH_OP) & OP_MASK_OP; |
| 1162 |
|
|
if (op == OP_OP_COP0) |
| 1163 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 1164 |
|
|
mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]); |
| 1165 |
|
|
else |
| 1166 |
|
|
(*info->fprintf_func) (info->stream, "$%ld", |
| 1167 |
|
|
(l >> OP_SH_RD) & OP_MASK_RD); |
| 1168 |
|
|
break; |
| 1169 |
|
|
|
| 1170 |
|
|
case 'K': |
| 1171 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 1172 |
|
|
mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]); |
| 1173 |
|
|
break; |
| 1174 |
|
|
|
| 1175 |
|
|
case 'N': |
| 1176 |
|
|
(*info->fprintf_func) (info->stream, |
| 1177 |
|
|
((opp->pinfo & (FP_D | FP_S)) != 0 |
| 1178 |
|
|
? "$fcc%ld" : "$cc%ld"), |
| 1179 |
|
|
(l >> OP_SH_BCC) & OP_MASK_BCC); |
| 1180 |
|
|
break; |
| 1181 |
|
|
|
| 1182 |
|
|
case 'M': |
| 1183 |
|
|
(*info->fprintf_func) (info->stream, "$fcc%ld", |
| 1184 |
|
|
(l >> OP_SH_CCC) & OP_MASK_CCC); |
| 1185 |
|
|
break; |
| 1186 |
|
|
|
| 1187 |
|
|
case 'P': |
| 1188 |
|
|
(*info->fprintf_func) (info->stream, "%ld", |
| 1189 |
|
|
(l >> OP_SH_PERFREG) & OP_MASK_PERFREG); |
| 1190 |
|
|
break; |
| 1191 |
|
|
|
| 1192 |
|
|
case 'e': |
| 1193 |
|
|
(*info->fprintf_func) (info->stream, "%ld", |
| 1194 |
|
|
(l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); |
| 1195 |
|
|
break; |
| 1196 |
|
|
|
| 1197 |
|
|
case '%': |
| 1198 |
|
|
(*info->fprintf_func) (info->stream, "%ld", |
| 1199 |
|
|
(l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); |
| 1200 |
|
|
break; |
| 1201 |
|
|
|
| 1202 |
|
|
case 'H': |
| 1203 |
|
|
(*info->fprintf_func) (info->stream, "%ld", |
| 1204 |
|
|
(l >> OP_SH_SEL) & OP_MASK_SEL); |
| 1205 |
|
|
break; |
| 1206 |
|
|
|
| 1207 |
|
|
case 'O': |
| 1208 |
|
|
(*info->fprintf_func) (info->stream, "%ld", |
| 1209 |
|
|
(l >> OP_SH_ALN) & OP_MASK_ALN); |
| 1210 |
|
|
break; |
| 1211 |
|
|
|
| 1212 |
|
|
case 'Q': |
| 1213 |
|
|
{ |
| 1214 |
|
|
unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; |
| 1215 |
|
|
|
| 1216 |
|
|
if ((vsel & 0x10) == 0) |
| 1217 |
|
|
{ |
| 1218 |
|
|
int fmt; |
| 1219 |
|
|
|
| 1220 |
|
|
vsel &= 0x0f; |
| 1221 |
|
|
for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) |
| 1222 |
|
|
if ((vsel & 1) == 0) |
| 1223 |
|
|
break; |
| 1224 |
|
|
(*info->fprintf_func) (info->stream, "$v%ld[%d]", |
| 1225 |
|
|
(l >> OP_SH_FT) & OP_MASK_FT, |
| 1226 |
|
|
vsel >> 1); |
| 1227 |
|
|
} |
| 1228 |
|
|
else if ((vsel & 0x08) == 0) |
| 1229 |
|
|
{ |
| 1230 |
|
|
(*info->fprintf_func) (info->stream, "$v%ld", |
| 1231 |
|
|
(l >> OP_SH_FT) & OP_MASK_FT); |
| 1232 |
|
|
} |
| 1233 |
|
|
else |
| 1234 |
|
|
{ |
| 1235 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", |
| 1236 |
|
|
(l >> OP_SH_FT) & OP_MASK_FT); |
| 1237 |
|
|
} |
| 1238 |
|
|
} |
| 1239 |
|
|
break; |
| 1240 |
|
|
|
| 1241 |
|
|
case 'X': |
| 1242 |
|
|
(*info->fprintf_func) (info->stream, "$v%ld", |
| 1243 |
|
|
(l >> OP_SH_FD) & OP_MASK_FD); |
| 1244 |
|
|
break; |
| 1245 |
|
|
|
| 1246 |
|
|
case 'Y': |
| 1247 |
|
|
(*info->fprintf_func) (info->stream, "$v%ld", |
| 1248 |
|
|
(l >> OP_SH_FS) & OP_MASK_FS); |
| 1249 |
|
|
break; |
| 1250 |
|
|
|
| 1251 |
|
|
case 'Z': |
| 1252 |
|
|
(*info->fprintf_func) (info->stream, "$v%ld", |
| 1253 |
|
|
(l >> OP_SH_FT) & OP_MASK_FT); |
| 1254 |
|
|
break; |
| 1255 |
|
|
|
| 1256 |
|
|
default: |
| 1257 |
|
|
/* xgettext:c-format */ |
| 1258 |
|
|
(*info->fprintf_func) (info->stream, |
| 1259 |
|
|
_("# internal error, undefined modifier(%c)"), |
| 1260 |
|
|
*d); |
| 1261 |
|
|
return; |
| 1262 |
|
|
} |
| 1263 |
|
|
} |
| 1264 |
|
|
} |
| 1265 |
|
|
|
| 1266 |
|
|
/* Print the mips instruction at address MEMADDR in debugged memory, |
| 1267 |
|
|
on using INFO. Returns length of the instruction, in bytes, which is |
| 1268 |
|
|
always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if |
| 1269 |
|
|
this is little-endian code. */ |
| 1270 |
|
|
|
| 1271 |
|
|
static int |
| 1272 |
|
|
print_insn_mips (bfd_vma memaddr, |
| 1273 |
|
|
unsigned long int word, |
| 1274 |
|
|
struct disassemble_info *info) |
| 1275 |
|
|
{ |
| 1276 |
|
|
const struct mips_opcode *op; |
| 1277 |
|
|
static bfd_boolean init = 0; |
| 1278 |
|
|
static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; |
| 1279 |
|
|
|
| 1280 |
|
|
/* Build a hash table to shorten the search time. */ |
| 1281 |
|
|
if (! init) |
| 1282 |
|
|
{ |
| 1283 |
|
|
unsigned int i; |
| 1284 |
|
|
|
| 1285 |
|
|
for (i = 0; i <= OP_MASK_OP; i++) |
| 1286 |
|
|
{ |
| 1287 |
|
|
for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) |
| 1288 |
|
|
{ |
| 1289 |
|
|
if (op->pinfo == INSN_MACRO |
| 1290 |
|
|
|| (no_aliases && (op->pinfo2 & INSN2_ALIAS))) |
| 1291 |
|
|
continue; |
| 1292 |
|
|
if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) |
| 1293 |
|
|
{ |
| 1294 |
|
|
mips_hash[i] = op; |
| 1295 |
|
|
break; |
| 1296 |
|
|
} |
| 1297 |
|
|
} |
| 1298 |
|
|
} |
| 1299 |
|
|
|
| 1300 |
|
|
init = 1; |
| 1301 |
|
|
} |
| 1302 |
|
|
|
| 1303 |
|
|
info->bytes_per_chunk = INSNLEN; |
| 1304 |
|
|
info->display_endian = info->endian; |
| 1305 |
|
|
info->insn_info_valid = 1; |
| 1306 |
|
|
info->branch_delay_insns = 0; |
| 1307 |
|
|
info->data_size = 0; |
| 1308 |
|
|
info->insn_type = dis_nonbranch; |
| 1309 |
|
|
info->target = 0; |
| 1310 |
|
|
info->target2 = 0; |
| 1311 |
|
|
|
| 1312 |
|
|
op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; |
| 1313 |
|
|
if (op != NULL) |
| 1314 |
|
|
{ |
| 1315 |
|
|
for (; op < &mips_opcodes[NUMOPCODES]; op++) |
| 1316 |
|
|
{ |
| 1317 |
|
|
if (op->pinfo != INSN_MACRO |
| 1318 |
|
|
&& !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) |
| 1319 |
|
|
&& (word & op->mask) == op->match) |
| 1320 |
|
|
{ |
| 1321 |
|
|
const char *d; |
| 1322 |
|
|
|
| 1323 |
|
|
/* We always allow to disassemble the jalx instruction. */ |
| 1324 |
|
|
if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor) |
| 1325 |
|
|
&& strcmp (op->name, "jalx")) |
| 1326 |
|
|
continue; |
| 1327 |
|
|
|
| 1328 |
|
|
/* Figure out instruction type and branch delay information. */ |
| 1329 |
|
|
if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) |
| 1330 |
|
|
{ |
| 1331 |
|
|
if ((info->insn_type & INSN_WRITE_GPR_31) != 0) |
| 1332 |
|
|
info->insn_type = dis_jsr; |
| 1333 |
|
|
else |
| 1334 |
|
|
info->insn_type = dis_branch; |
| 1335 |
|
|
info->branch_delay_insns = 1; |
| 1336 |
|
|
} |
| 1337 |
|
|
else if ((op->pinfo & (INSN_COND_BRANCH_DELAY |
| 1338 |
|
|
| INSN_COND_BRANCH_LIKELY)) != 0) |
| 1339 |
|
|
{ |
| 1340 |
|
|
if ((info->insn_type & INSN_WRITE_GPR_31) != 0) |
| 1341 |
|
|
info->insn_type = dis_condjsr; |
| 1342 |
|
|
else |
| 1343 |
|
|
info->insn_type = dis_condbranch; |
| 1344 |
|
|
info->branch_delay_insns = 1; |
| 1345 |
|
|
} |
| 1346 |
|
|
else if ((op->pinfo & (INSN_STORE_MEMORY |
| 1347 |
|
|
| INSN_LOAD_MEMORY_DELAY)) != 0) |
| 1348 |
|
|
info->insn_type = dis_dref; |
| 1349 |
|
|
|
| 1350 |
|
|
(*info->fprintf_func) (info->stream, "%s", op->name); |
| 1351 |
|
|
|
| 1352 |
|
|
d = op->args; |
| 1353 |
|
|
if (d != NULL && *d != '\0') |
| 1354 |
|
|
{ |
| 1355 |
|
|
(*info->fprintf_func) (info->stream, "\t"); |
| 1356 |
|
|
print_insn_args (d, word, memaddr, info, op); |
| 1357 |
|
|
} |
| 1358 |
|
|
|
| 1359 |
|
|
return INSNLEN; |
| 1360 |
|
|
} |
| 1361 |
|
|
} |
| 1362 |
|
|
} |
| 1363 |
|
|
|
| 1364 |
|
|
/* Handle undefined instructions. */ |
| 1365 |
|
|
info->insn_type = dis_noninsn; |
| 1366 |
|
|
(*info->fprintf_func) (info->stream, "0x%lx", word); |
| 1367 |
|
|
return INSNLEN; |
| 1368 |
|
|
} |
| 1369 |
|
|
|
| 1370 |
|
|
/* Disassemble an operand for a mips16 instruction. */ |
| 1371 |
|
|
|
| 1372 |
|
|
static void |
| 1373 |
|
|
print_mips16_insn_arg (char type, |
| 1374 |
|
|
const struct mips_opcode *op, |
| 1375 |
|
|
int l, |
| 1376 |
|
|
bfd_boolean use_extend, |
| 1377 |
|
|
int extend, |
| 1378 |
|
|
bfd_vma memaddr, |
| 1379 |
|
|
struct disassemble_info *info) |
| 1380 |
|
|
{ |
| 1381 |
|
|
switch (type) |
| 1382 |
|
|
{ |
| 1383 |
|
|
case ',': |
| 1384 |
|
|
case '(': |
| 1385 |
|
|
case ')': |
| 1386 |
|
|
(*info->fprintf_func) (info->stream, "%c", type); |
| 1387 |
|
|
break; |
| 1388 |
|
|
|
| 1389 |
|
|
case 'y': |
| 1390 |
|
|
case 'w': |
| 1391 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 1392 |
|
|
mips16_reg_names(((l >> MIPS16OP_SH_RY) |
| 1393 |
|
|
& MIPS16OP_MASK_RY))); |
| 1394 |
|
|
break; |
| 1395 |
|
|
|
| 1396 |
|
|
case 'x': |
| 1397 |
|
|
case 'v': |
| 1398 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 1399 |
|
|
mips16_reg_names(((l >> MIPS16OP_SH_RX) |
| 1400 |
|
|
& MIPS16OP_MASK_RX))); |
| 1401 |
|
|
break; |
| 1402 |
|
|
|
| 1403 |
|
|
case 'z': |
| 1404 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 1405 |
|
|
mips16_reg_names(((l >> MIPS16OP_SH_RZ) |
| 1406 |
|
|
& MIPS16OP_MASK_RZ))); |
| 1407 |
|
|
break; |
| 1408 |
|
|
|
| 1409 |
|
|
case 'Z': |
| 1410 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 1411 |
|
|
mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z) |
| 1412 |
|
|
& MIPS16OP_MASK_MOVE32Z))); |
| 1413 |
|
|
break; |
| 1414 |
|
|
|
| 1415 |
|
|
case '0': |
| 1416 |
|
|
(*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); |
| 1417 |
|
|
break; |
| 1418 |
|
|
|
| 1419 |
|
|
case 'S': |
| 1420 |
|
|
(*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]); |
| 1421 |
|
|
break; |
| 1422 |
|
|
|
| 1423 |
|
|
case 'P': |
| 1424 |
|
|
(*info->fprintf_func) (info->stream, "$pc"); |
| 1425 |
|
|
break; |
| 1426 |
|
|
|
| 1427 |
|
|
case 'R': |
| 1428 |
|
|
(*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]); |
| 1429 |
|
|
break; |
| 1430 |
|
|
|
| 1431 |
|
|
case 'X': |
| 1432 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 1433 |
|
|
mips_gpr_names[((l >> MIPS16OP_SH_REGR32) |
| 1434 |
|
|
& MIPS16OP_MASK_REGR32)]); |
| 1435 |
|
|
break; |
| 1436 |
|
|
|
| 1437 |
|
|
case 'Y': |
| 1438 |
|
|
(*info->fprintf_func) (info->stream, "%s", |
| 1439 |
|
|
mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]); |
| 1440 |
|
|
break; |
| 1441 |
|
|
|
| 1442 |
|
|
case '<': |
| 1443 |
|
|
case '>': |
| 1444 |
|
|
case '[': |
| 1445 |
|
|
case ']': |
| 1446 |
|
|
case '4': |
| 1447 |
|
|
case '5': |
| 1448 |
|
|
case 'H': |
| 1449 |
|
|
case 'W': |
| 1450 |
|
|
case 'D': |
| 1451 |
|
|
case 'j': |
| 1452 |
|
|
case '6': |
| 1453 |
|
|
case '8': |
| 1454 |
|
|
case 'V': |
| 1455 |
|
|
case 'C': |
| 1456 |
|
|
case 'U': |
| 1457 |
|
|
case 'k': |
| 1458 |
|
|
case 'K': |
| 1459 |
|
|
case 'p': |
| 1460 |
|
|
case 'q': |
| 1461 |
|
|
case 'A': |
| 1462 |
|
|
case 'B': |
| 1463 |
|
|
case 'E': |
| 1464 |
|
|
{ |
| 1465 |
|
|
int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; |
| 1466 |
|
|
|
| 1467 |
|
|
shift = 0; |
| 1468 |
|
|
signedp = 0; |
| 1469 |
|
|
extbits = 16; |
| 1470 |
|
|
pcrel = 0; |
| 1471 |
|
|
extu = 0; |
| 1472 |
|
|
branch = 0; |
| 1473 |
|
|
switch (type) |
| 1474 |
|
|
{ |
| 1475 |
|
|
case '<': |
| 1476 |
|
|
nbits = 3; |
| 1477 |
|
|
immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; |
| 1478 |
|
|
extbits = 5; |
| 1479 |
|
|
extu = 1; |
| 1480 |
|
|
break; |
| 1481 |
|
|
case '>': |
| 1482 |
|
|
nbits = 3; |
| 1483 |
|
|
immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
| 1484 |
|
|
extbits = 5; |
| 1485 |
|
|
extu = 1; |
| 1486 |
|
|
break; |
| 1487 |
|
|
case '[': |
| 1488 |
|
|
nbits = 3; |
| 1489 |
|
|
immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; |
| 1490 |
|
|
extbits = 6; |
| 1491 |
|
|
extu = 1; |
| 1492 |
|
|
break; |
| 1493 |
|
|
case ']': |
| 1494 |
|
|
nbits = 3; |
| 1495 |
|
|
immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
| 1496 |
|
|
extbits = 6; |
| 1497 |
|
|
extu = 1; |
| 1498 |
|
|
break; |
| 1499 |
|
|
case '4': |
| 1500 |
|
|
nbits = 4; |
| 1501 |
|
|
immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; |
| 1502 |
|
|
signedp = 1; |
| 1503 |
|
|
extbits = 15; |
| 1504 |
|
|
break; |
| 1505 |
|
|
case '5': |
| 1506 |
|
|
nbits = 5; |
| 1507 |
|
|
immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; |
| 1508 |
|
|
info->insn_type = dis_dref; |
| 1509 |
|
|
info->data_size = 1; |
| 1510 |
|
|
break; |
| 1511 |
|
|
case 'H': |
| 1512 |
|
|
nbits = 5; |
| 1513 |
|
|
shift = 1; |
| 1514 |
|
|
immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; |
| 1515 |
|
|
info->insn_type = dis_dref; |
| 1516 |
|
|
info->data_size = 2; |
| 1517 |
|
|
break; |
| 1518 |
|
|
case 'W': |
| 1519 |
|
|
nbits = 5; |
| 1520 |
|
|
shift = 2; |
| 1521 |
|
|
immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; |
| 1522 |
|
|
if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 |
| 1523 |
|
|
&& (op->pinfo & MIPS16_INSN_READ_SP) == 0) |
| 1524 |
|
|
{ |
| 1525 |
|
|
info->insn_type = dis_dref; |
| 1526 |
|
|
info->data_size = 4; |
| 1527 |
|
|
} |
| 1528 |
|
|
break; |
| 1529 |
|
|
case 'D': |
| 1530 |
|
|
nbits = 5; |
| 1531 |
|
|
shift = 3; |
| 1532 |
|
|
immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; |
| 1533 |
|
|
info->insn_type = dis_dref; |
| 1534 |
|
|
info->data_size = 8; |
| 1535 |
|
|
break; |
| 1536 |
|
|
case 'j': |
| 1537 |
|
|
nbits = 5; |
| 1538 |
|
|
immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; |
| 1539 |
|
|
signedp = 1; |
| 1540 |
|
|
break; |
| 1541 |
|
|
case '6': |
| 1542 |
|
|
nbits = 6; |
| 1543 |
|
|
immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; |
| 1544 |
|
|
break; |
| 1545 |
|
|
case '8': |
| 1546 |
|
|
nbits = 8; |
| 1547 |
|
|
immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; |
| 1548 |
|
|
break; |
| 1549 |
|
|
case 'V': |
| 1550 |
|
|
nbits = 8; |
| 1551 |
|
|
shift = 2; |
| 1552 |
|
|
immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; |
| 1553 |
|
|
/* FIXME: This might be lw, or it might be addiu to $sp or |
| 1554 |
|
|
$pc. We assume it's load. */ |
| 1555 |
|
|
info->insn_type = dis_dref; |
| 1556 |
|
|
info->data_size = 4; |
| 1557 |
|
|
break; |
| 1558 |
|
|
case 'C': |
| 1559 |
|
|
nbits = 8; |
| 1560 |
|
|
shift = 3; |
| 1561 |
|
|
immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; |
| 1562 |
|
|
info->insn_type = dis_dref; |
| 1563 |
|
|
info->data_size = 8; |
| 1564 |
|
|
break; |
| 1565 |
|
|
case 'U': |
| 1566 |
|
|
nbits = 8; |
| 1567 |
|
|
immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; |
| 1568 |
|
|
extu = 1; |
| 1569 |
|
|
break; |
| 1570 |
|
|
case 'k': |
| 1571 |
|
|
nbits = 8; |
| 1572 |
|
|
immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; |
| 1573 |
|
|
signedp = 1; |
| 1574 |
|
|
break; |
| 1575 |
|
|
case 'K': |
| 1576 |
|
|
nbits = 8; |
| 1577 |
|
|
shift = 3; |
| 1578 |
|
|
immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; |
| 1579 |
|
|
signedp = 1; |
| 1580 |
|
|
break; |
| 1581 |
|
|
case 'p': |
| 1582 |
|
|
nbits = 8; |
| 1583 |
|
|
immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; |
| 1584 |
|
|
signedp = 1; |
| 1585 |
|
|
pcrel = 1; |
| 1586 |
|
|
branch = 1; |
| 1587 |
|
|
info->insn_type = dis_condbranch; |
| 1588 |
|
|
break; |
| 1589 |
|
|
case 'q': |
| 1590 |
|
|
nbits = 11; |
| 1591 |
|
|
immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; |
| 1592 |
|
|
signedp = 1; |
| 1593 |
|
|
pcrel = 1; |
| 1594 |
|
|
branch = 1; |
| 1595 |
|
|
info->insn_type = dis_branch; |
| 1596 |
|
|
break; |
| 1597 |
|
|
case 'A': |
| 1598 |
|
|
nbits = 8; |
| 1599 |
|
|
shift = 2; |
| 1600 |
|
|
immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; |
| 1601 |
|
|
pcrel = 1; |
| 1602 |
|
|
/* FIXME: This can be lw or la. We assume it is lw. */ |
| 1603 |
|
|
info->insn_type = dis_dref; |
| 1604 |
|
|
info->data_size = 4; |
| 1605 |
|
|
break; |
| 1606 |
|
|
case 'B': |
| 1607 |
|
|
nbits = 5; |
| 1608 |
|
|
shift = 3; |
| 1609 |
|
|
immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; |
| 1610 |
|
|
pcrel = 1; |
| 1611 |
|
|
info->insn_type = dis_dref; |
| 1612 |
|
|
info->data_size = 8; |
| 1613 |
|
|
break; |
| 1614 |
|
|
case 'E': |
| 1615 |
|
|
nbits = 5; |
| 1616 |
|
|
shift = 2; |
| 1617 |
|
|
immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; |
| 1618 |
|
|
pcrel = 1; |
| 1619 |
|
|
break; |
| 1620 |
|
|
default: |
| 1621 |
|
|
abort (); |
| 1622 |
|
|
} |
| 1623 |
|
|
|
| 1624 |
|
|
if (! use_extend) |
| 1625 |
|
|
{ |
| 1626 |
|
|
if (signedp && immed >= (1 << (nbits - 1))) |
| 1627 |
|
|
immed -= 1 << nbits; |
| 1628 |
|
|
immed <<= shift; |
| 1629 |
|
|
if ((type == '<' || type == '>' || type == '[' || type == ']') |
| 1630 |
|
|
&& immed == 0) |
| 1631 |
|
|
immed = 8; |
| 1632 |
|
|
} |
| 1633 |
|
|
else |
| 1634 |
|
|
{ |
| 1635 |
|
|
if (extbits == 16) |
| 1636 |
|
|
immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); |
| 1637 |
|
|
else if (extbits == 15) |
| 1638 |
|
|
immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); |
| 1639 |
|
|
else |
| 1640 |
|
|
immed = ((extend >> 6) & 0x1f) | (extend & 0x20); |
| 1641 |
|
|
immed &= (1 << extbits) - 1; |
| 1642 |
|
|
if (! extu && immed >= (1 << (extbits - 1))) |
| 1643 |
|
|
immed -= 1 << extbits; |
| 1644 |
|
|
} |
| 1645 |
|
|
|
| 1646 |
|
|
if (! pcrel) |
| 1647 |
|
|
(*info->fprintf_func) (info->stream, "%d", immed); |
| 1648 |
|
|
else |
| 1649 |
|
|
{ |
| 1650 |
|
|
bfd_vma baseaddr; |
| 1651 |
|
|
|
| 1652 |
|
|
if (branch) |
| 1653 |
|
|
{ |
| 1654 |
|
|
immed *= 2; |
| 1655 |
|
|
baseaddr = memaddr + 2; |
| 1656 |
|
|
} |
| 1657 |
|
|
else if (use_extend) |
| 1658 |
|
|
baseaddr = memaddr - 2; |
| 1659 |
|
|
else |
| 1660 |
|
|
{ |
| 1661 |
|
|
int status; |
| 1662 |
|
|
bfd_byte buffer[2]; |
| 1663 |
|
|
|
| 1664 |
|
|
baseaddr = memaddr; |
| 1665 |
|
|
|
| 1666 |
|
|
/* If this instruction is in the delay slot of a jr |
| 1667 |
|
|
instruction, the base address is the address of the |
| 1668 |
|
|
jr instruction. If it is in the delay slot of jalr |
| 1669 |
|
|
instruction, the base address is the address of the |
| 1670 |
|
|
jalr instruction. This test is unreliable: we have |
| 1671 |
|
|
no way of knowing whether the previous word is |
| 1672 |
|
|
instruction or data. */ |
| 1673 |
|
|
status = (*info->read_memory_func) (memaddr - 4, buffer, 2, |
| 1674 |
|
|
info); |
| 1675 |
|
|
if (status == 0 |
| 1676 |
|
|
&& (((info->endian == BFD_ENDIAN_BIG |
| 1677 |
|
|
? bfd_getb16 (buffer) |
| 1678 |
|
|
: bfd_getl16 (buffer)) |
| 1679 |
|
|
& 0xf800) == 0x1800)) |
| 1680 |
|
|
baseaddr = memaddr - 4; |
| 1681 |
|
|
else |
| 1682 |
|
|
{ |
| 1683 |
|
|
status = (*info->read_memory_func) (memaddr - 2, buffer, |
| 1684 |
|
|
2, info); |
| 1685 |
|
|
if (status == 0 |
| 1686 |
|
|
&& (((info->endian == BFD_ENDIAN_BIG |
| 1687 |
|
|
? bfd_getb16 (buffer) |
| 1688 |
|
|
: bfd_getl16 (buffer)) |
| 1689 |
|
|
& 0xf81f) == 0xe800)) |
| 1690 |
|
|
baseaddr = memaddr - 2; |
| 1691 |
|
|
} |
| 1692 |
|
|
} |
| 1693 |
|
|
info->target = (baseaddr & ~((1 << shift) - 1)) + immed; |
| 1694 |
|
|
if (pcrel && branch |
| 1695 |
|
|
&& info->flavour == bfd_target_unknown_flavour) |
| 1696 |
|
|
/* For gdb disassembler, maintain odd address. */ |
| 1697 |
|
|
info->target |= 1; |
| 1698 |
|
|
(*info->print_address_func) (info->target, info); |
| 1699 |
|
|
} |
| 1700 |
|
|
} |
| 1701 |
|
|
break; |
| 1702 |
|
|
|
| 1703 |
|
|
case 'a': |
| 1704 |
|
|
{ |
| 1705 |
|
|
int jalx = l & 0x400; |
| 1706 |
|
|
|
| 1707 |
|
|
if (! use_extend) |
| 1708 |
|
|
extend = 0; |
| 1709 |
|
|
l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); |
| 1710 |
|
|
if (!jalx && info->flavour == bfd_target_unknown_flavour) |
| 1711 |
|
|
/* For gdb disassembler, maintain odd address. */ |
| 1712 |
|
|
l |= 1; |
| 1713 |
|
|
} |
| 1714 |
|
|
info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; |
| 1715 |
|
|
(*info->print_address_func) (info->target, info); |
| 1716 |
|
|
info->insn_type = dis_jsr; |
| 1717 |
|
|
info->branch_delay_insns = 1; |
| 1718 |
|
|
break; |
| 1719 |
|
|
|
| 1720 |
|
|
case 'l': |
| 1721 |
|
|
case 'L': |
| 1722 |
|
|
{ |
| 1723 |
|
|
int need_comma, amask, smask; |
| 1724 |
|
|
|
| 1725 |
|
|
need_comma = 0; |
| 1726 |
|
|
|
| 1727 |
|
|
l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; |
| 1728 |
|
|
|
| 1729 |
|
|
amask = (l >> 3) & 7; |
| 1730 |
|
|
|
| 1731 |
|
|
if (amask > 0 && amask < 5) |
| 1732 |
|
|
{ |
| 1733 |
|
|
(*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); |
| 1734 |
|
|
if (amask > 1) |
| 1735 |
|
|
(*info->fprintf_func) (info->stream, "-%s", |
| 1736 |
|
|
mips_gpr_names[amask + 3]); |
| 1737 |
|
|
need_comma = 1; |
| 1738 |
|
|
} |
| 1739 |
|
|
|
| 1740 |
|
|
smask = (l >> 1) & 3; |
| 1741 |
|
|
if (smask == 3) |
| 1742 |
|
|
{ |
| 1743 |
|
|
(*info->fprintf_func) (info->stream, "%s??", |
| 1744 |
|
|
need_comma ? "," : ""); |
| 1745 |
|
|
need_comma = 1; |
| 1746 |
|
|
} |
| 1747 |
|
|
else if (smask > 0) |
| 1748 |
|
|
{ |
| 1749 |
|
|
(*info->fprintf_func) (info->stream, "%s%s", |
| 1750 |
|
|
need_comma ? "," : "", |
| 1751 |
|
|
mips_gpr_names[16]); |
| 1752 |
|
|
if (smask > 1) |
| 1753 |
|
|
(*info->fprintf_func) (info->stream, "-%s", |
| 1754 |
|
|
mips_gpr_names[smask + 15]); |
| 1755 |
|
|
need_comma = 1; |
| 1756 |
|
|
} |
| 1757 |
|
|
|
| 1758 |
|
|
if (l & 1) |
| 1759 |
|
|
{ |
| 1760 |
|
|
(*info->fprintf_func) (info->stream, "%s%s", |
| 1761 |
|
|
need_comma ? "," : "", |
| 1762 |
|
|
mips_gpr_names[31]); |
| 1763 |
|
|
need_comma = 1; |
| 1764 |
|
|
} |
| 1765 |
|
|
|
| 1766 |
|
|
if (amask == 5 || amask == 6) |
| 1767 |
|
|
{ |
| 1768 |
|
|
(*info->fprintf_func) (info->stream, "%s$f0", |
| 1769 |
|
|
need_comma ? "," : ""); |
| 1770 |
|
|
if (amask == 6) |
| 1771 |
|
|
(*info->fprintf_func) (info->stream, "-$f1"); |
| 1772 |
|
|
} |
| 1773 |
|
|
} |
| 1774 |
|
|
break; |
| 1775 |
|
|
|
| 1776 |
|
|
case 'm': |
| 1777 |
|
|
case 'M': |
| 1778 |
|
|
/* MIPS16e save/restore. */ |
| 1779 |
|
|
{ |
| 1780 |
|
|
int need_comma = 0; |
| 1781 |
|
|
int amask, args, statics; |
| 1782 |
|
|
int nsreg, smask; |
| 1783 |
|
|
int framesz; |
| 1784 |
|
|
int i, j; |
| 1785 |
|
|
|
| 1786 |
|
|
l = l & 0x7f; |
| 1787 |
|
|
if (use_extend) |
| 1788 |
|
|
l |= extend << 16; |
| 1789 |
|
|
|
| 1790 |
|
|
amask = (l >> 16) & 0xf; |
| 1791 |
|
|
if (amask == MIPS16_ALL_ARGS) |
| 1792 |
|
|
{ |
| 1793 |
|
|
args = 4; |
| 1794 |
|
|
statics = 0; |
| 1795 |
|
|
} |
| 1796 |
|
|
else if (amask == MIPS16_ALL_STATICS) |
| 1797 |
|
|
{ |
| 1798 |
|
|
args = 0; |
| 1799 |
|
|
statics = 4; |
| 1800 |
|
|
} |
| 1801 |
|
|
else |
| 1802 |
|
|
{ |
| 1803 |
|
|
args = amask >> 2; |
| 1804 |
|
|
statics = amask & 3; |
| 1805 |
|
|
} |
| 1806 |
|
|
|
| 1807 |
|
|
if (args > 0) { |
| 1808 |
|
|
(*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); |
| 1809 |
|
|
if (args > 1) |
| 1810 |
|
|
(*info->fprintf_func) (info->stream, "-%s", |
| 1811 |
|
|
mips_gpr_names[4 + args - 1]); |
| 1812 |
|
|
need_comma = 1; |
| 1813 |
|
|
} |
| 1814 |
|
|
|
| 1815 |
|
|
framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8; |
| 1816 |
|
|
if (framesz == 0 && !use_extend) |
| 1817 |
|
|
framesz = 128; |
| 1818 |
|
|
|
| 1819 |
|
|
(*info->fprintf_func) (info->stream, "%s%d", |
| 1820 |
|
|
need_comma ? "," : "", |
| 1821 |
|
|
framesz); |
| 1822 |
|
|
|
| 1823 |
|
|
if (l & 0x40) /* $ra */ |
| 1824 |
|
|
(*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]); |
| 1825 |
|
|
|
| 1826 |
|
|
nsreg = (l >> 24) & 0x7; |
| 1827 |
|
|
smask = 0; |
| 1828 |
|
|
if (l & 0x20) /* $s0 */ |
| 1829 |
|
|
smask |= 1 << 0; |
| 1830 |
|
|
if (l & 0x10) /* $s1 */ |
| 1831 |
|
|
smask |= 1 << 1; |
| 1832 |
|
|
if (nsreg > 0) /* $s2-$s8 */ |
| 1833 |
|
|
smask |= ((1 << nsreg) - 1) << 2; |
| 1834 |
|
|
|
| 1835 |
|
|
/* Find first set static reg bit. */ |
| 1836 |
|
|
for (i = 0; i < 9; i++) |
| 1837 |
|
|
{ |
| 1838 |
|
|
if (smask & (1 << i)) |
| 1839 |
|
|
{ |
| 1840 |
|
|
(*info->fprintf_func) (info->stream, ",%s", |
| 1841 |
|
|
mips_gpr_names[i == 8 ? 30 : (16 + i)]); |
| 1842 |
|
|
/* Skip over string of set bits. */ |
| 1843 |
|
|
for (j = i; smask & (2 << j); j++) |
| 1844 |
|
|
continue; |
| 1845 |
|
|
if (j > i) |
| 1846 |
|
|
(*info->fprintf_func) (info->stream, "-%s", |
| 1847 |
|
|
mips_gpr_names[j == 8 ? 30 : (16 + j)]); |
| 1848 |
|
|
i = j + 1; |
| 1849 |
|
|
} |
| 1850 |
|
|
} |
| 1851 |
|
|
|
| 1852 |
|
|
/* Statics $ax - $a3. */ |
| 1853 |
|
|
if (statics == 1) |
| 1854 |
|
|
(*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]); |
| 1855 |
|
|
else if (statics > 0) |
| 1856 |
|
|
(*info->fprintf_func) (info->stream, ",%s-%s", |
| 1857 |
|
|
mips_gpr_names[7 - statics + 1], |
| 1858 |
|
|
mips_gpr_names[7]); |
| 1859 |
|
|
} |
| 1860 |
|
|
break; |
| 1861 |
|
|
|
| 1862 |
|
|
default: |
| 1863 |
|
|
/* xgettext:c-format */ |
| 1864 |
|
|
(*info->fprintf_func) |
| 1865 |
|
|
(info->stream, |
| 1866 |
|
|
_("# internal disassembler error, unrecognised modifier (%c)"), |
| 1867 |
|
|
type); |
| 1868 |
|
|
abort (); |
| 1869 |
|
|
} |
| 1870 |
|
|
} |
| 1871 |
|
|
|
| 1872 |
|
|
/* Disassemble mips16 instructions. */ |
| 1873 |
|
|
|
| 1874 |
|
|
static int |
| 1875 |
|
|
print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) |
| 1876 |
|
|
{ |
| 1877 |
|
|
int status; |
| 1878 |
|
|
bfd_byte buffer[2]; |
| 1879 |
|
|
int length; |
| 1880 |
|
|
int insn; |
| 1881 |
|
|
bfd_boolean use_extend; |
| 1882 |
|
|
int extend = 0; |
| 1883 |
|
|
const struct mips_opcode *op, *opend; |
| 1884 |
|
|
|
| 1885 |
|
|
info->bytes_per_chunk = 2; |
| 1886 |
|
|
info->display_endian = info->endian; |
| 1887 |
|
|
info->insn_info_valid = 1; |
| 1888 |
|
|
info->branch_delay_insns = 0; |
| 1889 |
|
|
info->data_size = 0; |
| 1890 |
|
|
info->insn_type = dis_nonbranch; |
| 1891 |
|
|
info->target = 0; |
| 1892 |
|
|
info->target2 = 0; |
| 1893 |
|
|
|
| 1894 |
|
|
status = (*info->read_memory_func) (memaddr, buffer, 2, info); |
| 1895 |
|
|
if (status != 0) |
| 1896 |
|
|
{ |
| 1897 |
|
|
(*info->memory_error_func) (status, memaddr, info); |
| 1898 |
|
|
return -1; |
| 1899 |
|
|
} |
| 1900 |
|
|
|
| 1901 |
|
|
length = 2; |
| 1902 |
|
|
|
| 1903 |
|
|
if (info->endian == BFD_ENDIAN_BIG) |
| 1904 |
|
|
insn = bfd_getb16 (buffer); |
| 1905 |
|
|
else |
| 1906 |
|
|
insn = bfd_getl16 (buffer); |
| 1907 |
|
|
|
| 1908 |
|
|
/* Handle the extend opcode specially. */ |
| 1909 |
|
|
use_extend = FALSE; |
| 1910 |
|
|
if ((insn & 0xf800) == 0xf000) |
| 1911 |
|
|
{ |
| 1912 |
|
|
use_extend = TRUE; |
| 1913 |
|
|
extend = insn & 0x7ff; |
| 1914 |
|
|
|
| 1915 |
|
|
memaddr += 2; |
| 1916 |
|
|
|
| 1917 |
|
|
status = (*info->read_memory_func) (memaddr, buffer, 2, info); |
| 1918 |
|
|
if (status != 0) |
| 1919 |
|
|
{ |
| 1920 |
|
|
(*info->fprintf_func) (info->stream, "extend 0x%x", |
| 1921 |
|
|
(unsigned int) extend); |
| 1922 |
|
|
(*info->memory_error_func) (status, memaddr, info); |
| 1923 |
|
|
return -1; |
| 1924 |
|
|
} |
| 1925 |
|
|
|
| 1926 |
|
|
if (info->endian == BFD_ENDIAN_BIG) |
| 1927 |
|
|
insn = bfd_getb16 (buffer); |
| 1928 |
|
|
else |
| 1929 |
|
|
insn = bfd_getl16 (buffer); |
| 1930 |
|
|
|
| 1931 |
|
|
/* Check for an extend opcode followed by an extend opcode. */ |
| 1932 |
|
|
if ((insn & 0xf800) == 0xf000) |
| 1933 |
|
|
{ |
| 1934 |
|
|
(*info->fprintf_func) (info->stream, "extend 0x%x", |
| 1935 |
|
|
(unsigned int) extend); |
| 1936 |
|
|
info->insn_type = dis_noninsn; |
| 1937 |
|
|
return length; |
| 1938 |
|
|
} |
| 1939 |
|
|
|
| 1940 |
|
|
length += 2; |
| 1941 |
|
|
} |
| 1942 |
|
|
|
| 1943 |
|
|
/* FIXME: Should probably use a hash table on the major opcode here. */ |
| 1944 |
|
|
|
| 1945 |
|
|
opend = mips16_opcodes + bfd_mips16_num_opcodes; |
| 1946 |
|
|
for (op = mips16_opcodes; op < opend; op++) |
| 1947 |
|
|
{ |
| 1948 |
|
|
if (op->pinfo != INSN_MACRO |
| 1949 |
|
|
&& !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) |
| 1950 |
|
|
&& (insn & op->mask) == op->match) |
| 1951 |
|
|
{ |
| 1952 |
|
|
const char *s; |
| 1953 |
|
|
|
| 1954 |
|
|
if (strchr (op->args, 'a') != NULL) |
| 1955 |
|
|
{ |
| 1956 |
|
|
if (use_extend) |
| 1957 |
|
|
{ |
| 1958 |
|
|
(*info->fprintf_func) (info->stream, "extend 0x%x", |
| 1959 |
|
|
(unsigned int) extend); |
| 1960 |
|
|
info->insn_type = dis_noninsn; |
| 1961 |
|
|
return length - 2; |
| 1962 |
|
|
} |
| 1963 |
|
|
|
| 1964 |
|
|
use_extend = FALSE; |
| 1965 |
|
|
|
| 1966 |
|
|
memaddr += 2; |
| 1967 |
|
|
|
| 1968 |
|
|
status = (*info->read_memory_func) (memaddr, buffer, 2, |
| 1969 |
|
|
info); |
| 1970 |
|
|
if (status == 0) |
| 1971 |
|
|
{ |
| 1972 |
|
|
use_extend = TRUE; |
| 1973 |
|
|
if (info->endian == BFD_ENDIAN_BIG) |
| 1974 |
|
|
extend = bfd_getb16 (buffer); |
| 1975 |
|
|
else |
| 1976 |
|
|
extend = bfd_getl16 (buffer); |
| 1977 |
|
|
length += 2; |
| 1978 |
|
|
} |
| 1979 |
|
|
} |
| 1980 |
|
|
|
| 1981 |
|
|
(*info->fprintf_func) (info->stream, "%s", op->name); |
| 1982 |
|
|
if (op->args[0] != '\0') |
| 1983 |
|
|
(*info->fprintf_func) (info->stream, "\t"); |
| 1984 |
|
|
|
| 1985 |
|
|
for (s = op->args; *s != '\0'; s++) |
| 1986 |
|
|
{ |
| 1987 |
|
|
if (*s == ',' |
| 1988 |
|
|
&& s[1] == 'w' |
| 1989 |
|
|
&& (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) |
| 1990 |
|
|
== ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) |
| 1991 |
|
|
{ |
| 1992 |
|
|
/* Skip the register and the comma. */ |
| 1993 |
|
|
++s; |
| 1994 |
|
|
continue; |
| 1995 |
|
|
} |
| 1996 |
|
|
if (*s == ',' |
| 1997 |
|
|
&& s[1] == 'v' |
| 1998 |
|
|
&& (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) |
| 1999 |
|
|
== ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) |
| 2000 |
|
|
{ |
| 2001 |
|
|
/* Skip the register and the comma. */ |
| 2002 |
|
|
++s; |
| 2003 |
|
|
continue; |
| 2004 |
|
|
} |
| 2005 |
|
|
print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, |
| 2006 |
|
|
info); |
| 2007 |
|
|
} |
| 2008 |
|
|
|
| 2009 |
|
|
if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) |
| 2010 |
|
|
{ |
| 2011 |
|
|
info->branch_delay_insns = 1; |
| 2012 |
|
|
if (info->insn_type != dis_jsr) |
| 2013 |
|
|
info->insn_type = dis_branch; |
| 2014 |
|
|
} |
| 2015 |
|
|
|
| 2016 |
|
|
return length; |
| 2017 |
|
|
} |
| 2018 |
|
|
} |
| 2019 |
|
|
|
| 2020 |
|
|
if (use_extend) |
| 2021 |
|
|
(*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); |
| 2022 |
|
|
(*info->fprintf_func) (info->stream, "0x%x", insn); |
| 2023 |
|
|
info->insn_type = dis_noninsn; |
| 2024 |
|
|
|
| 2025 |
|
|
return length; |
| 2026 |
|
|
} |
| 2027 |
|
|
|
| 2028 |
|
|
/* In an environment where we do not know the symbol type of the |
| 2029 |
|
|
instruction we are forced to assume that the low order bit of the |
| 2030 |
|
|
instructions' address may mark it as a mips16 instruction. If we |
| 2031 |
|
|
are single stepping, or the pc is within the disassembled function, |
| 2032 |
|
|
this works. Otherwise, we need a clue. Sometimes. */ |
| 2033 |
|
|
|
| 2034 |
|
|
static int |
| 2035 |
|
|
_print_insn_mips (bfd_vma memaddr, |
| 2036 |
|
|
struct disassemble_info *info, |
| 2037 |
|
|
enum bfd_endian endianness) |
| 2038 |
|
|
{ |
| 2039 |
|
|
bfd_byte buffer[INSNLEN]; |
| 2040 |
|
|
int status; |
| 2041 |
|
|
|
| 2042 |
|
|
set_default_mips_dis_options (info); |
| 2043 |
|
|
parse_mips_dis_options (info->disassembler_options); |
| 2044 |
|
|
|
| 2045 |
|
|
#if 1 |
| 2046 |
|
|
/* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ |
| 2047 |
|
|
/* Only a few tools will work this way. */ |
| 2048 |
|
|
if (memaddr & 0x01) |
| 2049 |
|
|
return print_insn_mips16 (memaddr, info); |
| 2050 |
|
|
#endif |
| 2051 |
|
|
|
| 2052 |
|
|
#if SYMTAB_AVAILABLE |
| 2053 |
|
|
if (info->mach == bfd_mach_mips16 |
| 2054 |
|
|
|| (info->flavour == bfd_target_elf_flavour |
| 2055 |
|
|
&& info->symbols != NULL |
| 2056 |
|
|
&& ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other |
| 2057 |
|
|
== STO_MIPS16))) |
| 2058 |
|
|
return print_insn_mips16 (memaddr, info); |
| 2059 |
|
|
#endif |
| 2060 |
|
|
|
| 2061 |
|
|
status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); |
| 2062 |
|
|
if (status == 0) |
| 2063 |
|
|
{ |
| 2064 |
|
|
unsigned long insn; |
| 2065 |
|
|
|
| 2066 |
|
|
if (endianness == BFD_ENDIAN_BIG) |
| 2067 |
|
|
insn = (unsigned long) bfd_getb32 (buffer); |
| 2068 |
|
|
else |
| 2069 |
|
|
insn = (unsigned long) bfd_getl32 (buffer); |
| 2070 |
|
|
|
| 2071 |
|
|
return print_insn_mips (memaddr, insn, info); |
| 2072 |
|
|
} |
| 2073 |
|
|
else |
| 2074 |
|
|
{ |
| 2075 |
|
|
(*info->memory_error_func) (status, memaddr, info); |
| 2076 |
|
|
return -1; |
| 2077 |
|
|
} |
| 2078 |
|
|
} |
| 2079 |
|
|
|
| 2080 |
|
|
int |
| 2081 |
|
|
print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info) |
| 2082 |
|
|
{ |
| 2083 |
|
|
return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); |
| 2084 |
|
|
} |
| 2085 |
|
|
|
| 2086 |
|
|
int |
| 2087 |
|
|
print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info) |
| 2088 |
|
|
{ |
| 2089 |
|
|
return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); |
| 2090 |
|
|
} |
| 2091 |
|
|
|
| 2092 |
|
|
void |
| 2093 |
|
|
print_mips_disassembler_options (FILE *stream) |
| 2094 |
|
|
{ |
| 2095 |
|
|
unsigned int i; |
| 2096 |
|
|
|
| 2097 |
|
|
fprintf (stream, _("\n\ |
| 2098 |
|
|
The following MIPS specific disassembler options are supported for use\n\ |
| 2099 |
|
|
with the -M switch (multiple options should be separated by commas):\n")); |
| 2100 |
|
|
|
| 2101 |
|
|
fprintf (stream, _("\n\ |
| 2102 |
|
|
gpr-names=ABI Print GPR names according to specified ABI.\n\ |
| 2103 |
|
|
Default: based on binary being disassembled.\n")); |
| 2104 |
|
|
|
| 2105 |
|
|
fprintf (stream, _("\n\ |
| 2106 |
|
|
fpr-names=ABI Print FPR names according to specified ABI.\n\ |
| 2107 |
|
|
Default: numeric.\n")); |
| 2108 |
|
|
|
| 2109 |
|
|
fprintf (stream, _("\n\ |
| 2110 |
|
|
cp0-names=ARCH Print CP0 register names according to\n\ |
| 2111 |
|
|
specified architecture.\n\ |
| 2112 |
|
|
Default: based on binary being disassembled.\n")); |
| 2113 |
|
|
|
| 2114 |
|
|
fprintf (stream, _("\n\ |
| 2115 |
|
|
hwr-names=ARCH Print HWR names according to specified \n\ |
| 2116 |
|
|
architecture.\n\ |
| 2117 |
|
|
Default: based on binary being disassembled.\n")); |
| 2118 |
|
|
|
| 2119 |
|
|
fprintf (stream, _("\n\ |
| 2120 |
|
|
reg-names=ABI Print GPR and FPR names according to\n\ |
| 2121 |
|
|
specified ABI.\n")); |
| 2122 |
|
|
|
| 2123 |
|
|
fprintf (stream, _("\n\ |
| 2124 |
|
|
reg-names=ARCH Print CP0 register and HWR names according to\n\ |
| 2125 |
|
|
specified architecture.\n")); |
| 2126 |
|
|
|
| 2127 |
|
|
fprintf (stream, _("\n\ |
| 2128 |
|
|
For the options above, the following values are supported for \"ABI\":\n\ |
| 2129 |
|
|
")); |
| 2130 |
|
|
for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) |
| 2131 |
|
|
fprintf (stream, " %s", mips_abi_choices[i].name); |
| 2132 |
|
|
fprintf (stream, _("\n")); |
| 2133 |
|
|
|
| 2134 |
|
|
fprintf (stream, _("\n\ |
| 2135 |
|
|
For the options above, The following values are supported for \"ARCH\":\n\ |
| 2136 |
|
|
")); |
| 2137 |
|
|
for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) |
| 2138 |
|
|
if (*mips_arch_choices[i].name != '\0') |
| 2139 |
|
|
fprintf (stream, " %s", mips_arch_choices[i].name); |
| 2140 |
|
|
fprintf (stream, _("\n")); |
| 2141 |
|
|
|
| 2142 |
|
|
fprintf (stream, _("\n")); |
| 2143 |
|
|
} |
