270 |
|
|
271 |
|
|
272 |
|
/* |
273 |
+ |
* Return target of branch instruction specified at ADDR, or 0 if |
274 |
+ |
* there is no such instruction |
275 |
+ |
*/ |
276 |
+ |
|
277 |
+ |
static uint32 powerpc_branch_target(uintptr addr) |
278 |
+ |
{ |
279 |
+ |
uint32 opcode = ntohl(*(uint32 *)addr); |
280 |
+ |
uint32 primop = opcode >> 26; |
281 |
+ |
uint32 target = 0; |
282 |
+ |
|
283 |
+ |
if (primop == 18) { // Branch |
284 |
+ |
target = opcode & 0x3fffffc; |
285 |
+ |
if (target & 0x2000000) |
286 |
+ |
target |= 0xfc000000; |
287 |
+ |
if ((opcode & 2) == 0) |
288 |
+ |
target += addr; |
289 |
+ |
} |
290 |
+ |
else if (primop == 16) { // Branch Conditional |
291 |
+ |
target = (int32)(int16)(opcode & 0xfffc); |
292 |
+ |
if ((opcode & 2) == 0) |
293 |
+ |
target += addr; |
294 |
+ |
} |
295 |
+ |
return target; |
296 |
+ |
} |
297 |
+ |
|
298 |
+ |
|
299 |
+ |
/* |
300 |
+ |
* Search ROM for instruction branching to target address, return 0 if none found |
301 |
+ |
*/ |
302 |
+ |
|
303 |
+ |
static uint32 find_rom_powerpc_branch(uint32 start, uint32 end, uint32 target) |
304 |
+ |
{ |
305 |
+ |
for (uint32 addr = start; addr < end; addr += 4) { |
306 |
+ |
if (powerpc_branch_target(ROM_BASE + addr) == ROM_BASE + target) |
307 |
+ |
return addr; |
308 |
+ |
} |
309 |
+ |
return 0; |
310 |
+ |
} |
311 |
+ |
|
312 |
+ |
|
313 |
+ |
/* |
314 |
|
* List of audio sifters installed in ROM and System file |
315 |
|
*/ |
316 |
|
|
738 |
|
static bool patch_nanokernel_boot(void) |
739 |
|
{ |
740 |
|
uint32 *lp; |
741 |
+ |
uint32 base, loc; |
742 |
|
|
743 |
|
// ROM boot structure patches |
744 |
|
lp = (uint32 *)(ROM_BASE + 0x30d000); |
751 |
|
lp[0xfd8 >> 2] = htonl(ROM_BASE + 0x2a); // 68k reset vector |
752 |
|
|
753 |
|
// Skip SR/BAT/SDR init |
754 |
+ |
loc = 0x310000; |
755 |
|
if (ROMType == ROMTYPE_GAZELLE || ROMType == ROMTYPE_GOSSAMER || ROMType == ROMTYPE_NEWWORLD) { |
756 |
< |
lp = (uint32 *)(ROM_BASE + 0x310000); |
756 |
> |
lp = (uint32 *)(ROM_BASE + loc); |
757 |
|
*lp++ = htonl(POWERPC_NOP); |
758 |
|
*lp = htonl(0x38000000); |
759 |
|
} |
760 |
< |
static const uint32 sr_init_loc[] = {0x3101b0, 0x3101b0, 0x3101b0, 0x3101ec, 0x3101fc, 0x310200}; |
761 |
< |
lp = (uint32 *)(ROM_BASE + 0x310008); |
762 |
< |
*lp = htonl(0x48000000 | (sr_init_loc[ROMType] - 8) & 0xffff); // b ROM_BASE+0x3101b0 |
763 |
< |
lp = (uint32 *)(ROM_BASE + sr_init_loc[ROMType]); |
760 |
> |
static const uint8 sr_init_dat[] = {0x35, 0x4a, 0xff, 0xfc, 0x7d, 0x86, 0x50, 0x2e}; |
761 |
> |
if ((base = find_rom_data(0x3101b0, 0x3105b0, sr_init_dat, sizeof(sr_init_dat))) == 0) return false; |
762 |
> |
D(bug("sr_init %08lx\n", base)); |
763 |
> |
lp = (uint32 *)(ROM_BASE + loc + 8); |
764 |
> |
*lp = htonl(0x48000000 | ((base - loc - 8) & 0x3fffffc)); // b ROM_BASE+0x3101b0 |
765 |
> |
lp = (uint32 *)(ROM_BASE + base); |
766 |
|
*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA); // lwz r1,(pointer to Kernel Data) |
767 |
|
*lp++ = htonl(0x3da0dead); // lis r13,0xdead (start of kernel memory) |
768 |
|
*lp++ = htonl(0x3dc00010); // lis r14,0x0010 (size of page table) |
769 |
|
*lp = htonl(0x3de00010); // lis r15,0x0010 (size of kernel memory) |
770 |
|
|
771 |
|
// Don't read PVR |
772 |
< |
static const uint32 pvr_loc[] = {0x3103b0, 0x3103b4, 0x3103b4, 0x310400, 0x310430, 0x310438}; |
773 |
< |
lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]); |
772 |
> |
static const uint8 pvr_read_dat[] = {0x7d, 0x9f, 0x42, 0xa6}; |
773 |
> |
if ((base = find_rom_data(0x3103b0, 0x3108b0, pvr_read_dat, sizeof(pvr_read_dat))) == 0) return false; |
774 |
> |
D(bug("pvr_read %08lx\n", base)); |
775 |
> |
lp = (uint32 *)(ROM_BASE + base); |
776 |
|
*lp = htonl(0x81800000 + XLM_PVR); // lwz r12,(theoretical PVR) |
777 |
|
|
778 |
|
// Set CPU specific data (even if ROM doesn't have support for that CPU) |
732 |
– |
lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]); |
779 |
|
if (ntohl(lp[6]) != 0x2c0c0001) |
780 |
|
return false; |
781 |
|
uint32 ofs = ntohl(lp[7]) & 0xffff; |
782 |
|
D(bug("ofs %08lx\n", ofs)); |
783 |
|
lp[8] = htonl((ntohl(lp[8]) & 0xffff) | 0x48000000); // beq -> b |
784 |
< |
uint32 loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE; |
784 |
> |
loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE; |
785 |
|
D(bug("loc %08lx\n", loc)); |
786 |
|
lp = (uint32 *)(ROM_BASE + ofs + 0x310000); |
787 |
|
switch (PVR >> 16) { |
896 |
|
} |
897 |
|
|
898 |
|
// Don't set SPRG3, don't test MQ |
899 |
< |
lp = (uint32 *)(ROM_BASE + loc + 0x20); |
900 |
< |
*lp++ = htonl(POWERPC_NOP); |
901 |
< |
lp++; |
902 |
< |
*lp++ = htonl(POWERPC_NOP); |
903 |
< |
lp++; |
904 |
< |
*lp = htonl(POWERPC_NOP); |
899 |
> |
static const uint8 sprg3_mq_dat[] = {0x7d, 0x13, 0x43, 0xa6, 0x3d, 0x00, 0x00, 0x04, 0x7d, 0x00, 0x03, 0xa6, 0x39, 0x00, 0x00, 0x00, 0x7d, 0x00, 0x02, 0xa6}; |
900 |
> |
if ((base = find_rom_data(loc + 0x20, loc + 0x60, sprg3_mq_dat, sizeof(sprg3_mq_dat))) == 0) return false; |
901 |
> |
D(bug("sprg3/mq %08lx\n", base)); |
902 |
> |
lp = (uint32 *)(ROM_BASE + base); |
903 |
> |
lp[0] = htonl(POWERPC_NOP); |
904 |
> |
lp[2] = htonl(POWERPC_NOP); |
905 |
> |
lp[4] = htonl(POWERPC_NOP); |
906 |
|
|
907 |
|
// Don't read MSR |
908 |
< |
lp = (uint32 *)(ROM_BASE + loc + 0x40); |
908 |
> |
static const uint8 msr_dat[] = {0x7d, 0xc0, 0x00, 0xa6}; |
909 |
> |
if ((base = find_rom_data(loc + 0x40, loc + 0x80, msr_dat, sizeof(msr_dat))) == 0) return false; |
910 |
> |
D(bug("msr %08lx\n", base)); |
911 |
> |
lp = (uint32 *)(ROM_BASE + base); |
912 |
|
*lp = htonl(0x39c00000); // li r14,0 |
913 |
|
|
914 |
|
// Don't write to DEC |
918 |
|
D(bug("loc %08lx\n", loc)); |
919 |
|
|
920 |
|
// Don't set SPRG3 |
921 |
< |
lp = (uint32 *)(ROM_BASE + loc + 0x2c); |
921 |
> |
static const uint8 sprg3_dat[] = {0x39, 0x21, 0x03, 0x60, 0x7d, 0x33, 0x43, 0xa6, 0x39, 0x01, 0x04, 0x20}; |
922 |
> |
if ((base = find_rom_data(0x310000, 0x314000, sprg3_dat, sizeof(sprg3_dat))) == 0) return false; |
923 |
> |
D(bug("sprg3 %08lx\n", base + 4)); |
924 |
> |
lp = (uint32 *)(ROM_BASE + base + 4); |
925 |
|
*lp = htonl(POWERPC_NOP); |
926 |
|
|
927 |
|
// Don't read PVR |
928 |
< |
static const uint32 pvr_ofs[] = {0x138, 0x138, 0x138, 0x140, 0x148, 0x148}; |
929 |
< |
lp = (uint32 *)(ROM_BASE + loc + pvr_ofs[ROMType]); |
928 |
> |
static const uint8 pvr_read2_dat[] = {0x7e, 0xff, 0x42, 0xa6, 0x56, 0xf7, 0x84, 0x3e}; |
929 |
> |
if ((base = find_rom_data(0x310000, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) == 0) return false; |
930 |
> |
D(bug("pvr_read2 %08lx\n", base)); |
931 |
> |
lp = (uint32 *)(ROM_BASE + base); |
932 |
|
*lp = htonl(0x82e00000 + XLM_PVR); // lwz r23,(theoretical PVR) |
933 |
< |
lp = (uint32 *)(ROM_BASE + loc + 0x170); |
934 |
< |
if (ntohl(*lp) == 0x7eff42a6) // NewWorld or Gossamer ROM |
933 |
> |
if ((base = find_rom_data(base + 4, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) != 0) { |
934 |
> |
D(bug("pvr_read2 %08lx\n", base)); |
935 |
> |
lp = (uint32 *)(ROM_BASE + base); |
936 |
|
*lp = htonl(0x82e00000 + XLM_PVR); // lwz r23,(theoretical PVR) |
937 |
< |
lp = (uint32 *)(ROM_BASE + 0x313134); |
938 |
< |
if (ntohl(*lp) == 0x7e5f42a6) |
939 |
< |
*lp = htonl(0x82400000 + XLM_PVR); // lwz r18,(theoretical PVR) |
940 |
< |
lp = (uint32 *)(ROM_BASE + 0x3131f4); |
941 |
< |
if (ntohl(*lp) == 0x7e5f42a6) // NewWorld ROM |
937 |
> |
} |
938 |
> |
static const uint8 pvr_read3_dat[] = {0x7e, 0x5f, 0x42, 0xa6, 0x56, 0x52, 0x84, 0x3e}; |
939 |
> |
if ((base = find_rom_data(0x310000, 0x320000, pvr_read3_dat, sizeof(pvr_read3_dat))) != 0) { |
940 |
> |
D(bug("pvr_read3 %08lx\n", base)); |
941 |
> |
lp = (uint32 *)(ROM_BASE + base); |
942 |
|
*lp = htonl(0x82400000 + XLM_PVR); // lwz r18,(theoretical PVR) |
943 |
< |
lp = (uint32 *)(ROM_BASE + 0x314600); |
944 |
< |
if (ntohl(*lp) == 0x7d3f42a6) |
943 |
> |
} |
944 |
> |
static const uint8 pvr_read4_dat[] = {0x7d, 0x3f, 0x42, 0xa6, 0x55, 0x29, 0x84, 0x3e}; |
945 |
> |
if ((base = find_rom_data(0x310000, 0x320000, pvr_read4_dat, sizeof(pvr_read4_dat))) != 0) { |
946 |
> |
D(bug("pvr_read4 %08lx\n", base)); |
947 |
> |
lp = (uint32 *)(ROM_BASE + base); |
948 |
|
*lp = htonl(0x81200000 + XLM_PVR); // lzw r9,(theoritical PVR) |
949 |
+ |
} |
950 |
|
|
951 |
|
// Don't read SDR1 |
952 |
< |
static const uint32 sdr1_ofs[] = {0x174, 0x174, 0x174, 0x17c, 0x19c, 0x19c}; |
953 |
< |
lp = (uint32 *)(ROM_BASE + loc + sdr1_ofs[ROMType]); |
952 |
> |
static const uint8 sdr1_read_dat[] = {0x7d, 0x19, 0x02, 0xa6, 0x55, 0x16, 0x81, 0xde}; |
953 |
> |
if ((base = find_rom_data(0x310000, 0x320000, sdr1_read_dat, sizeof(sdr1_read_dat))) == 0) return false; |
954 |
> |
D(bug("sdr1_read %08lx\n", base)); |
955 |
> |
lp = (uint32 *)(ROM_BASE + base); |
956 |
|
*lp++ = htonl(0x3d00dead); // lis r8,0xdead (pointer to page table) |
957 |
|
*lp++ = htonl(0x3ec0001f); // lis r22,0x001f (size of page table) |
958 |
|
*lp = htonl(POWERPC_NOP); |
959 |
|
|
960 |
< |
// Don't clear page table |
961 |
< |
static const uint32 pgtb_ofs[] = {0x198, 0x198, 0x198, 0x1a0, 0x1c0, 0x1c4}; |
962 |
< |
lp = (uint32 *)(ROM_BASE + loc + pgtb_ofs[ROMType]); |
960 |
> |
// Don't clear page table, don't invalidate TLB |
961 |
> |
static const uint8 pgtb_clear_dat[] = {0x36, 0xd6, 0xff, 0xfc, 0x7e, 0xe8, 0xb1, 0x2e, 0x41, 0x81, 0xff, 0xf8}; |
962 |
> |
if ((base = find_rom_data(0x310000, 0x320000, pgtb_clear_dat, sizeof(pgtb_clear_dat))) == 0) return false; |
963 |
> |
D(bug("pgtb_clear %08lx\n", base + 4)); |
964 |
> |
lp = (uint32 *)(ROM_BASE + base + 4); |
965 |
|
*lp = htonl(POWERPC_NOP); |
966 |
< |
|
967 |
< |
// Don't invalidate TLB |
904 |
< |
static const uint32 tlb_ofs[] = {0x1a0, 0x1a0, 0x1a0, 0x1a8, 0x1c8, 0x1cc}; |
905 |
< |
lp = (uint32 *)(ROM_BASE + loc + tlb_ofs[ROMType]); |
966 |
> |
D(bug("tblie %08lx\n", base + 12)); |
967 |
> |
lp = (uint32 *)(ROM_BASE + base + 12); |
968 |
|
*lp = htonl(POWERPC_NOP); |
969 |
|
|
970 |
|
// Don't create RAM descriptor table |
971 |
< |
static const uint32 desc_ofs[] = {0x350, 0x350, 0x350, 0x358, 0x378, 0x37c}; |
972 |
< |
lp = (uint32 *)(ROM_BASE + loc + desc_ofs[ROMType]); |
971 |
> |
static const uint8 desc_create_dat[] = {0x97, 0xfd, 0x00, 0x04, 0x3b, 0xff, 0x10, 0x00, 0x4b, 0xff, 0xff, 0xdc}; |
972 |
> |
if ((base = find_rom_data(0x310000, 0x320000, desc_create_dat, sizeof(desc_create_dat))) == 0) return false; |
973 |
> |
D(bug("desc_create %08lx\n", base)) |
974 |
> |
lp = (uint32 *)(ROM_BASE + base); |
975 |
|
*lp = htonl(POWERPC_NOP); |
976 |
|
|
977 |
|
// Don't load SRs and BATs |
978 |
< |
static const uint32 sr_ofs[] = {0x3d8, 0x3d8, 0x3d8, 0x3e0, 0x400, 0x404}; |
979 |
< |
lp = (uint32 *)(ROM_BASE + loc + sr_ofs[ROMType]); |
978 |
> |
static const uint8 sr_load[] = {0x7c, 0x00, 0x04, 0xac, 0x83, 0x9d, 0x00, 0x00, 0x93, 0x81, 0x05, 0xe8}; |
979 |
> |
if ((loc = find_rom_data(0x310000, 0x320000, sr_load, sizeof(sr_load))) == 0) return false; |
980 |
> |
static const uint8 sr_load_caller[] = {0x3e, 0xd6, 0xff, 0xff, 0x41, 0x81, 0xff, 0xdc, 0xb2, 0xc8, 0x00, 0x02}; |
981 |
> |
if ((base = find_rom_data(0x310000, 0x320000, sr_load_caller, sizeof(sr_load_caller))) == 0) return false; |
982 |
> |
if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false; |
983 |
> |
D(bug("sr_load %08lx, called from %08lx\n", loc, base)); |
984 |
> |
lp = (uint32 *)(ROM_BASE + base); |
985 |
|
*lp = htonl(POWERPC_NOP); |
986 |
|
|
987 |
|
// Don't mess with SRs |
988 |
< |
static const uint32 sr2_ofs[] = {0x312118, 0x312118, 0x312118, 0x312118, 0x312118, 0x3121b4}; |
989 |
< |
lp = (uint32 *)(ROM_BASE + sr2_ofs[ROMType]); |
988 |
> |
static const uint8 sr_load2_dat[] = {0x83, 0xa1, 0x05, 0xe8, 0x57, 0x7c, 0x3e, 0x78, 0x7f, 0xbd, 0xe0, 0x2e}; |
989 |
> |
if ((base = find_rom_data(0x310000, 0x320000, sr_load2_dat, sizeof(sr_load2_dat))) == 0) return false; |
990 |
> |
D(bug("sr_load2 %08lx\n", base)); |
991 |
> |
lp = (uint32 *)(ROM_BASE + base); |
992 |
|
*lp = htonl(POWERPC_BLR); |
993 |
|
|
994 |
|
// Don't check performance monitor |
995 |
< |
static const uint32 pm_ofs[] = {0x313148, 0x313148, 0x313148, 0x313148, 0x313158, 0x313218}; |
996 |
< |
lp = (uint32 *)(ROM_BASE + pm_ofs[ROMType]); |
997 |
< |
while (ntohl(*lp) != 0x7e58eba6) lp++; |
998 |
< |
*lp++ = htonl(POWERPC_NOP); |
999 |
< |
while (ntohl(*lp) != 0x7e78eaa6) lp++; |
1000 |
< |
*lp++ = htonl(POWERPC_NOP); |
1001 |
< |
while (ntohl(*lp) != 0x7e59eba6) lp++; |
1002 |
< |
*lp++ = htonl(POWERPC_NOP); |
1003 |
< |
while (ntohl(*lp) != 0x7e79eaa6) lp++; |
1004 |
< |
*lp++ = htonl(POWERPC_NOP); |
1005 |
< |
while (ntohl(*lp) != 0x7e5aeba6) lp++; |
1006 |
< |
*lp++ = htonl(POWERPC_NOP); |
1007 |
< |
while (ntohl(*lp) != 0x7e7aeaa6) lp++; |
1008 |
< |
*lp++ = htonl(POWERPC_NOP); |
1009 |
< |
while (ntohl(*lp) != 0x7e5beba6) lp++; |
1010 |
< |
*lp++ = htonl(POWERPC_NOP); |
1011 |
< |
while (ntohl(*lp) != 0x7e7beaa6) lp++; |
1012 |
< |
*lp++ = htonl(POWERPC_NOP); |
1013 |
< |
while (ntohl(*lp) != 0x7e5feba6) lp++; |
1014 |
< |
*lp++ = htonl(POWERPC_NOP); |
1015 |
< |
while (ntohl(*lp) != 0x7e7feaa6) lp++; |
1016 |
< |
*lp++ = htonl(POWERPC_NOP); |
1017 |
< |
while (ntohl(*lp) != 0x7e5ceba6) lp++; |
1018 |
< |
*lp++ = htonl(POWERPC_NOP); |
948 |
< |
while (ntohl(*lp) != 0x7e7ceaa6) lp++; |
949 |
< |
*lp++ = htonl(POWERPC_NOP); |
950 |
< |
while (ntohl(*lp) != 0x7e5deba6) lp++; |
951 |
< |
*lp++ = htonl(POWERPC_NOP); |
952 |
< |
while (ntohl(*lp) != 0x7e7deaa6) lp++; |
953 |
< |
*lp++ = htonl(POWERPC_NOP); |
954 |
< |
while (ntohl(*lp) != 0x7e5eeba6) lp++; |
955 |
< |
*lp++ = htonl(POWERPC_NOP); |
956 |
< |
while (ntohl(*lp) != 0x7e7eeaa6) lp++; |
957 |
< |
*lp++ = htonl(POWERPC_NOP); |
995 |
> |
static const uint8 pm_check_dat[] = {0x7e, 0x58, 0xeb, 0xa6, 0x7e, 0x53, 0x90, 0xf8, 0x7e, 0x78, 0xea, 0xa6}; |
996 |
> |
if ((base = find_rom_data(0x310000, 0x320000, pm_check_dat, sizeof(pm_check_dat))) == 0) return false; |
997 |
> |
D(bug("pm_check %08lx\n", base)); |
998 |
> |
lp = (uint32 *)(ROM_BASE + base); |
999 |
> |
|
1000 |
> |
static const int spr_check_list[] = { |
1001 |
> |
952 /* mmcr0 */, 953 /* pmc1 */, 954 /* pmc2 */, 955 /* sia */, |
1002 |
> |
956 /* mmcr1 */, 957 /* pmc3 */, 958 /* pmc4 */, 959 /* sda */ |
1003 |
> |
}; |
1004 |
> |
|
1005 |
> |
for (int i = 0; i < sizeof(spr_check_list)/sizeof(spr_check_list[0]); i++) { |
1006 |
> |
int spr = spr_check_list[i]; |
1007 |
> |
uint32 mtspr = 0x7e4003a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6); |
1008 |
> |
uint32 mfspr = 0x7e6002a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6); |
1009 |
> |
for (int ofs = 0; ofs < 64; ofs++) { |
1010 |
> |
if (ntohl(lp[ofs]) == mtspr) { |
1011 |
> |
if (ntohl(lp[ofs + 2]) != mfspr) |
1012 |
> |
return false; |
1013 |
> |
D(bug(" SPR%d %08lx\n", spr, base + 4*ofs)); |
1014 |
> |
lp[ofs] = htonl(POWERPC_NOP); |
1015 |
> |
lp[ofs + 2] = htonl(POWERPC_NOP); |
1016 |
> |
} |
1017 |
> |
} |
1018 |
> |
} |
1019 |
|
|
1020 |
|
// Jump to 68k emulator |
1021 |
< |
static const uint32 jump68k_ofs[] = {0x40c, 0x40c, 0x40c, 0x414, 0x434, 0x438}; |
1022 |
< |
lp = (uint32 *)(ROM_BASE + loc + jump68k_ofs[ROMType]); |
1021 |
> |
static const uint8 jump68k_dat[] = {0x7d, 0x92, 0x43, 0xa6, 0x7d, 0x5a, 0x03, 0xa6, 0x7d, 0x7b, 0x03, 0xa6}; |
1022 |
> |
if ((loc = find_rom_data(0x310000, 0x320000, jump68k_dat, sizeof(jump68k_dat))) == 0) return false; |
1023 |
> |
static const uint8 jump68k_caller_dat[] = {0x85, 0x13, 0x00, 0x08, 0x56, 0xbf, 0x50, 0x3e, 0x63, 0xff, 0x0c, 0x00}; |
1024 |
> |
if ((base = find_rom_data(0x310000, 0x320000, jump68k_caller_dat, sizeof(jump68k_caller_dat))) == 0) return false; |
1025 |
> |
if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false; |
1026 |
> |
D(bug("jump68k %08lx, called from %08lx\n", loc, base)); |
1027 |
> |
lp = (uint32 *)(ROM_BASE + base); |
1028 |
|
*lp++ = htonl(0x80610634); // lwz r3,0x0634(r1) (pointer to Emulator Data) |
1029 |
|
*lp++ = htonl(0x8081119c); // lwz r4,0x119c(r1) (pointer to opcode table) |
1030 |
|
*lp++ = htonl(0x80011184); // lwz r0,0x1184(r1) (pointer to emulator init routine) |
1044 |
|
uint32 base; |
1045 |
|
|
1046 |
|
// Overwrite twi instructions |
1047 |
< |
static const uint32 twi_loc[] = {0x36e680, 0x36e6c0, 0x36e6c0, 0x36e6c0, 0x36e740, 0x36e740}; |
1048 |
< |
base = twi_loc[ROMType]; |
1047 |
> |
static const uint8 twi_dat[] = {0x0f, 0xff, 0x00, 0x00, 0x0f, 0xff, 0x00, 0x01, 0x0f, 0xff, 0x00, 0x02}; |
1048 |
> |
if ((base = find_rom_data(0x36e600, 0x36ea00, twi_dat, sizeof(twi_dat))) == 0) return false; |
1049 |
> |
D(bug("twi %08lx\n", base)); |
1050 |
|
lp = (uint32 *)(ROM_BASE + base); |
1051 |
|
*lp++ = htonl(0x48000000 + 0x36f900 - base); // b 0x36f900 (Emulator start) |
1052 |
|
*lp++ = htonl(0x48000000 + 0x36fa00 - base - 4); // b 0x36fa00 (Mixed mode) |
1266 |
|
static bool patch_nanokernel(void) |
1267 |
|
{ |
1268 |
|
uint32 *lp; |
1269 |
+ |
uint32 base, loc; |
1270 |
|
|
1271 |
|
// Patch Mixed Mode trap |
1272 |
< |
lp = (uint32 *)(ROM_BASE + 0x313c90); // Don't translate virtual->physical |
1273 |
< |
while (ntohl(*lp) != 0x3ba10320) lp++; |
1274 |
< |
lp++; |
1275 |
< |
*lp++ = htonl(0x7f7fdb78); // mr r31,r27 |
1276 |
< |
lp++; |
1277 |
< |
*lp = htonl(POWERPC_NOP); |
1278 |
< |
|
1279 |
< |
lp = (uint32 *)(ROM_BASE + 0x313c3c); // Don't activate PPC exception table |
1280 |
< |
while (ntohl(*lp) != 0x39010420) lp++; |
1272 |
> |
static const uint8 virt2phys_dat[] = {0x7d, 0x1b, 0x43, 0x78, 0x3b, 0xa1, 0x03, 0x20}; |
1273 |
> |
if ((base = find_rom_data(0x313000, 0x314000, virt2phys_dat, sizeof(virt2phys_dat))) == 0) return false; |
1274 |
> |
D(bug("virt2phys %08lx\n", base + 8)); |
1275 |
> |
lp = (uint32 *)(ROM_BASE + base + 8); // Don't translate virtual->physical |
1276 |
> |
lp[0] = htonl(0x7f7fdb78); // mr r31,r27 |
1277 |
> |
lp[2] = htonl(POWERPC_NOP); |
1278 |
> |
|
1279 |
> |
static const uint8 ppc_excp_tbl_dat[] = {0x39, 0x01, 0x04, 0x20, 0x7d, 0x13, 0x43, 0xa6}; |
1280 |
> |
if ((base = find_rom_data(0x313000, 0x314000, ppc_excp_tbl_dat, sizeof(ppc_excp_tbl_dat))) == 0) return false; |
1281 |
> |
D(bug("ppc_excp_tbl %08lx\n", base)); |
1282 |
> |
lp = (uint32 *)(ROM_BASE + base); // Don't activate PPC exception table |
1283 |
|
*lp++ = htonl(0x39000000 + MODE_NATIVE); // li r8,MODE_NATIVE |
1284 |
< |
*lp = htonl(0x91000000 + XLM_RUN_MODE); // stw r8,XLM_RUN_MODE |
1284 |
> |
*lp = htonl(0x91000000 + XLM_RUN_MODE); // stw r8,XLM_RUN_MODE |
1285 |
|
|
1286 |
< |
lp = (uint32 *)(ROM_BASE + 0x312e88); // Don't modify MSR to turn on FPU |
1287 |
< |
while (ntohl(*lp) != 0x556b04e2) lp++; |
1288 |
< |
lp -= 4; |
1286 |
> |
static const uint8 save_fpu_dat[] = {0x7d, 0x00, 0x00, 0xa6, 0x61, 0x08, 0x20, 0x00, 0x7d, 0x00, 0x01, 0x24}; |
1287 |
> |
if ((base = find_rom_data(0x310000, 0x314000, save_fpu_dat, sizeof(save_fpu_dat))) == 0) return false; |
1288 |
> |
D(bug("save_fpu %08lx\n", base)); |
1289 |
> |
lp = (uint32 *)(ROM_BASE + base); // Don't modify MSR to turn on FPU |
1290 |
> |
if (ntohl(lp[4]) != 0x556b04e2) return false; |
1291 |
> |
loc = ROM_BASE + base; |
1292 |
> |
#if 1 |
1293 |
> |
// FIXME: is that really intended? |
1294 |
|
*lp++ = htonl(POWERPC_NOP); |
1295 |
|
lp++; |
1296 |
|
*lp++ = htonl(POWERPC_NOP); |
1297 |
|
lp++; |
1298 |
|
*lp = htonl(POWERPC_NOP); |
1299 |
+ |
#else |
1300 |
+ |
lp[0] = htonl(POWERPC_NOP); |
1301 |
+ |
lp[1] = htonl(POWERPC_NOP); |
1302 |
+ |
lp[2] = htonl(POWERPC_NOP); |
1303 |
+ |
lp[3] = htonl(POWERPC_NOP); |
1304 |
+ |
#endif |
1305 |
|
|
1306 |
< |
lp = (uint32 *)(ROM_BASE + 0x312b3c); // Always save FPU state |
1307 |
< |
while (ntohl(*lp) != 0x81010668) lp++; |
1308 |
< |
lp--; |
1306 |
> |
static const uint8 save_fpu_caller_dat[] = {0x93, 0xa6, 0x01, 0xec, 0x93, 0xc6, 0x01, 0xf4, 0x93, 0xe6, 0x01, 0xfc, 0x40}; |
1307 |
> |
if ((base = find_rom_data(0x310000, 0x314000, save_fpu_caller_dat, sizeof(save_fpu_caller_dat))) == 0) return false; |
1308 |
> |
D(bug("save_fpu_caller %08lx\n", base + 12)); |
1309 |
> |
if (powerpc_branch_target(ROM_BASE + base + 12) != loc) return false; |
1310 |
> |
lp = (uint32 *)(ROM_BASE + base + 12); // Always save FPU state |
1311 |
|
*lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312e88 |
1312 |
|
|
1313 |
< |
lp = (uint32 *)(ROM_BASE + 0x312b44); // Don't read DEC |
1314 |
< |
while (ntohl(*lp) != 0x7ff602a6) lp++; |
1315 |
< |
*lp = htonl(0x3be00000); // li r31,0 |
1316 |
< |
|
1317 |
< |
lp = (uint32 *)(ROM_BASE + 0x312b50); // Don't write DEC |
1235 |
< |
while (ntohl(*lp) != 0x7d1603a6) lp++; |
1313 |
> |
static const uint8 mdec_dat[] = {0x7f, 0xf6, 0x02, 0xa6, 0x2c, 0x08, 0x00, 0x00, 0x93, 0xe1, 0x06, 0x68, 0x7d, 0x16, 0x03, 0xa6}; |
1314 |
> |
if ((base = find_rom_data(0x310000, 0x314000, mdec_dat, sizeof(mdec_dat))) == 0) return false; |
1315 |
> |
D(bug("mdec %08lx\n", base)); |
1316 |
> |
lp = (uint32 *)(ROM_BASE + base); // Don't modify DEC |
1317 |
> |
lp[0] = htonl(0x3be00000); // li r31,0 |
1318 |
|
#if 1 |
1319 |
< |
*lp++ = htonl(POWERPC_NOP); |
1320 |
< |
*lp = htonl(POWERPC_NOP); |
1319 |
> |
lp[3] = htonl(POWERPC_NOP); |
1320 |
> |
lp[4] = htonl(POWERPC_NOP); |
1321 |
|
#else |
1322 |
< |
*lp++ = htonl(0x39000040); // li r8,0x40 |
1323 |
< |
*lp = htonl(0x990600e4); // stb r8,0xe4(r6) |
1322 |
> |
lp[3] = htonl(0x39000040); // li r8,0x40 |
1323 |
> |
lp[4] = htonl(0x990600e4); // stb r8,0xe4(r6) |
1324 |
|
#endif |
1325 |
|
|
1326 |
< |
lp = (uint32 *)(ROM_BASE + 0x312b9c); // Always restore FPU state |
1327 |
< |
while (ntohl(*lp) != 0x7c00092d) lp++; |
1328 |
< |
lp--; |
1326 |
> |
static const uint8 restore_fpu_caller_dat[] = {0x81, 0x06, 0x00, 0xf4, 0x81, 0x46, 0x00, 0xfc, 0x7d, 0x09, 0x03, 0xa6, 0x40}; |
1327 |
> |
if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller_dat, sizeof(restore_fpu_caller_dat))) == 0) return false; |
1328 |
> |
D(bug("restore_fpu_caller %08lx\n", base + 12)); |
1329 |
> |
lp = (uint32 *)(ROM_BASE + base + 12); // Always restore FPU state |
1330 |
|
*lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312ddc |
1331 |
|
|
1332 |
< |
lp = (uint32 *)(ROM_BASE + 0x312a68); // Don't activate 68k exception table |
1333 |
< |
while (ntohl(*lp) != 0x39010360) lp++; |
1332 |
> |
static const uint8 m68k_excp_tbl_dat[] = {0x81, 0x21, 0x06, 0x58, 0x39, 0x01, 0x03, 0x60, 0x7d, 0x13, 0x43, 0xa6}; |
1333 |
> |
if ((base = find_rom_data(0x310000, 0x314000, m68k_excp_tbl_dat, sizeof(m68k_excp_tbl_dat))) == 0) return false; |
1334 |
> |
D(bug("m68k_excp %08lx\n", base + 4)); |
1335 |
> |
lp = (uint32 *)(ROM_BASE + base + 4); // Don't activate 68k exception table |
1336 |
|
*lp++ = htonl(0x39000000 + MODE_68K); // li r8,MODE_68K |
1337 |
|
*lp = htonl(0x91000000 + XLM_RUN_MODE); // stw r8,XLM_RUN_MODE |
1338 |
|
|
1339 |
|
// Patch 68k emulator trap routine |
1340 |
< |
lp = (uint32 *)(ROM_BASE + 0x312994); // Always restore FPU state |
1341 |
< |
while (ntohl(*lp) != 0x39260040) lp++; |
1342 |
< |
lp--; |
1340 |
> |
static const uint8 restore_fpu_caller2_dat[] = {0x81, 0x86, 0x00, 0x8c, 0x80, 0x66, 0x00, 0x94, 0x80, 0x86, 0x00, 0x9c, 0x40}; |
1341 |
> |
if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller2_dat, sizeof(restore_fpu_caller2_dat))) == 0) return false; |
1342 |
> |
D(bug("restore_fpu_caller2 %08lx\n", base + 12)); |
1343 |
> |
loc = powerpc_branch_target(ROM_BASE + base + 12) - ROM_BASE; |
1344 |
> |
lp = (uint32 *)(ROM_BASE + base + 12); // Always restore FPU state |
1345 |
|
*lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312dd4 |
1346 |
|
|
1347 |
< |
lp = (uint32 *)(ROM_BASE + 0x312dd8); // Don't modify MSR to turn on FPU |
1348 |
< |
while (ntohl(*lp) != 0x810600e4) lp++; |
1349 |
< |
lp--; |
1347 |
> |
static const uint8 restore_fpu_dat[] = {0x55, 0x68, 0x04, 0xa5, 0x4c, 0x82, 0x00, 0x20, 0x81, 0x06, 0x00, 0xe4}; |
1348 |
> |
if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_dat, sizeof(restore_fpu_dat))) == 0) return false; |
1349 |
> |
D(bug("restore_fpu %08lx\n", base)); |
1350 |
> |
if (base != loc) return false; |
1351 |
> |
lp = (uint32 *)(ROM_BASE + base + 4); // Don't modify MSR to turn on FPU |
1352 |
|
*lp++ = htonl(POWERPC_NOP); |
1353 |
|
lp += 2; |
1354 |
|
*lp++ = htonl(POWERPC_NOP); |
1358 |
|
*lp = htonl(POWERPC_NOP); |
1359 |
|
|
1360 |
|
// Patch trap return routine |
1361 |
< |
lp = (uint32 *)(ROM_BASE + 0x312c20); |
1362 |
< |
while (ntohl(*lp) != 0x7d5a03a6) lp++; |
1361 |
> |
static const uint8 trap_return_dat[] = {0x80, 0xc1, 0x00, 0x18, 0x80, 0x21, 0x00, 0x04, 0x4c, 0x00, 0x00, 0x64}; |
1362 |
> |
if ((base = find_rom_data(0x312000, 0x320000, trap_return_dat, sizeof(trap_return_dat))) == 0) return false; |
1363 |
> |
D(bug("trap_return %08lx\n", base + 8)); |
1364 |
> |
lp = (uint32 *)(ROM_BASE + base + 8); // Replace rfi |
1365 |
> |
*lp = htonl(POWERPC_BCTR); |
1366 |
> |
|
1367 |
> |
while (ntohl(*lp) != 0x7d5a03a6) lp--; |
1368 |
|
*lp++ = htonl(0x7d4903a6); // mtctr r10 |
1369 |
|
*lp++ = htonl(0x7daff120); // mtcr r13 |
1370 |
< |
*lp = htonl(0x48000000 + 0x8000 - (((uint32)lp - ROM_BASE) & 0xffff)); // b ROM_BASE+0x318000 |
1371 |
< |
uint32 xlp = ((uint32)(lp+1) - ROM_BASE) & 0xffff; |
1278 |
< |
|
1279 |
< |
lp = (uint32 *)(ROM_BASE + 0x312c50); // Replace rfi |
1280 |
< |
while (ntohl(*lp) != 0x4c000064) lp++; |
1281 |
< |
*lp = htonl(POWERPC_BCTR); |
1370 |
> |
*lp = htonl(0x48000000 + ((0x318000 - ((uint32)lp - ROM_BASE)) & 0x03fffffc)); // b ROM_BASE+0x318000 |
1371 |
> |
uint32 npc = (uint32)(lp + 1) - ROM_BASE; |
1372 |
|
|
1373 |
|
lp = (uint32 *)(ROM_BASE + 0x318000); |
1374 |
|
#if EMULATED_PPC |
1375 |
|
*lp++ = htonl(NativeOpcode(NATIVE_ENABLE_INTERRUPT)); |
1376 |
< |
*lp = htonl(0x48000000 + ((xlp - 0x8004) & 0x03fffffc)); // b ROM_BASE+0x312c2c |
1376 |
> |
*lp = htonl(0x48000000 + ((npc - 0x318004) & 0x03fffffc)); // b ROM_BASE+0x312c2c |
1377 |
|
#else |
1378 |
|
*lp++ = htonl(0x81400000 + XLM_IRQ_NEST); // lwz r10,XLM_IRQ_NEST |
1379 |
|
*lp++ = htonl(0x394affff); // subi r10,r10,1 |
1380 |
|
*lp++ = htonl(0x91400000 + XLM_IRQ_NEST); // stw r10,XLM_IRQ_NEST |
1381 |
< |
*lp = htonl(0x48000000 + ((xlp - 0x800c) & 0x03fffffc)); // b ROM_BASE+0x312c2c |
1381 |
> |
*lp = htonl(0x48000000 + ((npc - 0x31800c) & 0x03fffffc)); // b ROM_BASE+0x312c2c |
1382 |
|
#endif |
1383 |
|
|
1384 |
|
/* |
1400 |
|
uint32 *lp; |
1401 |
|
uint16 *wp; |
1402 |
|
uint8 *bp; |
1403 |
< |
uint32 base; |
1403 |
> |
uint32 base, loc; |
1404 |
|
|
1405 |
|
// Remove 68k RESET instruction |
1406 |
|
static const uint8 reset_dat[] = {0x4e, 0x70}; |
1641 |
|
*wp = htons(M68K_NOP); |
1642 |
|
|
1643 |
|
// Don't initialize SCC (via 0x1ac) |
1644 |
< |
static const uint8 scc_init_dat[] = {0x48, 0xe7, 0x38, 0xfe}; |
1645 |
< |
if ((base = find_rom_data(0x190, 0x1f0, scc_init_dat, sizeof(scc_init_dat))) == 0) return false; |
1644 |
> |
static const uint8 scc_init_caller_dat[] = {0x21, 0xce, 0x01, 0x08, 0x22, 0x78, 0x0d, 0xd8}; |
1645 |
> |
if ((base = find_rom_data(0x180, 0x1f0, scc_init_caller_dat, sizeof(scc_init_caller_dat))) == 0) return false; |
1646 |
> |
D(bug("scc_init_caller %08lx\n", base + 12)); |
1647 |
> |
wp = (uint16 *)(ROM_BASE + base + 12); |
1648 |
> |
loc = ntohs(wp[1]) + ((uintptr)wp - ROM_BASE) + 2; |
1649 |
> |
static const uint8 scc_init_dat[] = {0x08, 0x38, 0x00, 0x03, 0x0d, 0xd3, 0x67, 0x12, 0x20, 0x78, 0x01, 0xdc, 0x22, 0x78, 0x01, 0xd8}; |
1650 |
> |
if ((base = find_rom_data(loc, loc + 0x80, scc_init_dat, sizeof(scc_init_dat))) != loc) return false; |
1651 |
|
D(bug("scc_init %08lx\n", base)); |
1652 |
< |
wp = (uint16 *)(ROM_BASE + base - 2); |
1558 |
< |
wp = (uint16 *)(ROM_BASE + ntohs(*wp) + base - 2); |
1652 |
> |
wp = (uint16 *)(ROM_BASE + base); |
1653 |
|
*wp++ = htons(M68K_EMUL_OP_RESET); |
1654 |
|
*wp = htons(M68K_RTS); |
1655 |
|
|