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root/cebix/SheepShaver/src/rom_patches.cpp
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Comparing SheepShaver/src/rom_patches.cpp (file contents):
Revision 1.19 by gbeauche, 2003-12-05T12:37:14Z vs.
Revision 1.35 by gbeauche, 2004-07-14T08:24:07Z

# Line 1 | Line 1
1   /*
2   *  rom_patches.cpp - ROM patches
3   *
4 < *  SheepShaver (C) 1997-2002 Christian Bauer and Marc Hellwig
4 > *  SheepShaver (C) 1997-2004 Christian Bauer and Marc Hellwig
5   *
6   *  This program is free software; you can redistribute it and/or modify
7   *  it under the terms of the GNU General Public License as published by
# Line 62 | Line 62
62   const uint32 CHECK_LOAD_PATCH_SPACE = 0x2fcf00;
63   const uint32 PUT_SCRAP_PATCH_SPACE = 0x2fcf80;
64   const uint32 GET_SCRAP_PATCH_SPACE = 0x2fcfc0;
65 < const uint32 ADDR_MAP_PATCH_SPACE = 0x2fd000;
65 > const uint32 ADDR_MAP_PATCH_SPACE = 0x2fd100;
66  
67   // Global variables
68   int ROMType;                            // ROM type
# Line 270 | Line 270 | static uint32 find_rom_trap(uint16 trap)
270  
271  
272   /*
273 + *  Return target of branch instruction specified at ADDR, or 0 if
274 + *  there is no such instruction
275 + */
276 +
277 + static uint32 powerpc_branch_target(uintptr addr)
278 + {
279 +        uint32 opcode = ntohl(*(uint32 *)addr);
280 +        uint32 primop = opcode >> 26;
281 +        uint32 target = 0;
282 +
283 +        if (primop == 18) {                     // Branch
284 +                target = opcode & 0x3fffffc;
285 +                if (target & 0x2000000)
286 +                        target |= 0xfc000000;
287 +                if ((opcode & 2) == 0)
288 +                        target += addr;
289 +        }
290 +        else if (primop == 16) {        // Branch Conditional
291 +                target = (int32)(int16)(opcode & 0xfffc);
292 +                if ((opcode & 2) == 0)
293 +                        target += addr;
294 +        }
295 +        return target;
296 + }
297 +
298 +
299 + /*
300 + *  Search ROM for instruction branching to target address, return 0 if none found
301 + */
302 +
303 + static uint32 find_rom_powerpc_branch(uint32 start, uint32 end, uint32 target)
304 + {
305 +        for (uint32 addr = start; addr < end; addr += 4) {
306 +                if (powerpc_branch_target(ROM_BASE + addr) == ROM_BASE + target)
307 +                        return addr;
308 +        }
309 +        return 0;
310 + }
311 +
312 +
313 + /*
314 + *  Check that requested ROM patch space is really available
315 + */
316 +
317 + static bool check_rom_patch_space(uint32 base, uint32 size)
318 + {
319 +        size = (size + 3) & -4;
320 +        for (int i = 0; i < size; i += 4) {
321 +                uint32 x = ntohl(*(uint32 *)(ROM_BASE + base + i));
322 +                if (x != 0x6b636b63 && x != 0)
323 +                        return false;
324 +        }
325 +        return true;
326 + }
327 +
328 +
329 + /*
330   *  List of audio sifters installed in ROM and System file
331   */
332  
# Line 656 | Line 713 | bool PatchROM(void)
713                  return false;
714  
715          // Check that other ROM addresses point to really free regions
716 <        if (ntohl(*(uint32 *)(ROM_BASE + CHECK_LOAD_PATCH_SPACE)) != 0x6b636b63)
716 >        if (!check_rom_patch_space(CHECK_LOAD_PATCH_SPACE, 0x40))
717                  return false;
718 <        if (ntohl(*(uint32 *)(ROM_BASE + PUT_SCRAP_PATCH_SPACE)) != 0x6b636b63)
718 >        if (!check_rom_patch_space(PUT_SCRAP_PATCH_SPACE, 0x40))
719                  return false;
720 <        if (ntohl(*(uint32 *)(ROM_BASE + GET_SCRAP_PATCH_SPACE)) != 0x6b636b63)
720 >        if (!check_rom_patch_space(GET_SCRAP_PATCH_SPACE, 0x40))
721                  return false;
722 <        if (ntohl(*(uint32 *)(ROM_BASE + ADDR_MAP_PATCH_SPACE)) != 0x6b636b63)
722 >        if (!check_rom_patch_space(ADDR_MAP_PATCH_SPACE - 10 * 4, 0x100))
723                  return false;
724  
725          // Apply patches
# Line 697 | Line 754 | bool PatchROM(void)
754   static bool patch_nanokernel_boot(void)
755   {
756          uint32 *lp;
757 +        uint32 base, loc;
758  
759          // ROM boot structure patches
760          lp = (uint32 *)(ROM_BASE + 0x30d000);
# Line 709 | Line 767 | static bool patch_nanokernel_boot(void)
767          lp[0xfd8 >> 2] = htonl(ROM_BASE + 0x2a);                // 68k reset vector
768  
769          // Skip SR/BAT/SDR init
770 +        loc = 0x310000;
771          if (ROMType == ROMTYPE_GAZELLE || ROMType == ROMTYPE_GOSSAMER || ROMType == ROMTYPE_NEWWORLD) {
772 <                lp = (uint32 *)(ROM_BASE + 0x310000);
772 >                lp = (uint32 *)(ROM_BASE + loc);
773                  *lp++ = htonl(POWERPC_NOP);
774                  *lp = htonl(0x38000000);
775          }
776 <        static const uint32 sr_init_loc[] = {0x3101b0, 0x3101b0, 0x3101b0, 0x3101ec, 0x3101fc, 0x310200};
777 <        lp = (uint32 *)(ROM_BASE + 0x310008);
778 <        *lp = htonl(0x48000000 | (sr_init_loc[ROMType] - 8) & 0xffff);  // b            ROM_BASE+0x3101b0
779 <        lp = (uint32 *)(ROM_BASE + sr_init_loc[ROMType]);
776 >        static const uint8 sr_init_dat[] = {0x35, 0x4a, 0xff, 0xfc, 0x7d, 0x86, 0x50, 0x2e};
777 >        if ((base = find_rom_data(0x3101b0, 0x3105b0, sr_init_dat, sizeof(sr_init_dat))) == 0) return false;
778 >        D(bug("sr_init %08lx\n", base));
779 >        lp = (uint32 *)(ROM_BASE + loc + 8);
780 >        *lp = htonl(0x48000000 | ((base - loc - 8) & 0x3fffffc));       // b            ROM_BASE+0x3101b0
781 >        lp = (uint32 *)(ROM_BASE + base);
782          *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);            // lwz  r1,(pointer to Kernel Data)
783          *lp++ = htonl(0x3da0dead);              // lis  r13,0xdead      (start of kernel memory)
784          *lp++ = htonl(0x3dc00010);              // lis  r14,0x0010      (size of page table)
785          *lp = htonl(0x3de00010);                // lis  r15,0x0010      (size of kernel memory)
786  
787          // Don't read PVR
788 <        static const uint32 pvr_loc[] = {0x3103b0, 0x3103b4, 0x3103b4, 0x310400, 0x310430, 0x310438};
789 <        lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
788 >        static const uint8 pvr_read_dat[] = {0x7d, 0x9f, 0x42, 0xa6};
789 >        if ((base = find_rom_data(0x3103b0, 0x3108b0, pvr_read_dat, sizeof(pvr_read_dat))) == 0) return false;
790 >        D(bug("pvr_read %08lx\n", base));
791 >        lp = (uint32 *)(ROM_BASE + base);
792          *lp = htonl(0x81800000 + XLM_PVR);      // lwz  r12,(theoretical PVR)
793  
794          // Set CPU specific data (even if ROM doesn't have support for that CPU)
732        lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
795          if (ntohl(lp[6]) != 0x2c0c0001)
796                  return false;
797          uint32 ofs = ntohl(lp[7]) & 0xffff;
798          D(bug("ofs %08lx\n", ofs));
799          lp[8] = htonl((ntohl(lp[8]) & 0xffff) | 0x48000000);    // beq -> b
800 <        uint32 loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
800 >        loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
801          D(bug("loc %08lx\n", loc));
802          lp = (uint32 *)(ROM_BASE + ofs + 0x310000);
803          switch (PVR >> 16) {
# Line 785 | Line 847 | static bool patch_nanokernel_boot(void)
847                          lp[7] = htonl(0x00040004);      // Inst cache assoc/Data cache assoc
848                          lp[8] = htonl(0x00400002);      // TLB total size/TLB assoc
849                          break;
850 <                case 8:         // 750
850 >                case 8:         // 750, 750FX
851 >                case 0x7000:
852                          lp[0] = htonl(0x1000);          // Page size
853                          lp[1] = htonl(0x8000);          // Data cache size
854                          lp[2] = htonl(0x8000);          // Inst cache size
# Line 809 | Line 872 | static bool patch_nanokernel_boot(void)
872                          lp[8] = htonl(0x00800002);      // TLB total size/TLB assoc
873                          break;
874   //              case 11:        // X704?
875 <                case 12:        // ???
875 >                case 12:        // 7400, 7410, 7450, 7455, 7457
876 >                case 0x800c:
877 >                case 0x8000:
878 >                case 0x8001:
879 >                case 0x8002:
880                          lp[0] = htonl(0x1000);          // Page size
881                          lp[1] = htonl(0x8000);          // Data cache size
882                          lp[2] = htonl(0x8000);          // Inst cache size
# Line 844 | Line 911 | static bool patch_nanokernel_boot(void)
911                          lp[7] = htonl(0x00080008);      // Inst cache assoc/Data cache assoc
912                          lp[8] = htonl(0x00800004);      // TLB total size/TLB assoc
913                          break;
914 +                case 0x39:      // 970
915 +                        lp[0] = htonl(0x1000);          // Page size
916 +                        lp[1] = htonl(0x8000);          // Data cache size
917 +                        lp[2] = htonl(0x10000);         // Inst cache size
918 +                        lp[3] = htonl(0x00200020);      // Coherency block size/Reservation granule size
919 +                        lp[4] = htonl(0x00010020);      // Unified caches/Inst cache line size
920 +                        lp[5] = htonl(0x00200020);      // Data cache line size/Data cache block size touch
921 +                        lp[6] = htonl(0x00800080);      // Inst cache block size/Data cache block size
922 +                        lp[7] = htonl(0x00020002);      // Inst cache assoc/Data cache assoc
923 +                        lp[8] = htonl(0x02000004);      // TLB total size/TLB assoc
924 +                        break;
925                  default:
926                          printf("WARNING: Unknown CPU type\n");
927                          break;
928          }
929  
930          // Don't set SPRG3, don't test MQ
931 <        lp = (uint32 *)(ROM_BASE + loc + 0x20);
932 <        *lp++ = htonl(POWERPC_NOP);
933 <        lp++;
934 <        *lp++ = htonl(POWERPC_NOP);
935 <        lp++;
936 <        *lp = htonl(POWERPC_NOP);
931 >        static const uint8 sprg3_mq_dat[] = {0x7d, 0x13, 0x43, 0xa6, 0x3d, 0x00, 0x00, 0x04, 0x7d, 0x00, 0x03, 0xa6, 0x39, 0x00, 0x00, 0x00, 0x7d, 0x00, 0x02, 0xa6};
932 >        if ((base = find_rom_data(loc + 0x20, loc + 0x60, sprg3_mq_dat, sizeof(sprg3_mq_dat))) == 0) return false;
933 >        D(bug("sprg3/mq %08lx\n", base));
934 >        lp = (uint32 *)(ROM_BASE + base);
935 >        lp[0] = htonl(POWERPC_NOP);
936 >        lp[2] = htonl(POWERPC_NOP);
937 >        lp[4] = htonl(POWERPC_NOP);
938  
939          // Don't read MSR
940 <        lp = (uint32 *)(ROM_BASE + loc + 0x40);
940 >        static const uint8 msr_dat[] = {0x7d, 0xc0, 0x00, 0xa6};
941 >        if ((base = find_rom_data(loc + 0x40, loc + 0x80, msr_dat, sizeof(msr_dat))) == 0) return false;
942 >        D(bug("msr %08lx\n", base));
943 >        lp = (uint32 *)(ROM_BASE + base);
944          *lp = htonl(0x39c00000);                // li   r14,0
945  
946          // Don't write to DEC
# Line 868 | Line 950 | static bool patch_nanokernel_boot(void)
950          D(bug("loc %08lx\n", loc));
951  
952          // Don't set SPRG3
953 <        lp = (uint32 *)(ROM_BASE + loc + 0x2c);
953 >        static const uint8 sprg3_dat[] = {0x39, 0x21, 0x03, 0x60, 0x7d, 0x33, 0x43, 0xa6, 0x39, 0x01, 0x04, 0x20};
954 >        if ((base = find_rom_data(0x310000, 0x314000, sprg3_dat, sizeof(sprg3_dat))) == 0) return false;
955 >        D(bug("sprg3 %08lx\n", base + 4));
956 >        lp = (uint32 *)(ROM_BASE + base + 4);
957          *lp = htonl(POWERPC_NOP);
958  
959          // Don't read PVR
960 <        static const uint32 pvr_ofs[] = {0x138, 0x138, 0x138, 0x140, 0x148, 0x148};
961 <        lp = (uint32 *)(ROM_BASE + loc + pvr_ofs[ROMType]);
960 >        static const uint8 pvr_read2_dat[] = {0x7e, 0xff, 0x42, 0xa6, 0x56, 0xf7, 0x84, 0x3e};
961 >        if ((base = find_rom_data(0x310000, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) == 0) return false;
962 >        D(bug("pvr_read2 %08lx\n", base));
963 >        lp = (uint32 *)(ROM_BASE + base);
964          *lp = htonl(0x82e00000 + XLM_PVR);              // lwz  r23,(theoretical PVR)
965 <        lp = (uint32 *)(ROM_BASE + loc + 0x170);
966 <        if (ntohl(*lp) == 0x7eff42a6)   // NewWorld or Gossamer ROM
965 >        if ((base = find_rom_data(base + 4, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) != 0) {
966 >                D(bug("pvr_read2 %08lx\n", base));
967 >                lp = (uint32 *)(ROM_BASE + base);
968                  *lp = htonl(0x82e00000 + XLM_PVR);      // lwz  r23,(theoretical PVR)
969 <        lp = (uint32 *)(ROM_BASE + 0x313134);
970 <        if (ntohl(*lp) == 0x7e5f42a6)
971 <                *lp = htonl(0x82400000 + XLM_PVR);      // lwz  r18,(theoretical PVR)
972 <        lp = (uint32 *)(ROM_BASE + 0x3131f4);
973 <        if (ntohl(*lp) == 0x7e5f42a6)   // NewWorld ROM
969 >        }
970 >        static const uint8 pvr_read3_dat[] = {0x7e, 0x5f, 0x42, 0xa6, 0x56, 0x52, 0x84, 0x3e};
971 >        if ((base = find_rom_data(0x310000, 0x320000, pvr_read3_dat, sizeof(pvr_read3_dat))) != 0) {
972 >                D(bug("pvr_read3 %08lx\n", base));
973 >                lp = (uint32 *)(ROM_BASE + base);
974                  *lp = htonl(0x82400000 + XLM_PVR);      // lwz  r18,(theoretical PVR)
975 <        lp = (uint32 *)(ROM_BASE + 0x314600);
976 <        if (ntohl(*lp) == 0x7d3f42a6)
975 >        }
976 >        static const uint8 pvr_read4_dat[] = {0x7d, 0x3f, 0x42, 0xa6, 0x55, 0x29, 0x84, 0x3e};
977 >        if ((base = find_rom_data(0x310000, 0x320000, pvr_read4_dat, sizeof(pvr_read4_dat))) != 0) {
978 >                D(bug("pvr_read4 %08lx\n", base));
979 >                lp = (uint32 *)(ROM_BASE + base);
980                  *lp = htonl(0x81200000 + XLM_PVR);      // lzw  r9,(theoritical PVR)
981 +        }
982  
983          // Don't read SDR1
984 <        static const uint32 sdr1_ofs[] = {0x174, 0x174, 0x174, 0x17c, 0x19c, 0x19c};
985 <        lp = (uint32 *)(ROM_BASE + loc + sdr1_ofs[ROMType]);
984 >        static const uint8 sdr1_read_dat[] = {0x7d, 0x19, 0x02, 0xa6, 0x55, 0x16, 0x81, 0xde};
985 >        if ((base = find_rom_data(0x310000, 0x320000, sdr1_read_dat, sizeof(sdr1_read_dat))) == 0) return false;
986 >        D(bug("sdr1_read %08lx\n", base));
987 >        lp = (uint32 *)(ROM_BASE + base);
988          *lp++ = htonl(0x3d00dead);              // lis  r8,0xdead               (pointer to page table)
989          *lp++ = htonl(0x3ec0001f);              // lis  r22,0x001f      (size of page table)
990          *lp = htonl(POWERPC_NOP);
991  
992 <        // Don't clear page table
993 <        static const uint32 pgtb_ofs[] = {0x198, 0x198, 0x198, 0x1a0, 0x1c0, 0x1c4};
994 <        lp = (uint32 *)(ROM_BASE + loc + pgtb_ofs[ROMType]);
992 >        // Don't clear page table, don't invalidate TLB
993 >        static const uint8 pgtb_clear_dat[] = {0x36, 0xd6, 0xff, 0xfc, 0x7e, 0xe8, 0xb1, 0x2e, 0x41, 0x81, 0xff, 0xf8};
994 >        if ((base = find_rom_data(0x310000, 0x320000, pgtb_clear_dat, sizeof(pgtb_clear_dat))) == 0) return false;
995 >        D(bug("pgtb_clear %08lx\n", base + 4));
996 >        lp = (uint32 *)(ROM_BASE + base + 4);
997          *lp = htonl(POWERPC_NOP);
998 <
999 <        // Don't invalidate TLB
904 <        static const uint32 tlb_ofs[] = {0x1a0, 0x1a0, 0x1a0, 0x1a8, 0x1c8, 0x1cc};
905 <        lp = (uint32 *)(ROM_BASE + loc + tlb_ofs[ROMType]);
998 >        D(bug("tblie %08lx\n", base + 12));
999 >        lp = (uint32 *)(ROM_BASE + base + 12);
1000          *lp = htonl(POWERPC_NOP);
1001  
1002          // Don't create RAM descriptor table
1003 <        static const uint32 desc_ofs[] = {0x350, 0x350, 0x350, 0x358, 0x378, 0x37c};
1004 <        lp = (uint32 *)(ROM_BASE + loc + desc_ofs[ROMType]);
1003 >        static const uint8 desc_create_dat[] = {0x97, 0xfd, 0x00, 0x04, 0x3b, 0xff, 0x10, 0x00, 0x4b, 0xff, 0xff, 0xdc};
1004 >        if ((base = find_rom_data(0x310000, 0x320000, desc_create_dat, sizeof(desc_create_dat))) == 0) return false;
1005 >        D(bug("desc_create %08lx\n", base))
1006 >        lp = (uint32 *)(ROM_BASE + base);
1007          *lp = htonl(POWERPC_NOP);
1008  
1009          // Don't load SRs and BATs
1010 <        static const uint32 sr_ofs[] = {0x3d8, 0x3d8, 0x3d8, 0x3e0, 0x400, 0x404};
1011 <        lp = (uint32 *)(ROM_BASE + loc + sr_ofs[ROMType]);
1010 >        static const uint8 sr_load[] = {0x7c, 0x00, 0x04, 0xac, 0x83, 0x9d, 0x00, 0x00, 0x93, 0x81, 0x05, 0xe8};
1011 >        if ((loc = find_rom_data(0x310000, 0x320000, sr_load, sizeof(sr_load))) == 0) return false;
1012 >        static const uint8 sr_load_caller[] = {0x3e, 0xd6, 0xff, 0xff, 0x41, 0x81, 0xff, 0xdc, 0xb2, 0xc8, 0x00, 0x02};
1013 >        if ((base = find_rom_data(0x310000, 0x320000, sr_load_caller, sizeof(sr_load_caller))) == 0) return false;
1014 >        if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false;
1015 >        D(bug("sr_load %08lx, called from %08lx\n", loc, base));
1016 >        lp = (uint32 *)(ROM_BASE + base);
1017          *lp = htonl(POWERPC_NOP);
1018  
1019          // Don't mess with SRs
1020 <        static const uint32 sr2_ofs[] = {0x312118, 0x312118, 0x312118, 0x312118, 0x312118, 0x3121b4};
1021 <        lp = (uint32 *)(ROM_BASE + sr2_ofs[ROMType]);
1020 >        static const uint8 sr_load2_dat[] = {0x83, 0xa1, 0x05, 0xe8, 0x57, 0x7c, 0x3e, 0x78, 0x7f, 0xbd, 0xe0, 0x2e};
1021 >        if ((base = find_rom_data(0x310000, 0x320000, sr_load2_dat, sizeof(sr_load2_dat))) == 0) return false;
1022 >        D(bug("sr_load2 %08lx\n", base));
1023 >        lp = (uint32 *)(ROM_BASE + base);
1024          *lp = htonl(POWERPC_BLR);
1025  
1026          // Don't check performance monitor
1027 <        static const uint32 pm_ofs[] = {0x313148, 0x313148, 0x313148, 0x313148, 0x313158, 0x313218};
1028 <        lp = (uint32 *)(ROM_BASE + pm_ofs[ROMType]);
1029 <        while (ntohl(*lp) != 0x7e58eba6) lp++;
1030 <        *lp++ = htonl(POWERPC_NOP);
1031 <        while (ntohl(*lp) != 0x7e78eaa6) lp++;
1032 <        *lp++ = htonl(POWERPC_NOP);
1033 <        while (ntohl(*lp) != 0x7e59eba6) lp++;
1034 <        *lp++ = htonl(POWERPC_NOP);
1035 <        while (ntohl(*lp) != 0x7e79eaa6) lp++;
1036 <        *lp++ = htonl(POWERPC_NOP);
1037 <        while (ntohl(*lp) != 0x7e5aeba6) lp++;
1038 <        *lp++ = htonl(POWERPC_NOP);
1039 <        while (ntohl(*lp) != 0x7e7aeaa6) lp++;
1040 <        *lp++ = htonl(POWERPC_NOP);
1041 <        while (ntohl(*lp) != 0x7e5beba6) lp++;
1042 <        *lp++ = htonl(POWERPC_NOP);
1043 <        while (ntohl(*lp) != 0x7e7beaa6) lp++;
1044 <        *lp++ = htonl(POWERPC_NOP);
1045 <        while (ntohl(*lp) != 0x7e5feba6) lp++;
1046 <        *lp++ = htonl(POWERPC_NOP);
1047 <        while (ntohl(*lp) != 0x7e7feaa6) lp++;
1048 <        *lp++ = htonl(POWERPC_NOP);
1049 <        while (ntohl(*lp) != 0x7e5ceba6) lp++;
1050 <        *lp++ = htonl(POWERPC_NOP);
948 <        while (ntohl(*lp) != 0x7e7ceaa6) lp++;
949 <        *lp++ = htonl(POWERPC_NOP);
950 <        while (ntohl(*lp) != 0x7e5deba6) lp++;
951 <        *lp++ = htonl(POWERPC_NOP);
952 <        while (ntohl(*lp) != 0x7e7deaa6) lp++;
953 <        *lp++ = htonl(POWERPC_NOP);
954 <        while (ntohl(*lp) != 0x7e5eeba6) lp++;
955 <        *lp++ = htonl(POWERPC_NOP);
956 <        while (ntohl(*lp) != 0x7e7eeaa6) lp++;
957 <        *lp++ = htonl(POWERPC_NOP);
1027 >        static const uint8 pm_check_dat[] = {0x7e, 0x58, 0xeb, 0xa6, 0x7e, 0x53, 0x90, 0xf8, 0x7e, 0x78, 0xea, 0xa6};
1028 >        if ((base = find_rom_data(0x310000, 0x320000, pm_check_dat, sizeof(pm_check_dat))) == 0) return false;
1029 >        D(bug("pm_check %08lx\n", base));
1030 >        lp = (uint32 *)(ROM_BASE + base);
1031 >        
1032 >        static const int spr_check_list[] = {
1033 >                952 /* mmcr0 */, 953 /* pmc1 */, 954 /* pmc2 */, 955 /* sia */,
1034 >                956 /* mmcr1 */, 957 /* pmc3 */, 958 /* pmc4 */, 959 /* sda */
1035 >        };
1036 >
1037 >        for (int i = 0; i < sizeof(spr_check_list)/sizeof(spr_check_list[0]); i++) {
1038 >                int spr = spr_check_list[i];
1039 >                uint32 mtspr = 0x7e4003a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6);
1040 >                uint32 mfspr = 0x7e6002a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6);
1041 >                for (int ofs = 0; ofs < 64; ofs++) {
1042 >                        if (ntohl(lp[ofs]) == mtspr) {
1043 >                                if (ntohl(lp[ofs + 2]) != mfspr)
1044 >                                        return false;
1045 >                                D(bug("  SPR%d %08lx\n", spr, base + 4*ofs));
1046 >                                lp[ofs] = htonl(POWERPC_NOP);
1047 >                                lp[ofs + 2] = htonl(POWERPC_NOP);
1048 >                        }
1049 >                }
1050 >        }
1051  
1052          // Jump to 68k emulator
1053 <        static const uint32 jump68k_ofs[] = {0x40c, 0x40c, 0x40c, 0x414, 0x434, 0x438};
1054 <        lp = (uint32 *)(ROM_BASE + loc + jump68k_ofs[ROMType]);
1053 >        static const uint8 jump68k_dat[] = {0x7d, 0x92, 0x43, 0xa6, 0x7d, 0x5a, 0x03, 0xa6, 0x7d, 0x7b, 0x03, 0xa6};
1054 >        if ((loc = find_rom_data(0x310000, 0x320000, jump68k_dat, sizeof(jump68k_dat))) == 0) return false;
1055 >        static const uint8 jump68k_caller_dat[] = {0x85, 0x13, 0x00, 0x08, 0x56, 0xbf, 0x50, 0x3e, 0x63, 0xff, 0x0c, 0x00};
1056 >        if ((base = find_rom_data(0x310000, 0x320000, jump68k_caller_dat, sizeof(jump68k_caller_dat))) == 0) return false;
1057 >        if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false;
1058 >        D(bug("jump68k %08lx, called from %08lx\n", loc, base));
1059 >        lp = (uint32 *)(ROM_BASE + base);
1060          *lp++ = htonl(0x80610634);              // lwz  r3,0x0634(r1)   (pointer to Emulator Data)
1061          *lp++ = htonl(0x8081119c);              // lwz  r4,0x119c(r1)   (pointer to opcode table)
1062          *lp++ = htonl(0x80011184);              // lwz  r0,0x1184(r1)   (pointer to emulator init routine)
# Line 975 | Line 1073 | static bool patch_nanokernel_boot(void)
1073   static bool patch_68k_emul(void)
1074   {
1075          uint32 *lp;
1076 <        uint32 base;
1076 >        uint32 base, loc;
1077  
1078          // Overwrite twi instructions
1079 <        static const uint32 twi_loc[] = {0x36e680, 0x36e6c0, 0x36e6c0, 0x36e6c0, 0x36e740, 0x36e740};
1080 <        base = twi_loc[ROMType];
1079 >        static const uint8 twi_dat[] = {0x0f, 0xff, 0x00, 0x00, 0x0f, 0xff, 0x00, 0x01, 0x0f, 0xff, 0x00, 0x02};
1080 >        if ((base = find_rom_data(0x36e600, 0x36ea00, twi_dat, sizeof(twi_dat))) == 0) return false;
1081 >        D(bug("twi %08lx\n", base));
1082          lp = (uint32 *)(ROM_BASE + base);
1083          *lp++ = htonl(0x48000000 + 0x36f900 - base);            // b 0x36f900 (Emulator start)
1084          *lp++ = htonl(0x48000000 + 0x36fa00 - base - 4);        // b 0x36fa00 (Mixed mode)
# Line 1038 | Line 1137 | static bool patch_68k_emul(void)
1137          // Extra routine for 68k emulator start
1138          lp = (uint32 *)(ROM_BASE + 0x36f900);
1139          *lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1041 #if EMULATED_PPC
1042        *lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1043 #else
1140          *lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1141          *lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
1142          *lp++ = htonl(0x90200000 + XLM_IRQ_NEST);       // stw          r1,XLM_IRQ_NEST
1047 #endif
1143          *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz              r1,XLM_KERNEL_DATA
1144          *lp++ = htonl(0x90c10018);                                      // stw          r6,0x18(r1)
1145          *lp++ = htonl(0x7cc902a6);                                      // mfctr        r6
# Line 1072 | Line 1167 | static bool patch_68k_emul(void)
1167          // Extra routine for Mixed Mode
1168          lp = (uint32 *)(ROM_BASE + 0x36fa00);
1169          *lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1075 #if EMULATED_PPC
1076        *lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1077 #else
1170          *lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1171          *lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
1172          *lp++ = htonl(0x90200000 + XLM_IRQ_NEST);       // stw          r1,XLM_IRQ_NEST
1081 #endif
1173          *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz              r1,XLM_KERNEL_DATA
1174          *lp++ = htonl(0x90c10018);                                      // stw          r6,0x18(r1)
1175          *lp++ = htonl(0x7cc902a6);                                      // mfctr        r6
# Line 1106 | Line 1197 | static bool patch_68k_emul(void)
1197          // Extra routine for Reset/FC1E opcode
1198          lp = (uint32 *)(ROM_BASE + 0x36fb00);
1199          *lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1109 #if EMULATED_PPC
1110        *lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1111 #else
1200          *lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1201          *lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
1202          *lp++ = htonl(0x90200000 + XLM_IRQ_NEST);       // stw          r1,XLM_IRQ_NEST
1115 #endif
1203          *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz              r1,XLM_KERNEL_DATA
1204          *lp++ = htonl(0x90c10018);                                      // stw          r6,0x18(r1)
1205          *lp++ = htonl(0x7cc902a6);                                      // mfctr        r6
# Line 1140 | Line 1227 | static bool patch_68k_emul(void)
1227          // Extra routine for FE0A opcode (QuickDraw 3D needs this)
1228          lp = (uint32 *)(ROM_BASE + 0x36fc00);
1229          *lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1143 #if EMULATED_PPC
1144        *lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1145 #else
1230          *lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1231          *lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
1232          *lp++ = htonl(0x90200000 + XLM_IRQ_NEST);       // stw          r1,XLM_IRQ_NEST
1149 #endif
1233          *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz              r1,XLM_KERNEL_DATA
1234          *lp++ = htonl(0x90c10018);                                      // stw          r6,0x18(r1)
1235          *lp++ = htonl(0x7cc902a6);                                      // mfctr        r6
# Line 1182 | Line 1265 | static bool patch_68k_emul(void)
1265          return false;
1266   dr_found:
1267          lp++;
1268 <        *lp = htonl(0x48000000 + 0xf000 - (((uint32)lp - ROM_BASE) & 0xffff));          // b    DR_CACHE_BASE+0x1f000
1269 <        lp = (uint32 *)(ROM_BASE + 0x37f000);
1270 <        *lp++ = htonl(0x3c000000 + ((ROM_BASE + 0x46d0a4) >> 16));              // lis  r0,xxx
1271 <        *lp++ = htonl(0x60000000 + ((ROM_BASE + 0x46d0a4) & 0xffff));   // ori  r0,r0,xxx
1272 <        *lp++ = htonl(0x7c0903a6);                                                                              // mtctr        r0
1273 <        *lp = htonl(POWERPC_BCTR);                                                                              // bctr
1268 >        loc = (uint32)lp - ROM_BASE;
1269 >        if ((base = powerpc_branch_target(ROM_BASE + loc)) == 0) base = ROM_BASE + loc;
1270 >        static const uint8 dr_ret_dat[] = {0x80, 0xbf, 0x08, 0x14, 0x53, 0x19, 0x4d, 0xac, 0x7c, 0xa8, 0x03, 0xa6};
1271 >        if ((base = find_rom_data(base - ROM_BASE, 0x380000, dr_ret_dat, sizeof(dr_ret_dat))) == 0) return false;
1272 >        D(bug("dr_ret %08lx\n", base));
1273 >        if (base != loc) {
1274 >                // OldWorld ROMs contain an absolute branch
1275 >                D(bug(" patching absolute branch at %08x\n", (uint32)lp - ROM_BASE));
1276 >                *lp = htonl(0x48000000 + 0xf000 - (((uint32)lp - ROM_BASE) & 0xffff));          // b    DR_CACHE_BASE+0x1f000
1277 >                lp = (uint32 *)(ROM_BASE + 0x37f000);
1278 >                *lp++ = htonl(0x3c000000 + ((ROM_BASE + base) >> 16));                  // lis  r0,xxx
1279 >                *lp++ = htonl(0x60000000 + ((ROM_BASE + base) & 0xffff));               // ori  r0,r0,xxx
1280 >                *lp++ = htonl(0x7c0803a6);                                                                              // mtlr r0
1281 >                *lp = htonl(POWERPC_BLR);                                                                               // blr
1282 >        }
1283          return true;
1284   }
1285  
# Line 1199 | Line 1291 | dr_found:
1291   static bool patch_nanokernel(void)
1292   {
1293          uint32 *lp;
1294 +        uint32 base, loc;
1295  
1296          // Patch Mixed Mode trap
1297 <        lp = (uint32 *)(ROM_BASE + 0x313c90);   // Don't translate virtual->physical
1298 <        while (ntohl(*lp) != 0x3ba10320) lp++;
1299 <        lp++;
1300 <        *lp++ = htonl(0x7f7fdb78);                                      // mr           r31,r27
1301 <        lp++;
1302 <        *lp = htonl(POWERPC_NOP);
1303 <
1304 <        lp = (uint32 *)(ROM_BASE + 0x313c3c);   // Don't activate PPC exception table
1305 <        while (ntohl(*lp) != 0x39010420) lp++;
1297 >        static const uint8 virt2phys_dat[] = {0x7d, 0x1b, 0x43, 0x78, 0x3b, 0xa1, 0x03, 0x20};
1298 >        if ((base = find_rom_data(0x313000, 0x314000, virt2phys_dat, sizeof(virt2phys_dat))) == 0) return false;
1299 >        D(bug("virt2phys %08lx\n", base + 8));
1300 >        lp = (uint32 *)(ROM_BASE + base + 8);   // Don't translate virtual->physical
1301 >        lp[0] = htonl(0x7f7fdb78);                                      // mr           r31,r27
1302 >        lp[2] = htonl(POWERPC_NOP);
1303 >
1304 >        static const uint8 ppc_excp_tbl_dat[] = {0x39, 0x01, 0x04, 0x20, 0x7d, 0x13, 0x43, 0xa6};
1305 >        if ((base = find_rom_data(0x313000, 0x314000, ppc_excp_tbl_dat, sizeof(ppc_excp_tbl_dat))) == 0) return false;
1306 >        D(bug("ppc_excp_tbl %08lx\n", base));
1307 >        lp = (uint32 *)(ROM_BASE + base);               // Don't activate PPC exception table
1308          *lp++ = htonl(0x39000000 + MODE_NATIVE);        // li   r8,MODE_NATIVE
1309 <        *lp = htonl(0x91000000 + XLM_RUN_MODE); // stw  r8,XLM_RUN_MODE
1309 >        *lp = htonl(0x91000000 + XLM_RUN_MODE);         // stw  r8,XLM_RUN_MODE
1310  
1311 <        lp = (uint32 *)(ROM_BASE + 0x312e88);   // Don't modify MSR to turn on FPU
1312 <        while (ntohl(*lp) != 0x556b04e2) lp++;
1313 <        lp -= 4;
1311 >        static const uint8 save_fpu_dat[] = {0x7d, 0x00, 0x00, 0xa6, 0x61, 0x08, 0x20, 0x00, 0x7d, 0x00, 0x01, 0x24};
1312 >        if ((base = find_rom_data(0x310000, 0x314000, save_fpu_dat, sizeof(save_fpu_dat))) == 0) return false;
1313 >        D(bug("save_fpu %08lx\n", base));
1314 >        lp = (uint32 *)(ROM_BASE + base);               // Don't modify MSR to turn on FPU
1315 >        if (ntohl(lp[4]) != 0x556b04e2) return false;
1316 >        loc = ROM_BASE + base;
1317 > #if 1
1318 >        // FIXME: is that really intended?
1319          *lp++ = htonl(POWERPC_NOP);
1320          lp++;
1321          *lp++ = htonl(POWERPC_NOP);
1322          lp++;
1323          *lp = htonl(POWERPC_NOP);
1324 + #else
1325 +        lp[0] = htonl(POWERPC_NOP);
1326 +        lp[1] = htonl(POWERPC_NOP);
1327 +        lp[2] = htonl(POWERPC_NOP);
1328 +        lp[3] = htonl(POWERPC_NOP);
1329 + #endif
1330  
1331 <        lp = (uint32 *)(ROM_BASE + 0x312b3c);   // Always save FPU state
1332 <        while (ntohl(*lp) != 0x81010668) lp++;
1333 <        lp--;
1331 >        static const uint8 save_fpu_caller_dat[] = {0x93, 0xa6, 0x01, 0xec, 0x93, 0xc6, 0x01, 0xf4, 0x93, 0xe6, 0x01, 0xfc, 0x40};
1332 >        if ((base = find_rom_data(0x310000, 0x314000, save_fpu_caller_dat, sizeof(save_fpu_caller_dat))) == 0) return false;
1333 >        D(bug("save_fpu_caller %08lx\n", base + 12));
1334 >        if (powerpc_branch_target(ROM_BASE + base + 12) != loc) return false;
1335 >        lp = (uint32 *)(ROM_BASE + base + 12);  // Always save FPU state
1336          *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312e88
1337  
1338 <        lp = (uint32 *)(ROM_BASE + 0x312b44);   // Don't read DEC
1339 <        while (ntohl(*lp) != 0x7ff602a6) lp++;
1340 <        *lp = htonl(0x3be00000);                                        // li   r31,0
1341 <
1342 <        lp = (uint32 *)(ROM_BASE + 0x312b50);   // Don't write DEC
1235 <        while (ntohl(*lp) != 0x7d1603a6) lp++;
1338 >        static const uint8 mdec_dat[] = {0x7f, 0xf6, 0x02, 0xa6, 0x2c, 0x08, 0x00, 0x00, 0x93, 0xe1, 0x06, 0x68, 0x7d, 0x16, 0x03, 0xa6};
1339 >        if ((base = find_rom_data(0x310000, 0x314000, mdec_dat, sizeof(mdec_dat))) == 0) return false;
1340 >        D(bug("mdec %08lx\n", base));
1341 >        lp = (uint32 *)(ROM_BASE + base);               // Don't modify DEC
1342 >        lp[0] = htonl(0x3be00000);                                      // li   r31,0
1343   #if 1
1344 <        *lp++ = htonl(POWERPC_NOP);
1345 <        *lp = htonl(POWERPC_NOP);
1344 >        lp[3] = htonl(POWERPC_NOP);
1345 >        lp[4] = htonl(POWERPC_NOP);
1346   #else
1347 <        *lp++ = htonl(0x39000040);                                      // li   r8,0x40
1348 <        *lp = htonl(0x990600e4);                                        // stb  r8,0xe4(r6)
1347 >        lp[3] = htonl(0x39000040);                                      // li   r8,0x40
1348 >        lp[4] = htonl(0x990600e4);                                      // stb  r8,0xe4(r6)
1349   #endif
1350  
1351 <        lp = (uint32 *)(ROM_BASE + 0x312b9c);   // Always restore FPU state
1352 <        while (ntohl(*lp) != 0x7c00092d) lp++;
1353 <        lp--;
1351 >        static const uint8 restore_fpu_caller_dat[] = {0x81, 0x06, 0x00, 0xf4, 0x81, 0x46, 0x00, 0xfc, 0x7d, 0x09, 0x03, 0xa6, 0x40};
1352 >        if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller_dat, sizeof(restore_fpu_caller_dat))) == 0) return false;
1353 >        D(bug("restore_fpu_caller %08lx\n", base + 12));
1354 >        lp = (uint32 *)(ROM_BASE + base + 12);  // Always restore FPU state
1355          *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312ddc
1356  
1357 <        lp = (uint32 *)(ROM_BASE + 0x312a68);   // Don't activate 68k exception table
1358 <        while (ntohl(*lp) != 0x39010360) lp++;
1357 >        static const uint8 m68k_excp_tbl_dat[] = {0x81, 0x21, 0x06, 0x58, 0x39, 0x01, 0x03, 0x60, 0x7d, 0x13, 0x43, 0xa6};
1358 >        if ((base = find_rom_data(0x310000, 0x314000, m68k_excp_tbl_dat, sizeof(m68k_excp_tbl_dat))) == 0) return false;
1359 >        D(bug("m68k_excp %08lx\n", base + 4));
1360 >        lp = (uint32 *)(ROM_BASE + base + 4);   // Don't activate 68k exception table
1361          *lp++ = htonl(0x39000000 + MODE_68K);           // li   r8,MODE_68K
1362          *lp = htonl(0x91000000 + XLM_RUN_MODE);         // stw  r8,XLM_RUN_MODE
1363  
1364          // Patch 68k emulator trap routine
1365 <        lp = (uint32 *)(ROM_BASE + 0x312994);   // Always restore FPU state
1366 <        while (ntohl(*lp) != 0x39260040) lp++;
1367 <        lp--;
1365 >        static const uint8 restore_fpu_caller2_dat[] = {0x81, 0x86, 0x00, 0x8c, 0x80, 0x66, 0x00, 0x94, 0x80, 0x86, 0x00, 0x9c, 0x40};
1366 >        if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller2_dat, sizeof(restore_fpu_caller2_dat))) == 0) return false;
1367 >        D(bug("restore_fpu_caller2 %08lx\n", base + 12));
1368 >        loc = powerpc_branch_target(ROM_BASE + base + 12) - ROM_BASE;
1369 >        lp = (uint32 *)(ROM_BASE + base + 12);  // Always restore FPU state
1370          *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312dd4
1371  
1372 <        lp = (uint32 *)(ROM_BASE + 0x312dd8);   // Don't modify MSR to turn on FPU
1373 <        while (ntohl(*lp) != 0x810600e4) lp++;
1374 <        lp--;
1372 >        static const uint8 restore_fpu_dat[] = {0x55, 0x68, 0x04, 0xa5, 0x4c, 0x82, 0x00, 0x20, 0x81, 0x06, 0x00, 0xe4};
1373 >        if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_dat, sizeof(restore_fpu_dat))) == 0) return false;
1374 >        D(bug("restore_fpu %08lx\n", base));
1375 >        if (base != loc) return false;
1376 >        lp = (uint32 *)(ROM_BASE + base + 4);   // Don't modify MSR to turn on FPU
1377          *lp++ = htonl(POWERPC_NOP);
1378          lp += 2;
1379          *lp++ = htonl(POWERPC_NOP);
# Line 1269 | Line 1383 | static bool patch_nanokernel(void)
1383          *lp = htonl(POWERPC_NOP);
1384  
1385          // Patch trap return routine
1386 <        lp = (uint32 *)(ROM_BASE + 0x312c20);
1387 <        while (ntohl(*lp) != 0x7d5a03a6) lp++;
1386 >        static const uint8 trap_return_dat[] = {0x80, 0xc1, 0x00, 0x18, 0x80, 0x21, 0x00, 0x04, 0x4c, 0x00, 0x00, 0x64};
1387 >        if ((base = find_rom_data(0x312000, 0x320000, trap_return_dat, sizeof(trap_return_dat))) == 0) return false;
1388 >        D(bug("trap_return %08lx\n", base + 8));
1389 >        lp = (uint32 *)(ROM_BASE + base + 8);   // Replace rfi
1390 >        *lp = htonl(POWERPC_BCTR);
1391 >
1392 >        while (ntohl(*lp) != 0x7d5a03a6) lp--;
1393          *lp++ = htonl(0x7d4903a6);                                      // mtctr        r10
1394          *lp++ = htonl(0x7daff120);                                      // mtcr r13
1395 <        *lp = htonl(0x48000000 + 0x8000 - (((uint32)lp - ROM_BASE) & 0xffff));  // b            ROM_BASE+0x318000
1396 <        uint32 xlp = ((uint32)(lp+1) - ROM_BASE) & 0xffff;
1278 <
1279 <        lp = (uint32 *)(ROM_BASE + 0x312c50);   // Replace rfi
1280 <        while (ntohl(*lp) != 0x4c000064) lp++;
1281 <        *lp = htonl(POWERPC_BCTR);
1395 >        *lp = htonl(0x48000000 + ((0x318000 - ((uint32)lp - ROM_BASE)) & 0x03fffffc));  // b            ROM_BASE+0x318000
1396 >        uint32 npc = (uint32)(lp + 1) - ROM_BASE;
1397  
1398          lp = (uint32 *)(ROM_BASE + 0x318000);
1284 #if EMULATED_PPC
1285        *lp++ = htonl(NativeOpcode(NATIVE_ENABLE_INTERRUPT));
1286        *lp = htonl(0x48000000 + ((xlp - 0x8004) & 0x03fffffc));        // b            ROM_BASE+0x312c2c
1287 #else
1399          *lp++ = htonl(0x81400000 + XLM_IRQ_NEST);       // lwz  r10,XLM_IRQ_NEST
1400          *lp++ = htonl(0x394affff);                                      // subi r10,r10,1
1401          *lp++ = htonl(0x91400000 + XLM_IRQ_NEST);       // stw  r10,XLM_IRQ_NEST
1402 <        *lp = htonl(0x48000000 + ((xlp - 0x800c) & 0x03fffffc));        // b            ROM_BASE+0x312c2c
1292 < #endif
1402 >        *lp = htonl(0x48000000 + ((npc - 0x31800c) & 0x03fffffc));      // b            ROM_BASE+0x312c2c
1403  
1404   /*
1405          // Disable FE0A/FE06 opcodes
# Line 1310 | Line 1420 | static bool patch_68k(void)
1420          uint32 *lp;
1421          uint16 *wp;
1422          uint8 *bp;
1423 <        uint32 base;
1423 >        uint32 base, loc;
1424  
1425          // Remove 68k RESET instruction
1426          static const uint8 reset_dat[] = {0x4e, 0x70};
# Line 1551 | Line 1661 | static bool patch_68k(void)
1661          *wp = htons(M68K_NOP);
1662  
1663          // Don't initialize SCC (via 0x1ac)
1664 <        static const uint8 scc_init_dat[] = {0x48, 0xe7, 0x38, 0xfe};
1665 <        if ((base = find_rom_data(0x190, 0x1f0, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1664 >        static const uint8 scc_init_caller_dat[] = {0x21, 0xce, 0x01, 0x08, 0x22, 0x78, 0x0d, 0xd8};
1665 >        if ((base = find_rom_data(0x180, 0x1f0, scc_init_caller_dat, sizeof(scc_init_caller_dat))) == 0) return false;
1666 >        D(bug("scc_init_caller %08lx\n", base + 12));
1667 >        wp = (uint16 *)(ROM_BASE + base + 12);
1668 >        loc = ntohs(wp[1]) + ((uintptr)wp - ROM_BASE) + 2;
1669 >        static const uint8 scc_init_dat[] = {0x20, 0x78, 0x01, 0xdc, 0x22, 0x78, 0x01, 0xd8};
1670 >        if ((base = find_rom_data(loc, loc + 0x80, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1671          D(bug("scc_init %08lx\n", base));
1672 <        wp = (uint16 *)(ROM_BASE + base - 2);
1558 <        wp = (uint16 *)(ROM_BASE + ntohs(*wp) + base - 2);
1672 >        wp = (uint16 *)(ROM_BASE + base);
1673          *wp++ = htons(M68K_EMUL_OP_RESET);
1674          *wp = htons(M68K_RTS);
1675  
# Line 1637 | Line 1751 | static bool patch_68k(void)
1751          *wp++ = htons(M68K_NOP);
1752          *wp = htons(M68K_NOP);
1753  
1754 <        // Gestalt PowerPC page size, RAM size (InitGestalt, via 0x25c)
1754 >        // Gestalt PowerPC page size, CPU type, RAM size (InitGestalt, via 0x25c)
1755          static const uint8 page_size2_dat[] = {0x26, 0x79, 0x5f, 0xff, 0xef, 0xd8, 0x25, 0x6b, 0x00, 0x10, 0x00, 0x1e};
1756          if ((base = find_rom_data(0x50000, 0x70000, page_size2_dat, sizeof(page_size2_dat))) == 0) return false;
1757          D(bug("page_size2 %08lx\n", base));
# Line 1647 | Line 1761 | static bool patch_68k(void)
1761          *wp++ = htons(0x1000);
1762          *wp++ = htons(0x001e);
1763          *wp++ = htons(0x157c);                  // move.b       #PVR,$1d(a2)
1764 <        *wp++ = htons(PVR >> 16);
1764 >        uint32 cput = (PVR >> 16);
1765 >        if (cput == 0x7000)
1766 >                cput |= 0x20;
1767 >        else if (cput >= 0x8000 && cput <= 0x8002)
1768 >                cput |= 0x10;
1769 >        cput &= 0xff;
1770 >        *wp++ = htons(cput);
1771          *wp++ = htons(0x001d);
1772          *wp++ = htons(0x263c);                  // move.l       #RAMSize,d3
1773          *wp++ = htons(RAMSize >> 16);
# Line 1700 | Line 1820 | static bool patch_68k(void)
1820                  if ((base = find_rom_data(0x13000, 0x20000, gc_mask2_dat, sizeof(gc_mask2_dat))) == 0) return false;
1821                  D(bug("gc_mask2 %08lx\n", base));
1822                  wp = (uint16 *)(ROM_BASE + base);
1823 <                if (ROMType == ROMTYPE_GOSSAMER)
1823 >                if (ROMType == ROMTYPE_GOSSAMER) {
1824 >                        *wp++ = htons(M68K_NOP);
1825                          *wp++ = htons(M68K_NOP);
1826 +                        *wp++ = htons(M68K_NOP);
1827 +                        *wp++ = htons(M68K_NOP);
1828 +                }
1829                  for (int i=0; i<5; i++) {
1830                          *wp++ = htons(M68K_NOP);
1831                          *wp++ = htons(M68K_NOP);
# Line 2117 | Line 2241 | static bool patch_68k(void)
2241          lp = (uint32 *)(ROM_BASE + ntohl(*lp));
2242          lp[0xa9fd & 0x3ff] = htonl(GET_SCRAP_PATCH_SPACE);
2243  
2120 #if __BEOS__
2244          // Patch SynchIdleTime()
2245          if (PrefsFindBool("idlewait")) {
2246                  wp = (uint16 *)(ROM_BASE + find_rom_trap(0xabf7) + 4);  // SynchIdleTime()
2247                  D(bug("SynchIdleTime at %08lx\n", wp));
2248 <                if (ntohs(*wp) == 0x2078) {
2248 >                if (ntohs(*wp) == 0x2078) {                                                             // movea.l      ExpandMem,a0
2249                          *wp++ = htons(M68K_EMUL_OP_IDLE_TIME);
2250                          *wp = htons(M68K_NOP);
2251 <                } else {
2251 >                }
2252 >                else if (ntohs(*wp) == 0x70fe)                                                  // moveq        #-2,d0
2253 >                        *wp++ = htons(M68K_EMUL_OP_IDLE_TIME_2);
2254 >                else {
2255                          D(bug("SynchIdleTime patch not installed\n"));
2256                  }
2257          }
2132 #endif
2258  
2259          // Construct list of all sifters used by sound components in ROM
2260          D(bug("Searching for sound components with type sdev in ROM\n"));
# Line 2194 | Line 2319 | void InstallDrivers(void)
2319                  WriteMacInt16(dce + dCtlFlags, SonyDriverFlags);
2320          }
2321  
2322 < #if DISABLE_SCSI && 0
2322 > #if DISABLE_SCSI && HAVE_SIGSEGV_SKIP_INSTRUCTION
2323          // Fake SCSIGlobals
2324          WriteMacInt32(0xc0c, SheepMem::ZeroPage());
2325   #endif

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