ViewVC Help

View File | Revision Log | Show Annotations | Revision Graph | Root Listing

root/cebix/SheepShaver/src/rom_patches.cpp

Comparing SheepShaver/src/rom_patches.cpp (file contents):
Revision 1.18 by gbeauche, 2003-12-04T17:26:35Z vs.
Revision 1.25 by gbeauche, 2004-01-31T11:10:48Z

#	Line 1 | Line 1
1		/*
2		*  rom_patches.cpp - ROM patches
3		*
4	<	*  SheepShaver (C) 1997-2002 Christian Bauer and Marc Hellwig
4	>	*  SheepShaver (C) 1997-2004 Christian Bauer and Marc Hellwig
5		*
6		*  This program is free software; you can redistribute it and/or modify
7		*  it under the terms of the GNU General Public License as published by
#	Line 62 | Line 62
62		const uint32 CHECK_LOAD_PATCH_SPACE = 0x2fcf00;
63		const uint32 PUT_SCRAP_PATCH_SPACE = 0x2fcf80;
64		const uint32 GET_SCRAP_PATCH_SPACE = 0x2fcfc0;
65	<	const uint32 ADDR_MAP_PATCH_SPACE = 0x2fd000;
65	>	const uint32 ADDR_MAP_PATCH_SPACE = 0x2fd100;
66
67		// Global variables
68		int ROMType;                            // ROM type
#	Line 270 | Line 270 | static uint32 find_rom_trap(uint16 trap)
270
271
272		/*
273	+	*  Return target of branch instruction specified at ADDR, or 0 if
274	+	*  there is no such instruction
275	+	*/
276	+
277	+	static uint32 powerpc_branch_target(uintptr addr)
278	+	{
279	+	uint32 opcode = ntohl(*(uint32 *)addr);
280	+	uint32 primop = opcode >> 26;
281	+	uint32 target = 0;
282	+
283	+	if (primop == 18) {                     // Branch
284	+	target = opcode & 0x3fffffc;
285	+	if (target & 0x2000000)
286	+	target |= 0xfc000000;
287	+	if ((opcode & 2) == 0)
288	+	target += addr;
289	+	}
290	+	else if (primop == 16) {        // Branch Conditional
291	+	target = (int32)(int16)(opcode & 0xfffc);
292	+	if ((opcode & 2) == 0)
293	+	target += addr;
294	+	}
295	+	return target;
296	+	}
297	+
298	+
299	+	/*
300	+	*  Search ROM for instruction branching to target address, return 0 if none found
301	+	*/
302	+
303	+	static uint32 find_rom_powerpc_branch(uint32 start, uint32 end, uint32 target)
304	+	{
305	+	for (uint32 addr = start; addr < end; addr += 4) {
306	+	if (powerpc_branch_target(ROM_BASE + addr) == ROM_BASE + target)
307	+	return addr;
308	+	}
309	+	return 0;
310	+	}
311	+
312	+
313	+	/*
314	+	*  Check that requested ROM patch space is really available
315	+	*/
316	+
317	+	static bool check_rom_patch_space(uint32 base, uint32 size)
318	+	{
319	+	size = (size + 3) & -4;
320	+	for (int i = 0; i < size; i += 4) {
321	+	uint32 x = ntohl(*(uint32 *)(ROM_BASE + base + i));
322	+	if (x != 0x6b636b63 && x != 0)
323	+	return false;
324	+	}
325	+	return true;
326	+	}
327	+
328	+
329	+	/*
330		*  List of audio sifters installed in ROM and System file
331		*/
332
#	Line 656 | Line 713 | bool PatchROM(void)
713		return false;
714
715		// Check that other ROM addresses point to really free regions
716	<	if (ntohl(*(uint32 *)(ROM_BASE + CHECK_LOAD_PATCH_SPACE)) != 0x6b636b63)
716	>	if (!check_rom_patch_space(CHECK_LOAD_PATCH_SPACE, 0x40))
717		return false;
718	<	if (ntohl(*(uint32 *)(ROM_BASE + PUT_SCRAP_PATCH_SPACE)) != 0x6b636b63)
718	>	if (!check_rom_patch_space(PUT_SCRAP_PATCH_SPACE, 0x40))
719		return false;
720	<	if (ntohl(*(uint32 *)(ROM_BASE + GET_SCRAP_PATCH_SPACE)) != 0x6b636b63)
720	>	if (!check_rom_patch_space(GET_SCRAP_PATCH_SPACE, 0x40))
721		return false;
722	<	if (ntohl(*(uint32 *)(ROM_BASE + ADDR_MAP_PATCH_SPACE)) != 0x6b636b63)
722	>	if (!check_rom_patch_space(ADDR_MAP_PATCH_SPACE - 10 * 4, 0x100))
723		return false;
724
725		// Apply patches
#	Line 697 | Line 754 | bool PatchROM(void)
754		static bool patch_nanokernel_boot(void)
755		{
756		uint32 *lp;
757	+	uint32 base, loc;
758
759		// ROM boot structure patches
760		lp = (uint32 *)(ROM_BASE + 0x30d000);
#	Line 709 | Line 767 | static bool patch_nanokernel_boot(void)
767		lp[0xfd8 >> 2] = htonl(ROM_BASE + 0x2a);                // 68k reset vector
768
769		// Skip SR/BAT/SDR init
770	+	loc = 0x310000;
771		if (ROMType == ROMTYPE_GAZELLE || ROMType == ROMTYPE_GOSSAMER || ROMType == ROMTYPE_NEWWORLD) {
772	<	lp = (uint32 *)(ROM_BASE + 0x310000);
772	>	lp = (uint32 *)(ROM_BASE + loc);
773		*lp++ = htonl(POWERPC_NOP);
774		*lp = htonl(0x38000000);
775		}
776	<	static const uint32 sr_init_loc[] = {0x3101b0, 0x3101b0, 0x3101b0, 0x3101ec, 0x3101fc, 0x310200};
777	<	lp = (uint32 *)(ROM_BASE + 0x310008);
778	<	*lp = htonl(0x48000000 | (sr_init_loc[ROMType] - 8) & 0xffff);  // b            ROM_BASE+0x3101b0
779	<	lp = (uint32 *)(ROM_BASE + sr_init_loc[ROMType]);
776	>	static const uint8 sr_init_dat[] = {0x35, 0x4a, 0xff, 0xfc, 0x7d, 0x86, 0x50, 0x2e};
777	>	if ((base = find_rom_data(0x3101b0, 0x3105b0, sr_init_dat, sizeof(sr_init_dat))) == 0) return false;
778	>	D(bug("sr_init %08lx\n", base));
779	>	lp = (uint32 *)(ROM_BASE + loc + 8);
780	>	*lp = htonl(0x48000000 | ((base - loc - 8) & 0x3fffffc));       // b            ROM_BASE+0x3101b0
781	>	lp = (uint32 *)(ROM_BASE + base);
782		*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);            // lwz  r1,(pointer to Kernel Data)
783		*lp++ = htonl(0x3da0dead);              // lis  r13,0xdead      (start of kernel memory)
784		*lp++ = htonl(0x3dc00010);              // lis  r14,0x0010      (size of page table)
785		*lp = htonl(0x3de00010);                // lis  r15,0x0010      (size of kernel memory)
786
787		// Don't read PVR
788	<	static const uint32 pvr_loc[] = {0x3103b0, 0x3103b4, 0x3103b4, 0x310400, 0x310430, 0x310438};
789	<	lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
788	>	static const uint8 pvr_read_dat[] = {0x7d, 0x9f, 0x42, 0xa6};
789	>	if ((base = find_rom_data(0x3103b0, 0x3108b0, pvr_read_dat, sizeof(pvr_read_dat))) == 0) return false;
790	>	D(bug("pvr_read %08lx\n", base));
791	>	lp = (uint32 *)(ROM_BASE + base);
792		*lp = htonl(0x81800000 + XLM_PVR);      // lwz  r12,(theoretical PVR)
793
794		// Set CPU specific data (even if ROM doesn't have support for that CPU)
732	–	lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
795		if (ntohl(lp[6]) != 0x2c0c0001)
796		return false;
797		uint32 ofs = ntohl(lp[7]) & 0xffff;
798		D(bug("ofs %08lx\n", ofs));
799		lp[8] = htonl((ntohl(lp[8]) & 0xffff) | 0x48000000);    // beq -> b
800	<	uint32 loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
800	>	loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
801		D(bug("loc %08lx\n", loc));
802		lp = (uint32 *)(ROM_BASE + ofs + 0x310000);
803		switch (PVR >> 16) {
#	Line 844 | Line 906 | static bool patch_nanokernel_boot(void)
906		lp[7] = htonl(0x00080008);      // Inst cache assoc/Data cache assoc
907		lp[8] = htonl(0x00800004);      // TLB total size/TLB assoc
908		break;
909	+	case 0x8000:    // 7400
910	+	case 0x800c:    // 7410
911	+	lp[0] = htonl(0x1000);          // Page size
912	+	lp[1] = htonl(0x8000);          // Data cache size
913	+	lp[2] = htonl(0x8000);          // Inst cache size
914	+	lp[3] = htonl(0x00200020);      // Coherency block size/Reservation granule size
915	+	lp[4] = htonl(0x00000020);      // Unified caches/Inst cache line size
916	+	lp[5] = htonl(0x00200020);      // Data cache line size/Data cache block size touch
917	+	lp[6] = htonl(0x00200020);      // Inst cache block size/Data cache block size
918	+	lp[7] = htonl(0x00080008);      // Inst cache assoc/Data cache assoc
919	+	lp[8] = htonl(0x00800002);      // TLB total size/TLB assoc
920	+	break;
921		default:
922		printf("WARNING: Unknown CPU type\n");
923		break;
924		}
925
926		// Don't set SPRG3, don't test MQ
927	<	lp = (uint32 *)(ROM_BASE + loc + 0x20);
928	<	*lp++ = htonl(POWERPC_NOP);
929	<	lp++;
930	<	*lp++ = htonl(POWERPC_NOP);
931	<	lp++;
932	<	*lp = htonl(POWERPC_NOP);
927	>	static const uint8 sprg3_mq_dat[] = {0x7d, 0x13, 0x43, 0xa6, 0x3d, 0x00, 0x00, 0x04, 0x7d, 0x00, 0x03, 0xa6, 0x39, 0x00, 0x00, 0x00, 0x7d, 0x00, 0x02, 0xa6};
928	>	if ((base = find_rom_data(loc + 0x20, loc + 0x60, sprg3_mq_dat, sizeof(sprg3_mq_dat))) == 0) return false;
929	>	D(bug("sprg3/mq %08lx\n", base));
930	>	lp = (uint32 *)(ROM_BASE + base);
931	>	lp[0] = htonl(POWERPC_NOP);
932	>	lp[2] = htonl(POWERPC_NOP);
933	>	lp[4] = htonl(POWERPC_NOP);
934
935		// Don't read MSR
936	<	lp = (uint32 *)(ROM_BASE + loc + 0x40);
936	>	static const uint8 msr_dat[] = {0x7d, 0xc0, 0x00, 0xa6};
937	>	if ((base = find_rom_data(loc + 0x40, loc + 0x80, msr_dat, sizeof(msr_dat))) == 0) return false;
938	>	D(bug("msr %08lx\n", base));
939	>	lp = (uint32 *)(ROM_BASE + base);
940		*lp = htonl(0x39c00000);                // li   r14,0
941
942		// Don't write to DEC
#	Line 868 | Line 946 | static bool patch_nanokernel_boot(void)
946		D(bug("loc %08lx\n", loc));
947
948		// Don't set SPRG3
949	<	lp = (uint32 *)(ROM_BASE + loc + 0x2c);
949	>	static const uint8 sprg3_dat[] = {0x39, 0x21, 0x03, 0x60, 0x7d, 0x33, 0x43, 0xa6, 0x39, 0x01, 0x04, 0x20};
950	>	if ((base = find_rom_data(0x310000, 0x314000, sprg3_dat, sizeof(sprg3_dat))) == 0) return false;
951	>	D(bug("sprg3 %08lx\n", base + 4));
952	>	lp = (uint32 *)(ROM_BASE + base + 4);
953		*lp = htonl(POWERPC_NOP);
954
955		// Don't read PVR
956	<	static const uint32 pvr_ofs[] = {0x138, 0x138, 0x138, 0x140, 0x148, 0x148};
957	<	lp = (uint32 *)(ROM_BASE + loc + pvr_ofs[ROMType]);
956	>	static const uint8 pvr_read2_dat[] = {0x7e, 0xff, 0x42, 0xa6, 0x56, 0xf7, 0x84, 0x3e};
957	>	if ((base = find_rom_data(0x310000, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) == 0) return false;
958	>	D(bug("pvr_read2 %08lx\n", base));
959	>	lp = (uint32 *)(ROM_BASE + base);
960		*lp = htonl(0x82e00000 + XLM_PVR);              // lwz  r23,(theoretical PVR)
961	<	lp = (uint32 *)(ROM_BASE + loc + 0x170);
962	<	if (ntohl(*lp) == 0x7eff42a6)   // NewWorld or Gossamer ROM
961	>	if ((base = find_rom_data(base + 4, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) != 0) {
962	>	D(bug("pvr_read2 %08lx\n", base));
963	>	lp = (uint32 *)(ROM_BASE + base);
964		*lp = htonl(0x82e00000 + XLM_PVR);      // lwz  r23,(theoretical PVR)
965	<	lp = (uint32 *)(ROM_BASE + 0x313134);
966	<	if (ntohl(*lp) == 0x7e5f42a6)
967	<	*lp = htonl(0x82400000 + XLM_PVR);      // lwz  r18,(theoretical PVR)
968	<	lp = (uint32 *)(ROM_BASE + 0x3131f4);
969	<	if (ntohl(*lp) == 0x7e5f42a6)   // NewWorld ROM
965	>	}
966	>	static const uint8 pvr_read3_dat[] = {0x7e, 0x5f, 0x42, 0xa6, 0x56, 0x52, 0x84, 0x3e};
967	>	if ((base = find_rom_data(0x310000, 0x320000, pvr_read3_dat, sizeof(pvr_read3_dat))) != 0) {
968	>	D(bug("pvr_read3 %08lx\n", base));
969	>	lp = (uint32 *)(ROM_BASE + base);
970		*lp = htonl(0x82400000 + XLM_PVR);      // lwz  r18,(theoretical PVR)
971	<	lp = (uint32 *)(ROM_BASE + 0x314600);
972	<	if (ntohl(*lp) == 0x7d3f42a6)
971	>	}
972	>	static const uint8 pvr_read4_dat[] = {0x7d, 0x3f, 0x42, 0xa6, 0x55, 0x29, 0x84, 0x3e};
973	>	if ((base = find_rom_data(0x310000, 0x320000, pvr_read4_dat, sizeof(pvr_read4_dat))) != 0) {
974	>	D(bug("pvr_read4 %08lx\n", base));
975	>	lp = (uint32 *)(ROM_BASE + base);
976		*lp = htonl(0x81200000 + XLM_PVR);      // lzw  r9,(theoritical PVR)
977	+	}
978
979		// Don't read SDR1
980	<	static const uint32 sdr1_ofs[] = {0x174, 0x174, 0x174, 0x17c, 0x19c, 0x19c};
981	<	lp = (uint32 *)(ROM_BASE + loc + sdr1_ofs[ROMType]);
980	>	static const uint8 sdr1_read_dat[] = {0x7d, 0x19, 0x02, 0xa6, 0x55, 0x16, 0x81, 0xde};
981	>	if ((base = find_rom_data(0x310000, 0x320000, sdr1_read_dat, sizeof(sdr1_read_dat))) == 0) return false;
982	>	D(bug("sdr1_read %08lx\n", base));
983	>	lp = (uint32 *)(ROM_BASE + base);
984		*lp++ = htonl(0x3d00dead);              // lis  r8,0xdead               (pointer to page table)
985		*lp++ = htonl(0x3ec0001f);              // lis  r22,0x001f      (size of page table)
986		*lp = htonl(POWERPC_NOP);
987
988	<	// Don't clear page table
989	<	static const uint32 pgtb_ofs[] = {0x198, 0x198, 0x198, 0x1a0, 0x1c0, 0x1c4};
990	<	lp = (uint32 *)(ROM_BASE + loc + pgtb_ofs[ROMType]);
988	>	// Don't clear page table, don't invalidate TLB
989	>	static const uint8 pgtb_clear_dat[] = {0x36, 0xd6, 0xff, 0xfc, 0x7e, 0xe8, 0xb1, 0x2e, 0x41, 0x81, 0xff, 0xf8};
990	>	if ((base = find_rom_data(0x310000, 0x320000, pgtb_clear_dat, sizeof(pgtb_clear_dat))) == 0) return false;
991	>	D(bug("pgtb_clear %08lx\n", base + 4));
992	>	lp = (uint32 *)(ROM_BASE + base + 4);
993		*lp = htonl(POWERPC_NOP);
994	<
995	<	// Don't invalidate TLB
904	<	static const uint32 tlb_ofs[] = {0x1a0, 0x1a0, 0x1a0, 0x1a8, 0x1c8, 0x1cc};
905	<	lp = (uint32 *)(ROM_BASE + loc + tlb_ofs[ROMType]);
994	>	D(bug("tblie %08lx\n", base + 12));
995	>	lp = (uint32 *)(ROM_BASE + base + 12);
996		*lp = htonl(POWERPC_NOP);
997
998		// Don't create RAM descriptor table
999	<	static const uint32 desc_ofs[] = {0x350, 0x350, 0x350, 0x358, 0x378, 0x37c};
1000	<	lp = (uint32 *)(ROM_BASE + loc + desc_ofs[ROMType]);
999	>	static const uint8 desc_create_dat[] = {0x97, 0xfd, 0x00, 0x04, 0x3b, 0xff, 0x10, 0x00, 0x4b, 0xff, 0xff, 0xdc};
1000	>	if ((base = find_rom_data(0x310000, 0x320000, desc_create_dat, sizeof(desc_create_dat))) == 0) return false;
1001	>	D(bug("desc_create %08lx\n", base))
1002	>	lp = (uint32 *)(ROM_BASE + base);
1003		*lp = htonl(POWERPC_NOP);
1004
1005		// Don't load SRs and BATs
1006	<	static const uint32 sr_ofs[] = {0x3d8, 0x3d8, 0x3d8, 0x3e0, 0x400, 0x404};
1007	<	lp = (uint32 *)(ROM_BASE + loc + sr_ofs[ROMType]);
1006	>	static const uint8 sr_load[] = {0x7c, 0x00, 0x04, 0xac, 0x83, 0x9d, 0x00, 0x00, 0x93, 0x81, 0x05, 0xe8};
1007	>	if ((loc = find_rom_data(0x310000, 0x320000, sr_load, sizeof(sr_load))) == 0) return false;
1008	>	static const uint8 sr_load_caller[] = {0x3e, 0xd6, 0xff, 0xff, 0x41, 0x81, 0xff, 0xdc, 0xb2, 0xc8, 0x00, 0x02};
1009	>	if ((base = find_rom_data(0x310000, 0x320000, sr_load_caller, sizeof(sr_load_caller))) == 0) return false;
1010	>	if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false;
1011	>	D(bug("sr_load %08lx, called from %08lx\n", loc, base));
1012	>	lp = (uint32 *)(ROM_BASE + base);
1013		*lp = htonl(POWERPC_NOP);
1014
1015		// Don't mess with SRs
1016	<	static const uint32 sr2_ofs[] = {0x312118, 0x312118, 0x312118, 0x312118, 0x312118, 0x3121b4};
1017	<	lp = (uint32 *)(ROM_BASE + sr2_ofs[ROMType]);
1016	>	static const uint8 sr_load2_dat[] = {0x83, 0xa1, 0x05, 0xe8, 0x57, 0x7c, 0x3e, 0x78, 0x7f, 0xbd, 0xe0, 0x2e};
1017	>	if ((base = find_rom_data(0x310000, 0x320000, sr_load2_dat, sizeof(sr_load2_dat))) == 0) return false;
1018	>	D(bug("sr_load2 %08lx\n", base));
1019	>	lp = (uint32 *)(ROM_BASE + base);
1020		*lp = htonl(POWERPC_BLR);
1021
1022		// Don't check performance monitor
1023	<	static const uint32 pm_ofs[] = {0x313148, 0x313148, 0x313148, 0x313148, 0x313158, 0x313218};
1024	<	lp = (uint32 *)(ROM_BASE + pm_ofs[ROMType]);
1025	<	while (ntohl(*lp) != 0x7e58eba6) lp++;
1026	<	*lp++ = htonl(POWERPC_NOP);
1027	<	while (ntohl(*lp) != 0x7e78eaa6) lp++;
1028	<	*lp++ = htonl(POWERPC_NOP);
1029	<	while (ntohl(*lp) != 0x7e59eba6) lp++;
1030	<	*lp++ = htonl(POWERPC_NOP);
1031	<	while (ntohl(*lp) != 0x7e79eaa6) lp++;
1032	<	*lp++ = htonl(POWERPC_NOP);
1033	<	while (ntohl(*lp) != 0x7e5aeba6) lp++;
1034	<	*lp++ = htonl(POWERPC_NOP);
1035	<	while (ntohl(*lp) != 0x7e7aeaa6) lp++;
1036	<	*lp++ = htonl(POWERPC_NOP);
1037	<	while (ntohl(*lp) != 0x7e5beba6) lp++;
1038	<	*lp++ = htonl(POWERPC_NOP);
1039	<	while (ntohl(*lp) != 0x7e7beaa6) lp++;
1040	<	*lp++ = htonl(POWERPC_NOP);
1041	<	while (ntohl(*lp) != 0x7e5feba6) lp++;
1042	<	*lp++ = htonl(POWERPC_NOP);
1043	<	while (ntohl(*lp) != 0x7e7feaa6) lp++;
1044	<	*lp++ = htonl(POWERPC_NOP);
1045	<	while (ntohl(*lp) != 0x7e5ceba6) lp++;
1046	<	*lp++ = htonl(POWERPC_NOP);
948	<	while (ntohl(*lp) != 0x7e7ceaa6) lp++;
949	<	*lp++ = htonl(POWERPC_NOP);
950	<	while (ntohl(*lp) != 0x7e5deba6) lp++;
951	<	*lp++ = htonl(POWERPC_NOP);
952	<	while (ntohl(*lp) != 0x7e7deaa6) lp++;
953	<	*lp++ = htonl(POWERPC_NOP);
954	<	while (ntohl(*lp) != 0x7e5eeba6) lp++;
955	<	*lp++ = htonl(POWERPC_NOP);
956	<	while (ntohl(*lp) != 0x7e7eeaa6) lp++;
957	<	*lp++ = htonl(POWERPC_NOP);
1023	>	static const uint8 pm_check_dat[] = {0x7e, 0x58, 0xeb, 0xa6, 0x7e, 0x53, 0x90, 0xf8, 0x7e, 0x78, 0xea, 0xa6};
1024	>	if ((base = find_rom_data(0x310000, 0x320000, pm_check_dat, sizeof(pm_check_dat))) == 0) return false;
1025	>	D(bug("pm_check %08lx\n", base));
1026	>	lp = (uint32 *)(ROM_BASE + base);
1027	>
1028	>	static const int spr_check_list[] = {
1029	>	952 /* mmcr0 */, 953 /* pmc1 */, 954 /* pmc2 */, 955 /* sia */,
1030	>	956 /* mmcr1 */, 957 /* pmc3 */, 958 /* pmc4 */, 959 /* sda */
1031	>	};
1032	>
1033	>	for (int i = 0; i < sizeof(spr_check_list)/sizeof(spr_check_list[0]); i++) {
1034	>	int spr = spr_check_list[i];
1035	>	uint32 mtspr = 0x7e4003a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6);
1036	>	uint32 mfspr = 0x7e6002a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6);
1037	>	for (int ofs = 0; ofs < 64; ofs++) {
1038	>	if (ntohl(lp[ofs]) == mtspr) {
1039	>	if (ntohl(lp[ofs + 2]) != mfspr)
1040	>	return false;
1041	>	D(bug("  SPR%d %08lx\n", spr, base + 4*ofs));
1042	>	lp[ofs] = htonl(POWERPC_NOP);
1043	>	lp[ofs + 2] = htonl(POWERPC_NOP);
1044	>	}
1045	>	}
1046	>	}
1047
1048		// Jump to 68k emulator
1049	<	static const uint32 jump68k_ofs[] = {0x40c, 0x40c, 0x40c, 0x414, 0x434, 0x438};
1050	<	lp = (uint32 *)(ROM_BASE + loc + jump68k_ofs[ROMType]);
1049	>	static const uint8 jump68k_dat[] = {0x7d, 0x92, 0x43, 0xa6, 0x7d, 0x5a, 0x03, 0xa6, 0x7d, 0x7b, 0x03, 0xa6};
1050	>	if ((loc = find_rom_data(0x310000, 0x320000, jump68k_dat, sizeof(jump68k_dat))) == 0) return false;
1051	>	static const uint8 jump68k_caller_dat[] = {0x85, 0x13, 0x00, 0x08, 0x56, 0xbf, 0x50, 0x3e, 0x63, 0xff, 0x0c, 0x00};
1052	>	if ((base = find_rom_data(0x310000, 0x320000, jump68k_caller_dat, sizeof(jump68k_caller_dat))) == 0) return false;
1053	>	if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false;
1054	>	D(bug("jump68k %08lx, called from %08lx\n", loc, base));
1055	>	lp = (uint32 *)(ROM_BASE + base);
1056		*lp++ = htonl(0x80610634);              // lwz  r3,0x0634(r1)   (pointer to Emulator Data)
1057		*lp++ = htonl(0x8081119c);              // lwz  r4,0x119c(r1)   (pointer to opcode table)
1058		*lp++ = htonl(0x80011184);              // lwz  r0,0x1184(r1)   (pointer to emulator init routine)
#	Line 978 | Line 1072 | static bool patch_68k_emul(void)
1072		uint32 base;
1073
1074		// Overwrite twi instructions
1075	<	static const uint32 twi_loc[] = {0x36e680, 0x36e6c0, 0x36e6c0, 0x36e6c0, 0x36e740, 0x36e740};
1076	<	base = twi_loc[ROMType];
1075	>	static const uint8 twi_dat[] = {0x0f, 0xff, 0x00, 0x00, 0x0f, 0xff, 0x00, 0x01, 0x0f, 0xff, 0x00, 0x02};
1076	>	if ((base = find_rom_data(0x36e600, 0x36ea00, twi_dat, sizeof(twi_dat))) == 0) return false;
1077	>	D(bug("twi %08lx\n", base));
1078		lp = (uint32 *)(ROM_BASE + base);
1079		*lp++ = htonl(0x48000000 + 0x36f900 - base);            // b 0x36f900 (Emulator start)
1080		*lp++ = htonl(0x48000000 + 0x36fa00 - base - 4);        // b 0x36fa00 (Mixed mode)
#	Line 1199 | Line 1294 | dr_found:
1294		static bool patch_nanokernel(void)
1295		{
1296		uint32 *lp;
1297	+	uint32 base, loc;
1298
1299		// Patch Mixed Mode trap
1300	<	lp = (uint32 *)(ROM_BASE + 0x313c90);   // Don't translate virtual->physical
1301	<	while (ntohl(*lp) != 0x3ba10320) lp++;
1302	<	lp++;
1303	<	*lp++ = htonl(0x7f7fdb78);                                      // mr           r31,r27
1304	<	lp++;
1305	<	*lp = htonl(POWERPC_NOP);
1306	<
1307	<	lp = (uint32 *)(ROM_BASE + 0x313c3c);   // Don't activate PPC exception table
1308	<	while (ntohl(*lp) != 0x39010420) lp++;
1300	>	static const uint8 virt2phys_dat[] = {0x7d, 0x1b, 0x43, 0x78, 0x3b, 0xa1, 0x03, 0x20};
1301	>	if ((base = find_rom_data(0x313000, 0x314000, virt2phys_dat, sizeof(virt2phys_dat))) == 0) return false;
1302	>	D(bug("virt2phys %08lx\n", base + 8));
1303	>	lp = (uint32 *)(ROM_BASE + base + 8);   // Don't translate virtual->physical
1304	>	lp[0] = htonl(0x7f7fdb78);                                      // mr           r31,r27
1305	>	lp[2] = htonl(POWERPC_NOP);
1306	>
1307	>	static const uint8 ppc_excp_tbl_dat[] = {0x39, 0x01, 0x04, 0x20, 0x7d, 0x13, 0x43, 0xa6};
1308	>	if ((base = find_rom_data(0x313000, 0x314000, ppc_excp_tbl_dat, sizeof(ppc_excp_tbl_dat))) == 0) return false;
1309	>	D(bug("ppc_excp_tbl %08lx\n", base));
1310	>	lp = (uint32 *)(ROM_BASE + base);               // Don't activate PPC exception table
1311		*lp++ = htonl(0x39000000 + MODE_NATIVE);        // li   r8,MODE_NATIVE
1312	<	*lp = htonl(0x91000000 + XLM_RUN_MODE); // stw  r8,XLM_RUN_MODE
1312	>	*lp = htonl(0x91000000 + XLM_RUN_MODE);         // stw  r8,XLM_RUN_MODE
1313
1314	<	lp = (uint32 *)(ROM_BASE + 0x312e88);   // Don't modify MSR to turn on FPU
1315	<	while (ntohl(*lp) != 0x556b04e2) lp++;
1316	<	lp -= 4;
1314	>	static const uint8 save_fpu_dat[] = {0x7d, 0x00, 0x00, 0xa6, 0x61, 0x08, 0x20, 0x00, 0x7d, 0x00, 0x01, 0x24};
1315	>	if ((base = find_rom_data(0x310000, 0x314000, save_fpu_dat, sizeof(save_fpu_dat))) == 0) return false;
1316	>	D(bug("save_fpu %08lx\n", base));
1317	>	lp = (uint32 *)(ROM_BASE + base);               // Don't modify MSR to turn on FPU
1318	>	if (ntohl(lp[4]) != 0x556b04e2) return false;
1319	>	loc = ROM_BASE + base;
1320	>	#if 1
1321	>	// FIXME: is that really intended?
1322		*lp++ = htonl(POWERPC_NOP);
1323		lp++;
1324		*lp++ = htonl(POWERPC_NOP);
1325		lp++;
1326		*lp = htonl(POWERPC_NOP);
1327	+	#else
1328	+	lp[0] = htonl(POWERPC_NOP);
1329	+	lp[1] = htonl(POWERPC_NOP);
1330	+	lp[2] = htonl(POWERPC_NOP);
1331	+	lp[3] = htonl(POWERPC_NOP);
1332	+	#endif
1333
1334	<	lp = (uint32 *)(ROM_BASE + 0x312b3c);   // Always save FPU state
1335	<	while (ntohl(*lp) != 0x81010668) lp++;
1336	<	lp--;
1334	>	static const uint8 save_fpu_caller_dat[] = {0x93, 0xa6, 0x01, 0xec, 0x93, 0xc6, 0x01, 0xf4, 0x93, 0xe6, 0x01, 0xfc, 0x40};
1335	>	if ((base = find_rom_data(0x310000, 0x314000, save_fpu_caller_dat, sizeof(save_fpu_caller_dat))) == 0) return false;
1336	>	D(bug("save_fpu_caller %08lx\n", base + 12));
1337	>	if (powerpc_branch_target(ROM_BASE + base + 12) != loc) return false;
1338	>	lp = (uint32 *)(ROM_BASE + base + 12);  // Always save FPU state
1339		*lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312e88
1340
1341	<	lp = (uint32 *)(ROM_BASE + 0x312b44);   // Don't read DEC
1342	<	while (ntohl(*lp) != 0x7ff602a6) lp++;
1343	<	*lp = htonl(0x3be00000);                                        // li   r31,0
1344	<
1345	<	lp = (uint32 *)(ROM_BASE + 0x312b50);   // Don't write DEC
1235	<	while (ntohl(*lp) != 0x7d1603a6) lp++;
1341	>	static const uint8 mdec_dat[] = {0x7f, 0xf6, 0x02, 0xa6, 0x2c, 0x08, 0x00, 0x00, 0x93, 0xe1, 0x06, 0x68, 0x7d, 0x16, 0x03, 0xa6};
1342	>	if ((base = find_rom_data(0x310000, 0x314000, mdec_dat, sizeof(mdec_dat))) == 0) return false;
1343	>	D(bug("mdec %08lx\n", base));
1344	>	lp = (uint32 *)(ROM_BASE + base);               // Don't modify DEC
1345	>	lp[0] = htonl(0x3be00000);                                      // li   r31,0
1346		#if 1
1347	<	*lp++ = htonl(POWERPC_NOP);
1348	<	*lp = htonl(POWERPC_NOP);
1347	>	lp[3] = htonl(POWERPC_NOP);
1348	>	lp[4] = htonl(POWERPC_NOP);
1349		#else
1350	<	*lp++ = htonl(0x39000040);                                      // li   r8,0x40
1351	<	*lp = htonl(0x990600e4);                                        // stb  r8,0xe4(r6)
1350	>	lp[3] = htonl(0x39000040);                                      // li   r8,0x40
1351	>	lp[4] = htonl(0x990600e4);                                      // stb  r8,0xe4(r6)
1352		#endif
1353
1354	<	lp = (uint32 *)(ROM_BASE + 0x312b9c);   // Always restore FPU state
1355	<	while (ntohl(*lp) != 0x7c00092d) lp++;
1356	<	lp--;
1354	>	static const uint8 restore_fpu_caller_dat[] = {0x81, 0x06, 0x00, 0xf4, 0x81, 0x46, 0x00, 0xfc, 0x7d, 0x09, 0x03, 0xa6, 0x40};
1355	>	if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller_dat, sizeof(restore_fpu_caller_dat))) == 0) return false;
1356	>	D(bug("restore_fpu_caller %08lx\n", base + 12));
1357	>	lp = (uint32 *)(ROM_BASE + base + 12);  // Always restore FPU state
1358		*lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312ddc
1359
1360	<	lp = (uint32 *)(ROM_BASE + 0x312a68);   // Don't activate 68k exception table
1361	<	while (ntohl(*lp) != 0x39010360) lp++;
1360	>	static const uint8 m68k_excp_tbl_dat[] = {0x81, 0x21, 0x06, 0x58, 0x39, 0x01, 0x03, 0x60, 0x7d, 0x13, 0x43, 0xa6};
1361	>	if ((base = find_rom_data(0x310000, 0x314000, m68k_excp_tbl_dat, sizeof(m68k_excp_tbl_dat))) == 0) return false;
1362	>	D(bug("m68k_excp %08lx\n", base + 4));
1363	>	lp = (uint32 *)(ROM_BASE + base + 4);   // Don't activate 68k exception table
1364		*lp++ = htonl(0x39000000 + MODE_68K);           // li   r8,MODE_68K
1365		*lp = htonl(0x91000000 + XLM_RUN_MODE);         // stw  r8,XLM_RUN_MODE
1366
1367		// Patch 68k emulator trap routine
1368	<	lp = (uint32 *)(ROM_BASE + 0x312994);   // Always restore FPU state
1369	<	while (ntohl(*lp) != 0x39260040) lp++;
1370	<	lp--;
1368	>	static const uint8 restore_fpu_caller2_dat[] = {0x81, 0x86, 0x00, 0x8c, 0x80, 0x66, 0x00, 0x94, 0x80, 0x86, 0x00, 0x9c, 0x40};
1369	>	if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller2_dat, sizeof(restore_fpu_caller2_dat))) == 0) return false;
1370	>	D(bug("restore_fpu_caller2 %08lx\n", base + 12));
1371	>	loc = powerpc_branch_target(ROM_BASE + base + 12) - ROM_BASE;
1372	>	lp = (uint32 *)(ROM_BASE + base + 12);  // Always restore FPU state
1373		*lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312dd4
1374
1375	<	lp = (uint32 *)(ROM_BASE + 0x312dd8);   // Don't modify MSR to turn on FPU
1376	<	while (ntohl(*lp) != 0x810600e4) lp++;
1377	<	lp--;
1375	>	static const uint8 restore_fpu_dat[] = {0x55, 0x68, 0x04, 0xa5, 0x4c, 0x82, 0x00, 0x20, 0x81, 0x06, 0x00, 0xe4};
1376	>	if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_dat, sizeof(restore_fpu_dat))) == 0) return false;
1377	>	D(bug("restore_fpu %08lx\n", base));
1378	>	if (base != loc) return false;
1379	>	lp = (uint32 *)(ROM_BASE + base + 4);   // Don't modify MSR to turn on FPU
1380		*lp++ = htonl(POWERPC_NOP);
1381		lp += 2;
1382		*lp++ = htonl(POWERPC_NOP);
#	Line 1269 | Line 1386 | static bool patch_nanokernel(void)
1386		*lp = htonl(POWERPC_NOP);
1387
1388		// Patch trap return routine
1389	<	lp = (uint32 *)(ROM_BASE + 0x312c20);
1390	<	while (ntohl(*lp) != 0x7d5a03a6) lp++;
1389	>	static const uint8 trap_return_dat[] = {0x80, 0xc1, 0x00, 0x18, 0x80, 0x21, 0x00, 0x04, 0x4c, 0x00, 0x00, 0x64};
1390	>	if ((base = find_rom_data(0x312000, 0x320000, trap_return_dat, sizeof(trap_return_dat))) == 0) return false;
1391	>	D(bug("trap_return %08lx\n", base + 8));
1392	>	lp = (uint32 *)(ROM_BASE + base + 8);   // Replace rfi
1393	>	*lp = htonl(POWERPC_BCTR);
1394	>
1395	>	while (ntohl(*lp) != 0x7d5a03a6) lp--;
1396		*lp++ = htonl(0x7d4903a6);                                      // mtctr        r10
1397		*lp++ = htonl(0x7daff120);                                      // mtcr r13
1398	<	*lp = htonl(0x48000000 + 0x8000 - (((uint32)lp - ROM_BASE) & 0xffff));  // b            ROM_BASE+0x318000
1399	<	uint32 xlp = ((uint32)(lp+1) - ROM_BASE) & 0xffff;
1278	<
1279	<	lp = (uint32 *)(ROM_BASE + 0x312c50);   // Replace rfi
1280	<	while (ntohl(*lp) != 0x4c000064) lp++;
1281	<	*lp = htonl(POWERPC_BCTR);
1398	>	*lp = htonl(0x48000000 + ((0x318000 - ((uint32)lp - ROM_BASE)) & 0x03fffffc));  // b            ROM_BASE+0x318000
1399	>	uint32 npc = (uint32)(lp + 1) - ROM_BASE;
1400
1401		lp = (uint32 *)(ROM_BASE + 0x318000);
1402		#if EMULATED_PPC
1403		*lp++ = htonl(NativeOpcode(NATIVE_ENABLE_INTERRUPT));
1404	<	*lp = htonl(0x48000000 + ((xlp - 0x8004) & 0x03fffffc));        // b            ROM_BASE+0x312c2c
1404	>	*lp = htonl(0x48000000 + ((npc - 0x318004) & 0x03fffffc));      // b            ROM_BASE+0x312c2c
1405		#else
1406		*lp++ = htonl(0x81400000 + XLM_IRQ_NEST);       // lwz  r10,XLM_IRQ_NEST
1407		*lp++ = htonl(0x394affff);                                      // subi r10,r10,1
1408		*lp++ = htonl(0x91400000 + XLM_IRQ_NEST);       // stw  r10,XLM_IRQ_NEST
1409	<	*lp = htonl(0x48000000 + ((xlp - 0x800c) & 0x03fffffc));        // b            ROM_BASE+0x312c2c
1409	>	*lp = htonl(0x48000000 + ((npc - 0x31800c) & 0x03fffffc));      // b            ROM_BASE+0x312c2c
1410		#endif
1411
1412		/*
#	Line 1310 | Line 1428 | static bool patch_68k(void)
1428		uint32 *lp;
1429		uint16 *wp;
1430		uint8 *bp;
1431	<	uint32 base;
1431	>	uint32 base, loc;
1432
1433		// Remove 68k RESET instruction
1434		static const uint8 reset_dat[] = {0x4e, 0x70};
#	Line 1551 | Line 1669 | static bool patch_68k(void)
1669		*wp = htons(M68K_NOP);
1670
1671		// Don't initialize SCC (via 0x1ac)
1672	<	static const uint8 scc_init_dat[] = {0x48, 0xe7, 0x38, 0xfe};
1673	<	if ((base = find_rom_data(0x190, 0x1f0, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1672	>	static const uint8 scc_init_caller_dat[] = {0x21, 0xce, 0x01, 0x08, 0x22, 0x78, 0x0d, 0xd8};
1673	>	if ((base = find_rom_data(0x180, 0x1f0, scc_init_caller_dat, sizeof(scc_init_caller_dat))) == 0) return false;
1674	>	D(bug("scc_init_caller %08lx\n", base + 12));
1675	>	wp = (uint16 *)(ROM_BASE + base + 12);
1676	>	loc = ntohs(wp[1]) + ((uintptr)wp - ROM_BASE) + 2;
1677	>	static const uint8 scc_init_dat[] = {0x20, 0x78, 0x01, 0xdc, 0x22, 0x78, 0x01, 0xd8};
1678	>	if ((base = find_rom_data(loc, loc + 0x80, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1679		D(bug("scc_init %08lx\n", base));
1680	<	wp = (uint16 *)(ROM_BASE + base - 2);
1558	<	wp = (uint16 *)(ROM_BASE + ntohs(*wp) + base - 2);
1680	>	wp = (uint16 *)(ROM_BASE + base);
1681		*wp++ = htons(M68K_EMUL_OP_RESET);
1682		*wp = htons(M68K_RTS);
1683
#	Line 1839 | Line 1961 | static bool patch_68k(void)
1961		*lp = htonl(0x38600000);                // li   r3,0
1962		}
1963
1964	+	// FIXME: Fake reading from [HpChk]+4 (the callchain reports some function from DriverServicesLib)
1965	+	if (1) {
1966	+	uint32 hpchk_offset = find_rom_resource(FOURCC('n','l','i','b'), 10);
1967	+	static const uint8 hpchk_dat[] = {0x80, 0x80, 0x03, 0x16, 0x94, 0x21, 0xff, 0xb0, 0x83, 0xc4, 0x00, 0x04};
1968	+	if ((base = find_rom_data(hpchk_offset, hpchk_offset + 0x3000, hpchk_dat, sizeof(hpchk_dat))) == 0) return false;
1969	+	D(bug("hpchk %08lx\n", base));
1970	+	lp = (uint32 *)(ROM_BASE + base);
1971	+	*lp = htonl(0x80800000 + XLM_ZERO_PAGE);                // lwz  r4,(zero page)
1972	+	}
1973	+
1974		// Patch Name Registry
1975		static const uint8 name_reg_dat[] = {0x70, 0xff, 0xab, 0xeb};
1976		if ((base = find_rom_data(0x300, 0x380, name_reg_dat, sizeof(name_reg_dat))) == 0) return false;
#	Line 2186 | Line 2318 | void InstallDrivers(void)
2318
2319		#if DISABLE_SCSI && 0
2320		// Fake SCSIGlobals
2321	<	static const uint8 fake_scsi_globals[32] = {0,};
2190	<	WriteMacInt32(0xc0c, (uint32)fake_scsi_globals);
2321	>	WriteMacInt32(0xc0c, SheepMem::ZeroPage());
2322		#endif
2323
2324		// Open .Sony driver

Diff Legend

–	Removed lines
+	Added lines
<	Changed lines
>	Changed lines