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root/cebix/SheepShaver/src/rom_patches.cpp

Comparing SheepShaver/src/rom_patches.cpp (file contents):
Revision 1.12 by gbeauche, 2003-10-05T23:38:07Z vs.
Revision 1.23 by gbeauche, 2003-12-15T15:27:01Z

#	Line 40 | Line 40
40		#include "audio_defs.h"
41		#include "serial.h"
42		#include "macos_util.h"
43	+	#include "thunks.h"
44
45		#define DEBUG 0
46		#include "debug.h"
#	Line 58 | Line 59
59
60
61		// Other ROM addresses
62	<	const uint32 CHECK_LOAD_PATCH_SPACE = 0x2f7f00;
63	<	const uint32 PUT_SCRAP_PATCH_SPACE = 0x2f7f80;
64	<	const uint32 GET_SCRAP_PATCH_SPACE = 0x2f7fc0;
65	<	const uint32 ADDR_MAP_PATCH_SPACE = 0x2f8000;
62	>	const uint32 CHECK_LOAD_PATCH_SPACE = 0x2fcf00;
63	>	const uint32 PUT_SCRAP_PATCH_SPACE = 0x2fcf80;
64	>	const uint32 GET_SCRAP_PATCH_SPACE = 0x2fcfc0;
65	>	const uint32 ADDR_MAP_PATCH_SPACE = 0x2fd100;
66
67		// Global variables
68		int ROMType;                            // ROM type
#	Line 131 | Line 132 | void decode_parcels(const uint8 *src, ui
132		(parcel_type >> 8) & 0xff, parcel_type & 0xff, &parcel_data[6]));
133		if (parcel_type == FOURCC('r','o','m',' ')) {
134		uint32 lzss_offset  = ntohl(parcel_data[2]);
135	<	uint32 lzss_size = ((uint32)src + parcel_offset) - ((uint32)parcel_data + lzss_offset);
135	>	uint32 lzss_size = ((uintptr)src + next_offset) - ((uintptr)parcel_data + lzss_offset);
136		decode_lzss((uint8 *)parcel_data + lzss_offset, dest, lzss_size);
137		}
138		parcel_offset = next_offset;
#	Line 269 | Line 270 | static uint32 find_rom_trap(uint16 trap)
270
271
272		/*
273	+	*  Return target of branch instruction specified at ADDR, or 0 if
274	+	*  there is no such instruction
275	+	*/
276	+
277	+	static uint32 powerpc_branch_target(uintptr addr)
278	+	{
279	+	uint32 opcode = ntohl(*(uint32 *)addr);
280	+	uint32 primop = opcode >> 26;
281	+	uint32 target = 0;
282	+
283	+	if (primop == 18) {                     // Branch
284	+	target = opcode & 0x3fffffc;
285	+	if (target & 0x2000000)
286	+	target |= 0xfc000000;
287	+	if ((opcode & 2) == 0)
288	+	target += addr;
289	+	}
290	+	else if (primop == 16) {        // Branch Conditional
291	+	target = (int32)(int16)(opcode & 0xfffc);
292	+	if ((opcode & 2) == 0)
293	+	target += addr;
294	+	}
295	+	return target;
296	+	}
297	+
298	+
299	+	/*
300	+	*  Search ROM for instruction branching to target address, return 0 if none found
301	+	*/
302	+
303	+	static uint32 find_rom_powerpc_branch(uint32 start, uint32 end, uint32 target)
304	+	{
305	+	for (uint32 addr = start; addr < end; addr += 4) {
306	+	if (powerpc_branch_target(ROM_BASE + addr) == ROM_BASE + target)
307	+	return addr;
308	+	}
309	+	return 0;
310	+	}
311	+
312	+
313	+	/*
314	+	*  Check that requested ROM patch space is really available
315	+	*/
316	+
317	+	static bool check_rom_patch_space(uint32 base, uint32 size)
318	+	{
319	+	size = (size + 3) & -4;
320	+	for (int i = 0; i < size; i += 4) {
321	+	uint32 x = ntohl(*(uint32 *)(ROM_BASE + base + i));
322	+	if (x != 0x6b636b63 && x != 0)
323	+	return false;
324	+	}
325	+	return true;
326	+	}
327	+
328	+
329	+	/*
330		*  List of audio sifters installed in ROM and System file
331		*/
332
#	Line 447 | Line 505 | static const uint8 cdrom_driver[] = {  //
505		0x4e, 0x75                                                      //  rts
506		};
507
508	<	#if EMULATED_PPC
451	<	#define SERIAL_TRAMPOLINES 1
452	<	static uint32 serial_nothing_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_NOTHING)), 0};
453	<	static uint32 serial_open_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_OPEN)), 0};
454	<	static uint32 serial_prime_in_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_PRIME_IN)), 0};
455	<	static uint32 serial_prime_out_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_PRIME_OUT)), 0};
456	<	static uint32 serial_control_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_CONTROL)), 0};
457	<	static uint32 serial_status_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_STATUS)), 0};
458	<	static uint32 serial_close_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_CLOSE)), 0};
459	<	#elif defined(__linux__)
460	<	#define SERIAL_TRAMPOLINES 1
461	<	static uint32 serial_nothing_tvect[2] = {(uint32)SerialNothing, 0};
462	<	static uint32 serial_open_tvect[2] = {(uint32)SerialOpen, 0};
463	<	static uint32 serial_prime_in_tvect[2] = {(uint32)SerialPrimeIn, 0};
464	<	static uint32 serial_prime_out_tvect[2] = {(uint32)SerialPrimeOut, 0};
465	<	static uint32 serial_control_tvect[2] = {(uint32)SerialControl, 0};
466	<	static uint32 serial_status_tvect[2] = {(uint32)SerialStatus, 0};
467	<	static uint32 serial_close_tvect[2] = {(uint32)SerialClose, 0};
468	<	#endif
508	>	static uint32 long_ptr;
509
510	<	static const uint32 ain_driver[] = {    // .AIn driver header
511	<	0x4d000000, 0x00000000,
512	<	0x00200040, 0x00600080,
513	<	0x00a0042e, 0x41496e00,
514	<	0x00000000, 0x00000000,
515	<	0xaafe0700, 0x00000000,
516	<	0x00000000, 0x00179822,
517	<	#ifdef SERIAL_TRAMPOLINES
518	<	0x00010004, (uint32)serial_nothing_tvect,
519	<	#else
520	<	0x00010004, (uint32)SerialNothing,
521	<	#endif
522	<	0x00000000, 0x00000000,
523	<	0xaafe0700, 0x00000000,
524	<	0x00000000, 0x00179822,
525	<	#ifdef SERIAL_TRAMPOLINES
526	<	0x00010004, (uint32)serial_prime_in_tvect,
527	<	#else
528	<	0x00010004, (uint32)SerialPrimeIn,
529	<	#endif
530	<	0x00000000, 0x00000000,
531	<	0xaafe0700, 0x00000000,
532	<	0x00000000, 0x00179822,
533	<	#ifdef SERIAL_TRAMPOLINES
534	<	0x00010004, (uint32)serial_control_tvect,
535	<	#else
536	<	0x00010004, (uint32)SerialControl,
537	<	#endif
538	<	0x00000000, 0x00000000,
539	<	0xaafe0700, 0x00000000,
540	<	0x00000000, 0x00179822,
541	<	#ifdef SERIAL_TRAMPOLINES
542	<	0x00010004, (uint32)serial_status_tvect,
543	<	#else
544	<	0x00010004, (uint32)SerialStatus,
545	<	#endif
546	<	0x00000000, 0x00000000,
547	<	0xaafe0700, 0x00000000,
548	<	0x00000000, 0x00179822,
549	<	#ifdef SERIAL_TRAMPOLINES
510	<	0x00010004, (uint32)serial_nothing_tvect,
511	<	#else
512	<	0x00010004, (uint32)SerialNothing,
513	<	#endif
514	<	0x00000000, 0x00000000,
510	>	static void SetLongBase(uint32 addr)
511	>	{
512	>	long_ptr = addr;
513	>	}
514	>
515	>	static void Long(uint32 value)
516	>	{
517	>	WriteMacInt32(long_ptr, value);
518	>	long_ptr += 4;
519	>	}
520	>
521	>	static void gen_ain_driver(uintptr addr)
522	>	{
523	>	SetLongBase(addr);
524	>
525	>	// .AIn driver header
526	>	Long(0x4d000000); Long(0x00000000);
527	>	Long(0x00200040); Long(0x00600080);
528	>	Long(0x00a0042e); Long(0x41496e00);
529	>	Long(0x00000000); Long(0x00000000);
530	>	Long(0xaafe0700); Long(0x00000000);
531	>	Long(0x00000000); Long(0x00179822);
532	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
533	>	Long(0x00000000); Long(0x00000000);
534	>	Long(0xaafe0700); Long(0x00000000);
535	>	Long(0x00000000); Long(0x00179822);
536	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_IN));
537	>	Long(0x00000000); Long(0x00000000);
538	>	Long(0xaafe0700); Long(0x00000000);
539	>	Long(0x00000000); Long(0x00179822);
540	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
541	>	Long(0x00000000); Long(0x00000000);
542	>	Long(0xaafe0700); Long(0x00000000);
543	>	Long(0x00000000); Long(0x00179822);
544	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
545	>	Long(0x00000000); Long(0x00000000);
546	>	Long(0xaafe0700); Long(0x00000000);
547	>	Long(0x00000000); Long(0x00179822);
548	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
549	>	Long(0x00000000); Long(0x00000000);
550		};
551
552	<	static const uint32 aout_driver[] = {   // .AOut driver header
553	<	0x4d000000, 0x00000000,
554	<	0x00200040, 0x00600080,
555	<	0x00a0052e, 0x414f7574,
556	<	0x00000000, 0x00000000,
557	<	0xaafe0700, 0x00000000,
558	<	0x00000000, 0x00179822,
559	<	#ifdef SERIAL_TRAMPOLINES
560	<	0x00010004, (uint32)serial_open_tvect,
561	<	#else
562	<	0x00010004, (uint32)SerialOpen,
563	<	#endif
564	<	0x00000000, 0x00000000,
565	<	0xaafe0700, 0x00000000,
566	<	0x00000000, 0x00179822,
567	<	#ifdef SERIAL_TRAMPOLINES
568	<	0x00010004, (uint32)serial_prime_out_tvect,
569	<	#else
570	<	0x00010004, (uint32)SerialPrimeOut,
571	<	#endif
572	<	0x00000000, 0x00000000,
573	<	0xaafe0700, 0x00000000,
574	<	0x00000000, 0x00179822,
575	<	#ifdef SERIAL_TRAMPOLINES
576	<	0x00010004, (uint32)serial_control_tvect,
577	<	#else
578	<	0x00010004, (uint32)SerialControl,
579	<	#endif
580	<	0x00000000, 0x00000000,
546	<	0xaafe0700, 0x00000000,
547	<	0x00000000, 0x00179822,
548	<	#ifdef SERIAL_TRAMPOLINES
549	<	0x00010004, (uint32)serial_status_tvect,
550	<	#else
551	<	0x00010004, (uint32)SerialStatus,
552	<	#endif
553	<	0x00000000, 0x00000000,
554	<	0xaafe0700, 0x00000000,
555	<	0x00000000, 0x00179822,
556	<	#ifdef SERIAL_TRAMPOLINES
557	<	0x00010004, (uint32)serial_close_tvect,
558	<	#else
559	<	0x00010004, (uint32)SerialClose,
560	<	#endif
561	<	0x00000000, 0x00000000,
552	>	static void gen_aout_driver(uintptr addr)
553	>	{
554	>	SetLongBase(addr);
555	>
556	>	// .AOut driver header
557	>	Long(0x4d000000); Long(0x00000000);
558	>	Long(0x00200040); Long(0x00600080);
559	>	Long(0x00a0052e); Long(0x414f7574);
560	>	Long(0x00000000); Long(0x00000000);
561	>	Long(0xaafe0700); Long(0x00000000);
562	>	Long(0x00000000); Long(0x00179822);
563	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_OPEN));
564	>	Long(0x00000000); Long(0x00000000);
565	>	Long(0xaafe0700); Long(0x00000000);
566	>	Long(0x00000000); Long(0x00179822);
567	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_OUT));
568	>	Long(0x00000000); Long(0x00000000);
569	>	Long(0xaafe0700); Long(0x00000000);
570	>	Long(0x00000000); Long(0x00179822);
571	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
572	>	Long(0x00000000); Long(0x00000000);
573	>	Long(0xaafe0700); Long(0x00000000);
574	>	Long(0x00000000); Long(0x00179822);
575	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
576	>	Long(0x00000000); Long(0x00000000);
577	>	Long(0xaafe0700); Long(0x00000000);
578	>	Long(0x00000000); Long(0x00179822);
579	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CLOSE));
580	>	Long(0x00000000); Long(0x00000000);
581		};
582
583	<	static const uint32 bin_driver[] = {    // .BIn driver header
584	<	0x4d000000, 0x00000000,
585	<	0x00200040, 0x00600080,
586	<	0x00a0042e, 0x42496e00,
587	<	0x00000000, 0x00000000,
588	<	0xaafe0700, 0x00000000,
589	<	0x00000000, 0x00179822,
590	<	#ifdef SERIAL_TRAMPOLINES
591	<	0x00010004, (uint32)serial_nothing_tvect,
592	<	#else
593	<	0x00010004, (uint32)SerialNothing,
594	<	#endif
595	<	0x00000000, 0x00000000,
596	<	0xaafe0700, 0x00000000,
597	<	0x00000000, 0x00179822,
598	<	#ifdef SERIAL_TRAMPOLINES
599	<	0x00010004, (uint32)serial_prime_in_tvect,
600	<	#else
601	<	0x00010004, (uint32)SerialPrimeIn,
602	<	#endif
603	<	0x00000000, 0x00000000,
604	<	0xaafe0700, 0x00000000,
605	<	0x00000000, 0x00179822,
606	<	#ifdef SERIAL_TRAMPOLINES
607	<	0x00010004, (uint32)serial_control_tvect,
608	<	#else
609	<	0x00010004, (uint32)SerialControl,
610	<	#endif
611	<	0x00000000, 0x00000000,
593	<	0xaafe0700, 0x00000000,
594	<	0x00000000, 0x00179822,
595	<	#ifdef SERIAL_TRAMPOLINES
596	<	0x00010004, (uint32)serial_status_tvect,
597	<	#else
598	<	0x00010004, (uint32)SerialStatus,
599	<	#endif
600	<	0x00000000, 0x00000000,
601	<	0xaafe0700, 0x00000000,
602	<	0x00000000, 0x00179822,
603	<	#ifdef SERIAL_TRAMPOLINES
604	<	0x00010004, (uint32)serial_nothing_tvect,
605	<	#else
606	<	0x00010004, (uint32)SerialNothing,
607	<	#endif
608	<	0x00000000, 0x00000000,
583	>	static void gen_bin_driver(uintptr addr)
584	>	{
585	>	SetLongBase(addr);
586	>
587	>	// .BIn driver header
588	>	Long(0x4d000000); Long(0x00000000);
589	>	Long(0x00200040); Long(0x00600080);
590	>	Long(0x00a0042e); Long(0x42496e00);
591	>	Long(0x00000000); Long(0x00000000);
592	>	Long(0xaafe0700); Long(0x00000000);
593	>	Long(0x00000000); Long(0x00179822);
594	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
595	>	Long(0x00000000); Long(0x00000000);
596	>	Long(0xaafe0700); Long(0x00000000);
597	>	Long(0x00000000); Long(0x00179822);
598	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_IN));
599	>	Long(0x00000000); Long(0x00000000);
600	>	Long(0xaafe0700); Long(0x00000000);
601	>	Long(0x00000000); Long(0x00179822);
602	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
603	>	Long(0x00000000); Long(0x00000000);
604	>	Long(0xaafe0700); Long(0x00000000);
605	>	Long(0x00000000); Long(0x00179822);
606	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
607	>	Long(0x00000000); Long(0x00000000);
608	>	Long(0xaafe0700); Long(0x00000000);
609	>	Long(0x00000000); Long(0x00179822);
610	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
611	>	Long(0x00000000); Long(0x00000000);
612		};
613
614	<	static const uint32 bout_driver[] = {   // .BOut driver header
615	<	0x4d000000, 0x00000000,
616	<	0x00200040, 0x00600080,
617	<	0x00a0052e, 0x424f7574,
618	<	0x00000000, 0x00000000,
619	<	0xaafe0700, 0x00000000,
620	<	0x00000000, 0x00179822,
621	<	#ifdef SERIAL_TRAMPOLINES
622	<	0x00010004, (uint32)serial_open_tvect,
623	<	#else
624	<	0x00010004, (uint32)SerialOpen,
625	<	#endif
626	<	0x00000000, 0x00000000,
627	<	0xaafe0700, 0x00000000,
628	<	0x00000000, 0x00179822,
629	<	#ifdef SERIAL_TRAMPOLINES
630	<	0x00010004, (uint32)serial_prime_out_tvect,
631	<	#else
632	<	0x00010004, (uint32)SerialPrimeOut,
633	<	#endif
634	<	0x00000000, 0x00000000,
635	<	0xaafe0700, 0x00000000,
636	<	0x00000000, 0x00179822,
637	<	#ifdef SERIAL_TRAMPOLINES
638	<	0x00010004, (uint32)serial_control_tvect,
639	<	#else
640	<	0x00010004, (uint32)SerialControl,
641	<	#endif
642	<	0x00000000, 0x00000000,
640	<	0xaafe0700, 0x00000000,
641	<	0x00000000, 0x00179822,
642	<	#ifdef SERIAL_TRAMPOLINES
643	<	0x00010004, (uint32)serial_status_tvect,
644	<	#else
645	<	0x00010004, (uint32)SerialStatus,
646	<	#endif
647	<	0x00000000, 0x00000000,
648	<	0xaafe0700, 0x00000000,
649	<	0x00000000, 0x00179822,
650	<	#ifdef SERIAL_TRAMPOLINES
651	<	0x00010004, (uint32)serial_close_tvect,
652	<	#else
653	<	0x00010004, (uint32)SerialClose,
654	<	#endif
655	<	0x00000000, 0x00000000,
614	>	static void gen_bout_driver(uintptr addr)
615	>	{
616	>	SetLongBase(addr);
617	>
618	>	// .BOut driver header
619	>	Long(0x4d000000); Long(0x00000000);
620	>	Long(0x00200040); Long(0x00600080);
621	>	Long(0x00a0052e); Long(0x424f7574);
622	>	Long(0x00000000); Long(0x00000000);
623	>	Long(0xaafe0700); Long(0x00000000);
624	>	Long(0x00000000); Long(0x00179822);
625	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_OPEN));
626	>	Long(0x00000000); Long(0x00000000);
627	>	Long(0xaafe0700); Long(0x00000000);
628	>	Long(0x00000000); Long(0x00179822);
629	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_OUT));
630	>	Long(0x00000000); Long(0x00000000);
631	>	Long(0xaafe0700); Long(0x00000000);
632	>	Long(0x00000000); Long(0x00179822);
633	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
634	>	Long(0x00000000); Long(0x00000000);
635	>	Long(0xaafe0700); Long(0x00000000);
636	>	Long(0x00000000); Long(0x00179822);
637	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
638	>	Long(0x00000000); Long(0x00000000);
639	>	Long(0xaafe0700); Long(0x00000000);
640	>	Long(0x00000000); Long(0x00179822);
641	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CLOSE));
642	>	Long(0x00000000); Long(0x00000000);
643		};
644
645		static const uint8 adbop_patch[] = {    // Call ADBOp() completion procedure
#	Line 725 | Line 712 | bool PatchROM(void)
712		else
713		return false;
714
715	+	// Check that other ROM addresses point to really free regions
716	+	if (!check_rom_patch_space(CHECK_LOAD_PATCH_SPACE, 0x40))
717	+	return false;
718	+	if (!check_rom_patch_space(PUT_SCRAP_PATCH_SPACE, 0x40))
719	+	return false;
720	+	if (!check_rom_patch_space(GET_SCRAP_PATCH_SPACE, 0x40))
721	+	return false;
722	+	if (!check_rom_patch_space(ADDR_MAP_PATCH_SPACE - 10 * 4, 0x100))
723	+	return false;
724	+
725		// Apply patches
726		if (!patch_nanokernel_boot()) return false;
727		if (!patch_68k_emul()) return false;
#	Line 757 | Line 754 | bool PatchROM(void)
754		static bool patch_nanokernel_boot(void)
755		{
756		uint32 *lp;
757	+	uint32 base, loc;
758
759		// ROM boot structure patches
760		lp = (uint32 *)(ROM_BASE + 0x30d000);
#	Line 769 | Line 767 | static bool patch_nanokernel_boot(void)
767		lp[0xfd8 >> 2] = htonl(ROM_BASE + 0x2a);                // 68k reset vector
768
769		// Skip SR/BAT/SDR init
770	+	loc = 0x310000;
771		if (ROMType == ROMTYPE_GAZELLE || ROMType == ROMTYPE_GOSSAMER || ROMType == ROMTYPE_NEWWORLD) {
772	<	lp = (uint32 *)(ROM_BASE + 0x310000);
772	>	lp = (uint32 *)(ROM_BASE + loc);
773		*lp++ = htonl(POWERPC_NOP);
774		*lp = htonl(0x38000000);
775		}
776	<	static const uint32 sr_init_loc[] = {0x3101b0, 0x3101b0, 0x3101b0, 0x3101ec, 0x3101fc, 0x310200};
777	<	lp = (uint32 *)(ROM_BASE + 0x310008);
778	<	*lp = htonl(0x48000000 | (sr_init_loc[ROMType] - 8) & 0xffff);  // b            ROM_BASE+0x3101b0
779	<	lp = (uint32 *)(ROM_BASE + sr_init_loc[ROMType]);
776	>	static const uint8 sr_init_dat[] = {0x35, 0x4a, 0xff, 0xfc, 0x7d, 0x86, 0x50, 0x2e};
777	>	if ((base = find_rom_data(0x3101b0, 0x3105b0, sr_init_dat, sizeof(sr_init_dat))) == 0) return false;
778	>	D(bug("sr_init %08lx\n", base));
779	>	lp = (uint32 *)(ROM_BASE + loc + 8);
780	>	*lp = htonl(0x48000000 | ((base - loc - 8) & 0x3fffffc));       // b            ROM_BASE+0x3101b0
781	>	lp = (uint32 *)(ROM_BASE + base);
782		*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);            // lwz  r1,(pointer to Kernel Data)
783		*lp++ = htonl(0x3da0dead);              // lis  r13,0xdead      (start of kernel memory)
784		*lp++ = htonl(0x3dc00010);              // lis  r14,0x0010      (size of page table)
785		*lp = htonl(0x3de00010);                // lis  r15,0x0010      (size of kernel memory)
786
787		// Don't read PVR
788	<	static const uint32 pvr_loc[] = {0x3103b0, 0x3103b4, 0x3103b4, 0x310400, 0x310430, 0x310438};
789	<	lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
788	>	static const uint8 pvr_read_dat[] = {0x7d, 0x9f, 0x42, 0xa6};
789	>	if ((base = find_rom_data(0x3103b0, 0x3108b0, pvr_read_dat, sizeof(pvr_read_dat))) == 0) return false;
790	>	D(bug("pvr_read %08lx\n", base));
791	>	lp = (uint32 *)(ROM_BASE + base);
792		*lp = htonl(0x81800000 + XLM_PVR);      // lwz  r12,(theoretical PVR)
793
794		// Set CPU specific data (even if ROM doesn't have support for that CPU)
792	–	lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
795		if (ntohl(lp[6]) != 0x2c0c0001)
796		return false;
797		uint32 ofs = ntohl(lp[7]) & 0xffff;
798		D(bug("ofs %08lx\n", ofs));
799		lp[8] = htonl((ntohl(lp[8]) & 0xffff) | 0x48000000);    // beq -> b
800	<	uint32 loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
800	>	loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
801		D(bug("loc %08lx\n", loc));
802		lp = (uint32 *)(ROM_BASE + ofs + 0x310000);
803		switch (PVR >> 16) {
#	Line 910 | Line 912 | static bool patch_nanokernel_boot(void)
912		}
913
914		// Don't set SPRG3, don't test MQ
915	<	lp = (uint32 *)(ROM_BASE + loc + 0x20);
916	<	*lp++ = htonl(POWERPC_NOP);
917	<	lp++;
918	<	*lp++ = htonl(POWERPC_NOP);
919	<	lp++;
920	<	*lp = htonl(POWERPC_NOP);
915	>	static const uint8 sprg3_mq_dat[] = {0x7d, 0x13, 0x43, 0xa6, 0x3d, 0x00, 0x00, 0x04, 0x7d, 0x00, 0x03, 0xa6, 0x39, 0x00, 0x00, 0x00, 0x7d, 0x00, 0x02, 0xa6};
916	>	if ((base = find_rom_data(loc + 0x20, loc + 0x60, sprg3_mq_dat, sizeof(sprg3_mq_dat))) == 0) return false;
917	>	D(bug("sprg3/mq %08lx\n", base));
918	>	lp = (uint32 *)(ROM_BASE + base);
919	>	lp[0] = htonl(POWERPC_NOP);
920	>	lp[2] = htonl(POWERPC_NOP);
921	>	lp[4] = htonl(POWERPC_NOP);
922
923		// Don't read MSR
924	<	lp = (uint32 *)(ROM_BASE + loc + 0x40);
924	>	static const uint8 msr_dat[] = {0x7d, 0xc0, 0x00, 0xa6};
925	>	if ((base = find_rom_data(loc + 0x40, loc + 0x80, msr_dat, sizeof(msr_dat))) == 0) return false;
926	>	D(bug("msr %08lx\n", base));
927	>	lp = (uint32 *)(ROM_BASE + base);
928		*lp = htonl(0x39c00000);                // li   r14,0
929
930		// Don't write to DEC
#	Line 928 | Line 934 | static bool patch_nanokernel_boot(void)
934		D(bug("loc %08lx\n", loc));
935
936		// Don't set SPRG3
937	<	lp = (uint32 *)(ROM_BASE + loc + 0x2c);
937	>	static const uint8 sprg3_dat[] = {0x39, 0x21, 0x03, 0x60, 0x7d, 0x33, 0x43, 0xa6, 0x39, 0x01, 0x04, 0x20};
938	>	if ((base = find_rom_data(0x310000, 0x314000, sprg3_dat, sizeof(sprg3_dat))) == 0) return false;
939	>	D(bug("sprg3 %08lx\n", base + 4));
940	>	lp = (uint32 *)(ROM_BASE + base + 4);
941		*lp = htonl(POWERPC_NOP);
942
943		// Don't read PVR
944	<	static const uint32 pvr_ofs[] = {0x138, 0x138, 0x138, 0x140, 0x148, 0x148};
945	<	lp = (uint32 *)(ROM_BASE + loc + pvr_ofs[ROMType]);
944	>	static const uint8 pvr_read2_dat[] = {0x7e, 0xff, 0x42, 0xa6, 0x56, 0xf7, 0x84, 0x3e};
945	>	if ((base = find_rom_data(0x310000, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) == 0) return false;
946	>	D(bug("pvr_read2 %08lx\n", base));
947	>	lp = (uint32 *)(ROM_BASE + base);
948		*lp = htonl(0x82e00000 + XLM_PVR);              // lwz  r23,(theoretical PVR)
949	<	lp = (uint32 *)(ROM_BASE + loc + 0x170);
950	<	if (ntohl(*lp) == 0x7eff42a6)   // NewWorld or Gossamer ROM
949	>	if ((base = find_rom_data(base + 4, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) != 0) {
950	>	D(bug("pvr_read2 %08lx\n", base));
951	>	lp = (uint32 *)(ROM_BASE + base);
952		*lp = htonl(0x82e00000 + XLM_PVR);      // lwz  r23,(theoretical PVR)
953	<	lp = (uint32 *)(ROM_BASE + 0x313134);
954	<	if (ntohl(*lp) == 0x7e5f42a6)
955	<	*lp = htonl(0x82400000 + XLM_PVR);      // lwz  r18,(theoretical PVR)
956	<	lp = (uint32 *)(ROM_BASE + 0x3131f4);
957	<	if (ntohl(*lp) == 0x7e5f42a6)   // NewWorld ROM
953	>	}
954	>	static const uint8 pvr_read3_dat[] = {0x7e, 0x5f, 0x42, 0xa6, 0x56, 0x52, 0x84, 0x3e};
955	>	if ((base = find_rom_data(0x310000, 0x320000, pvr_read3_dat, sizeof(pvr_read3_dat))) != 0) {
956	>	D(bug("pvr_read3 %08lx\n", base));
957	>	lp = (uint32 *)(ROM_BASE + base);
958		*lp = htonl(0x82400000 + XLM_PVR);      // lwz  r18,(theoretical PVR)
959	<	lp = (uint32 *)(ROM_BASE + 0x314600);
960	<	if (ntohl(*lp) == 0x7d3f42a6)
959	>	}
960	>	static const uint8 pvr_read4_dat[] = {0x7d, 0x3f, 0x42, 0xa6, 0x55, 0x29, 0x84, 0x3e};
961	>	if ((base = find_rom_data(0x310000, 0x320000, pvr_read4_dat, sizeof(pvr_read4_dat))) != 0) {
962	>	D(bug("pvr_read4 %08lx\n", base));
963	>	lp = (uint32 *)(ROM_BASE + base);
964		*lp = htonl(0x81200000 + XLM_PVR);      // lzw  r9,(theoritical PVR)
965	+	}
966
967		// Don't read SDR1
968	<	static const uint32 sdr1_ofs[] = {0x174, 0x174, 0x174, 0x17c, 0x19c, 0x19c};
969	<	lp = (uint32 *)(ROM_BASE + loc + sdr1_ofs[ROMType]);
968	>	static const uint8 sdr1_read_dat[] = {0x7d, 0x19, 0x02, 0xa6, 0x55, 0x16, 0x81, 0xde};
969	>	if ((base = find_rom_data(0x310000, 0x320000, sdr1_read_dat, sizeof(sdr1_read_dat))) == 0) return false;
970	>	D(bug("sdr1_read %08lx\n", base));
971	>	lp = (uint32 *)(ROM_BASE + base);
972		*lp++ = htonl(0x3d00dead);              // lis  r8,0xdead               (pointer to page table)
973		*lp++ = htonl(0x3ec0001f);              // lis  r22,0x001f      (size of page table)
974		*lp = htonl(POWERPC_NOP);
975
976	<	// Don't clear page table
977	<	static const uint32 pgtb_ofs[] = {0x198, 0x198, 0x198, 0x1a0, 0x1c0, 0x1c4};
978	<	lp = (uint32 *)(ROM_BASE + loc + pgtb_ofs[ROMType]);
976	>	// Don't clear page table, don't invalidate TLB
977	>	static const uint8 pgtb_clear_dat[] = {0x36, 0xd6, 0xff, 0xfc, 0x7e, 0xe8, 0xb1, 0x2e, 0x41, 0x81, 0xff, 0xf8};
978	>	if ((base = find_rom_data(0x310000, 0x320000, pgtb_clear_dat, sizeof(pgtb_clear_dat))) == 0) return false;
979	>	D(bug("pgtb_clear %08lx\n", base + 4));
980	>	lp = (uint32 *)(ROM_BASE + base + 4);
981		*lp = htonl(POWERPC_NOP);
982	<
983	<	// Don't invalidate TLB
964	<	static const uint32 tlb_ofs[] = {0x1a0, 0x1a0, 0x1a0, 0x1a8, 0x1c8, 0x1cc};
965	<	lp = (uint32 *)(ROM_BASE + loc + tlb_ofs[ROMType]);
982	>	D(bug("tblie %08lx\n", base + 12));
983	>	lp = (uint32 *)(ROM_BASE + base + 12);
984		*lp = htonl(POWERPC_NOP);
985
986		// Don't create RAM descriptor table
987	<	static const uint32 desc_ofs[] = {0x350, 0x350, 0x350, 0x358, 0x378, 0x37c};
988	<	lp = (uint32 *)(ROM_BASE + loc + desc_ofs[ROMType]);
987	>	static const uint8 desc_create_dat[] = {0x97, 0xfd, 0x00, 0x04, 0x3b, 0xff, 0x10, 0x00, 0x4b, 0xff, 0xff, 0xdc};
988	>	if ((base = find_rom_data(0x310000, 0x320000, desc_create_dat, sizeof(desc_create_dat))) == 0) return false;
989	>	D(bug("desc_create %08lx\n", base))
990	>	lp = (uint32 *)(ROM_BASE + base);
991		*lp = htonl(POWERPC_NOP);
992
993		// Don't load SRs and BATs
994	<	static const uint32 sr_ofs[] = {0x3d8, 0x3d8, 0x3d8, 0x3e0, 0x400, 0x404};
995	<	lp = (uint32 *)(ROM_BASE + loc + sr_ofs[ROMType]);
994	>	static const uint8 sr_load[] = {0x7c, 0x00, 0x04, 0xac, 0x83, 0x9d, 0x00, 0x00, 0x93, 0x81, 0x05, 0xe8};
995	>	if ((loc = find_rom_data(0x310000, 0x320000, sr_load, sizeof(sr_load))) == 0) return false;
996	>	static const uint8 sr_load_caller[] = {0x3e, 0xd6, 0xff, 0xff, 0x41, 0x81, 0xff, 0xdc, 0xb2, 0xc8, 0x00, 0x02};
997	>	if ((base = find_rom_data(0x310000, 0x320000, sr_load_caller, sizeof(sr_load_caller))) == 0) return false;
998	>	if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false;
999	>	D(bug("sr_load %08lx, called from %08lx\n", loc, base));
1000	>	lp = (uint32 *)(ROM_BASE + base);
1001		*lp = htonl(POWERPC_NOP);
1002
1003		// Don't mess with SRs
1004	<	static const uint32 sr2_ofs[] = {0x312118, 0x312118, 0x312118, 0x312118, 0x312118, 0x3121b4};
1005	<	lp = (uint32 *)(ROM_BASE + sr2_ofs[ROMType]);
1004	>	static const uint8 sr_load2_dat[] = {0x83, 0xa1, 0x05, 0xe8, 0x57, 0x7c, 0x3e, 0x78, 0x7f, 0xbd, 0xe0, 0x2e};
1005	>	if ((base = find_rom_data(0x310000, 0x320000, sr_load2_dat, sizeof(sr_load2_dat))) == 0) return false;
1006	>	D(bug("sr_load2 %08lx\n", base));
1007	>	lp = (uint32 *)(ROM_BASE + base);
1008		*lp = htonl(POWERPC_BLR);
1009
1010		// Don't check performance monitor
1011	<	static const uint32 pm_ofs[] = {0x313148, 0x313148, 0x313148, 0x313148, 0x313158, 0x313218};
1012	<	lp = (uint32 *)(ROM_BASE + pm_ofs[ROMType]);
1013	<	while (ntohl(*lp) != 0x7e58eba6) lp++;
1014	<	*lp++ = htonl(POWERPC_NOP);
1015	<	while (ntohl(*lp) != 0x7e78eaa6) lp++;
1016	<	*lp++ = htonl(POWERPC_NOP);
1017	<	while (ntohl(*lp) != 0x7e59eba6) lp++;
1018	<	*lp++ = htonl(POWERPC_NOP);
1019	<	while (ntohl(*lp) != 0x7e79eaa6) lp++;
1020	<	*lp++ = htonl(POWERPC_NOP);
1021	<	while (ntohl(*lp) != 0x7e5aeba6) lp++;
1022	<	*lp++ = htonl(POWERPC_NOP);
1023	<	while (ntohl(*lp) != 0x7e7aeaa6) lp++;
1024	<	*lp++ = htonl(POWERPC_NOP);
1025	<	while (ntohl(*lp) != 0x7e5beba6) lp++;
1026	<	*lp++ = htonl(POWERPC_NOP);
1027	<	while (ntohl(*lp) != 0x7e7beaa6) lp++;
1028	<	*lp++ = htonl(POWERPC_NOP);
1029	<	while (ntohl(*lp) != 0x7e5feba6) lp++;
1030	<	*lp++ = htonl(POWERPC_NOP);
1031	<	while (ntohl(*lp) != 0x7e7feaa6) lp++;
1032	<	*lp++ = htonl(POWERPC_NOP);
1033	<	while (ntohl(*lp) != 0x7e5ceba6) lp++;
1034	<	*lp++ = htonl(POWERPC_NOP);
1008	<	while (ntohl(*lp) != 0x7e7ceaa6) lp++;
1009	<	*lp++ = htonl(POWERPC_NOP);
1010	<	while (ntohl(*lp) != 0x7e5deba6) lp++;
1011	<	*lp++ = htonl(POWERPC_NOP);
1012	<	while (ntohl(*lp) != 0x7e7deaa6) lp++;
1013	<	*lp++ = htonl(POWERPC_NOP);
1014	<	while (ntohl(*lp) != 0x7e5eeba6) lp++;
1015	<	*lp++ = htonl(POWERPC_NOP);
1016	<	while (ntohl(*lp) != 0x7e7eeaa6) lp++;
1017	<	*lp++ = htonl(POWERPC_NOP);
1011	>	static const uint8 pm_check_dat[] = {0x7e, 0x58, 0xeb, 0xa6, 0x7e, 0x53, 0x90, 0xf8, 0x7e, 0x78, 0xea, 0xa6};
1012	>	if ((base = find_rom_data(0x310000, 0x320000, pm_check_dat, sizeof(pm_check_dat))) == 0) return false;
1013	>	D(bug("pm_check %08lx\n", base));
1014	>	lp = (uint32 *)(ROM_BASE + base);
1015	>
1016	>	static const int spr_check_list[] = {
1017	>	952 /* mmcr0 */, 953 /* pmc1 */, 954 /* pmc2 */, 955 /* sia */,
1018	>	956 /* mmcr1 */, 957 /* pmc3 */, 958 /* pmc4 */, 959 /* sda */
1019	>	};
1020	>
1021	>	for (int i = 0; i < sizeof(spr_check_list)/sizeof(spr_check_list[0]); i++) {
1022	>	int spr = spr_check_list[i];
1023	>	uint32 mtspr = 0x7e4003a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6);
1024	>	uint32 mfspr = 0x7e6002a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6);
1025	>	for (int ofs = 0; ofs < 64; ofs++) {
1026	>	if (ntohl(lp[ofs]) == mtspr) {
1027	>	if (ntohl(lp[ofs + 2]) != mfspr)
1028	>	return false;
1029	>	D(bug("  SPR%d %08lx\n", spr, base + 4*ofs));
1030	>	lp[ofs] = htonl(POWERPC_NOP);
1031	>	lp[ofs + 2] = htonl(POWERPC_NOP);
1032	>	}
1033	>	}
1034	>	}
1035
1036		// Jump to 68k emulator
1037	<	static const uint32 jump68k_ofs[] = {0x40c, 0x40c, 0x40c, 0x414, 0x434, 0x438};
1038	<	lp = (uint32 *)(ROM_BASE + loc + jump68k_ofs[ROMType]);
1037	>	static const uint8 jump68k_dat[] = {0x7d, 0x92, 0x43, 0xa6, 0x7d, 0x5a, 0x03, 0xa6, 0x7d, 0x7b, 0x03, 0xa6};
1038	>	if ((loc = find_rom_data(0x310000, 0x320000, jump68k_dat, sizeof(jump68k_dat))) == 0) return false;
1039	>	static const uint8 jump68k_caller_dat[] = {0x85, 0x13, 0x00, 0x08, 0x56, 0xbf, 0x50, 0x3e, 0x63, 0xff, 0x0c, 0x00};
1040	>	if ((base = find_rom_data(0x310000, 0x320000, jump68k_caller_dat, sizeof(jump68k_caller_dat))) == 0) return false;
1041	>	if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false;
1042	>	D(bug("jump68k %08lx, called from %08lx\n", loc, base));
1043	>	lp = (uint32 *)(ROM_BASE + base);
1044		*lp++ = htonl(0x80610634);              // lwz  r3,0x0634(r1)   (pointer to Emulator Data)
1045		*lp++ = htonl(0x8081119c);              // lwz  r4,0x119c(r1)   (pointer to opcode table)
1046		*lp++ = htonl(0x80011184);              // lwz  r0,0x1184(r1)   (pointer to emulator init routine)
#	Line 1038 | Line 1060 | static bool patch_68k_emul(void)
1060		uint32 base;
1061
1062		// Overwrite twi instructions
1063	<	static const uint32 twi_loc[] = {0x36e680, 0x36e6c0, 0x36e6c0, 0x36e6c0, 0x36e740, 0x36e740};
1064	<	base = twi_loc[ROMType];
1063	>	static const uint8 twi_dat[] = {0x0f, 0xff, 0x00, 0x00, 0x0f, 0xff, 0x00, 0x01, 0x0f, 0xff, 0x00, 0x02};
1064	>	if ((base = find_rom_data(0x36e600, 0x36ea00, twi_dat, sizeof(twi_dat))) == 0) return false;
1065	>	D(bug("twi %08lx\n", base));
1066		lp = (uint32 *)(ROM_BASE + base);
1067		*lp++ = htonl(0x48000000 + 0x36f900 - base);            // b 0x36f900 (Emulator start)
1068		*lp++ = htonl(0x48000000 + 0x36fa00 - base - 4);        // b 0x36fa00 (Mixed mode)
#	Line 1099 | Line 1122 | static bool patch_68k_emul(void)
1122		lp = (uint32 *)(ROM_BASE + 0x36f900);
1123		*lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1124		#if EMULATED_PPC
1125	<	*lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1125	>	*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1126		#else
1127		*lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1128		*lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
#	Line 1133 | Line 1156 | static bool patch_68k_emul(void)
1156		lp = (uint32 *)(ROM_BASE + 0x36fa00);
1157		*lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1158		#if EMULATED_PPC
1159	<	*lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1159	>	*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1160		#else
1161		*lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1162		*lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
#	Line 1167 | Line 1190 | static bool patch_68k_emul(void)
1190		lp = (uint32 *)(ROM_BASE + 0x36fb00);
1191		*lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1192		#if EMULATED_PPC
1193	<	*lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1193	>	*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1194		#else
1195		*lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1196		*lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
#	Line 1201 | Line 1224 | static bool patch_68k_emul(void)
1224		lp = (uint32 *)(ROM_BASE + 0x36fc00);
1225		*lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1226		#if EMULATED_PPC
1227	<	*lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1227	>	*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1228		#else
1229		*lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1230		*lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
#	Line 1259 | Line 1282 | dr_found:
1282		static bool patch_nanokernel(void)
1283		{
1284		uint32 *lp;
1285	+	uint32 base, loc;
1286
1287		// Patch Mixed Mode trap
1288	<	lp = (uint32 *)(ROM_BASE + 0x313c90);   // Don't translate virtual->physical
1289	<	while (ntohl(*lp) != 0x3ba10320) lp++;
1290	<	lp++;
1291	<	*lp++ = htonl(0x7f7fdb78);                                      // mr           r31,r27
1292	<	lp++;
1293	<	*lp = htonl(POWERPC_NOP);
1294	<
1295	<	lp = (uint32 *)(ROM_BASE + 0x313c3c);   // Don't activate PPC exception table
1296	<	while (ntohl(*lp) != 0x39010420) lp++;
1288	>	static const uint8 virt2phys_dat[] = {0x7d, 0x1b, 0x43, 0x78, 0x3b, 0xa1, 0x03, 0x20};
1289	>	if ((base = find_rom_data(0x313000, 0x314000, virt2phys_dat, sizeof(virt2phys_dat))) == 0) return false;
1290	>	D(bug("virt2phys %08lx\n", base + 8));
1291	>	lp = (uint32 *)(ROM_BASE + base + 8);   // Don't translate virtual->physical
1292	>	lp[0] = htonl(0x7f7fdb78);                                      // mr           r31,r27
1293	>	lp[2] = htonl(POWERPC_NOP);
1294	>
1295	>	static const uint8 ppc_excp_tbl_dat[] = {0x39, 0x01, 0x04, 0x20, 0x7d, 0x13, 0x43, 0xa6};
1296	>	if ((base = find_rom_data(0x313000, 0x314000, ppc_excp_tbl_dat, sizeof(ppc_excp_tbl_dat))) == 0) return false;
1297	>	D(bug("ppc_excp_tbl %08lx\n", base));
1298	>	lp = (uint32 *)(ROM_BASE + base);               // Don't activate PPC exception table
1299		*lp++ = htonl(0x39000000 + MODE_NATIVE);        // li   r8,MODE_NATIVE
1300	<	*lp = htonl(0x91000000 + XLM_RUN_MODE); // stw  r8,XLM_RUN_MODE
1300	>	*lp = htonl(0x91000000 + XLM_RUN_MODE);         // stw  r8,XLM_RUN_MODE
1301
1302	<	lp = (uint32 *)(ROM_BASE + 0x312e88);   // Don't modify MSR to turn on FPU
1303	<	while (ntohl(*lp) != 0x556b04e2) lp++;
1304	<	lp -= 4;
1302	>	static const uint8 save_fpu_dat[] = {0x7d, 0x00, 0x00, 0xa6, 0x61, 0x08, 0x20, 0x00, 0x7d, 0x00, 0x01, 0x24};
1303	>	if ((base = find_rom_data(0x310000, 0x314000, save_fpu_dat, sizeof(save_fpu_dat))) == 0) return false;
1304	>	D(bug("save_fpu %08lx\n", base));
1305	>	lp = (uint32 *)(ROM_BASE + base);               // Don't modify MSR to turn on FPU
1306	>	if (ntohl(lp[4]) != 0x556b04e2) return false;
1307	>	loc = ROM_BASE + base;
1308	>	#if 1
1309	>	// FIXME: is that really intended?
1310		*lp++ = htonl(POWERPC_NOP);
1311		lp++;
1312		*lp++ = htonl(POWERPC_NOP);
1313		lp++;
1314		*lp = htonl(POWERPC_NOP);
1315	+	#else
1316	+	lp[0] = htonl(POWERPC_NOP);
1317	+	lp[1] = htonl(POWERPC_NOP);
1318	+	lp[2] = htonl(POWERPC_NOP);
1319	+	lp[3] = htonl(POWERPC_NOP);
1320	+	#endif
1321
1322	<	lp = (uint32 *)(ROM_BASE + 0x312b3c);   // Always save FPU state
1323	<	while (ntohl(*lp) != 0x81010668) lp++;
1324	<	lp--;
1322	>	static const uint8 save_fpu_caller_dat[] = {0x93, 0xa6, 0x01, 0xec, 0x93, 0xc6, 0x01, 0xf4, 0x93, 0xe6, 0x01, 0xfc, 0x40};
1323	>	if ((base = find_rom_data(0x310000, 0x314000, save_fpu_caller_dat, sizeof(save_fpu_caller_dat))) == 0) return false;
1324	>	D(bug("save_fpu_caller %08lx\n", base + 12));
1325	>	if (powerpc_branch_target(ROM_BASE + base + 12) != loc) return false;
1326	>	lp = (uint32 *)(ROM_BASE + base + 12);  // Always save FPU state
1327		*lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312e88
1328
1329	<	lp = (uint32 *)(ROM_BASE + 0x312b44);   // Don't read DEC
1330	<	while (ntohl(*lp) != 0x7ff602a6) lp++;
1331	<	*lp = htonl(0x3be00000);                                        // li   r31,0
1332	<
1333	<	lp = (uint32 *)(ROM_BASE + 0x312b50);   // Don't write DEC
1295	<	while (ntohl(*lp) != 0x7d1603a6) lp++;
1329	>	static const uint8 mdec_dat[] = {0x7f, 0xf6, 0x02, 0xa6, 0x2c, 0x08, 0x00, 0x00, 0x93, 0xe1, 0x06, 0x68, 0x7d, 0x16, 0x03, 0xa6};
1330	>	if ((base = find_rom_data(0x310000, 0x314000, mdec_dat, sizeof(mdec_dat))) == 0) return false;
1331	>	D(bug("mdec %08lx\n", base));
1332	>	lp = (uint32 *)(ROM_BASE + base);               // Don't modify DEC
1333	>	lp[0] = htonl(0x3be00000);                                      // li   r31,0
1334		#if 1
1335	<	*lp++ = htonl(POWERPC_NOP);
1336	<	*lp = htonl(POWERPC_NOP);
1335	>	lp[3] = htonl(POWERPC_NOP);
1336	>	lp[4] = htonl(POWERPC_NOP);
1337		#else
1338	<	*lp++ = htonl(0x39000040);                                      // li   r8,0x40
1339	<	*lp = htonl(0x990600e4);                                        // stb  r8,0xe4(r6)
1338	>	lp[3] = htonl(0x39000040);                                      // li   r8,0x40
1339	>	lp[4] = htonl(0x990600e4);                                      // stb  r8,0xe4(r6)
1340		#endif
1341
1342	<	lp = (uint32 *)(ROM_BASE + 0x312b9c);   // Always restore FPU state
1343	<	while (ntohl(*lp) != 0x7c00092d) lp++;
1344	<	lp--;
1342	>	static const uint8 restore_fpu_caller_dat[] = {0x81, 0x06, 0x00, 0xf4, 0x81, 0x46, 0x00, 0xfc, 0x7d, 0x09, 0x03, 0xa6, 0x40};
1343	>	if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller_dat, sizeof(restore_fpu_caller_dat))) == 0) return false;
1344	>	D(bug("restore_fpu_caller %08lx\n", base + 12));
1345	>	lp = (uint32 *)(ROM_BASE + base + 12);  // Always restore FPU state
1346		*lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312ddc
1347
1348	<	lp = (uint32 *)(ROM_BASE + 0x312a68);   // Don't activate 68k exception table
1349	<	while (ntohl(*lp) != 0x39010360) lp++;
1348	>	static const uint8 m68k_excp_tbl_dat[] = {0x81, 0x21, 0x06, 0x58, 0x39, 0x01, 0x03, 0x60, 0x7d, 0x13, 0x43, 0xa6};
1349	>	if ((base = find_rom_data(0x310000, 0x314000, m68k_excp_tbl_dat, sizeof(m68k_excp_tbl_dat))) == 0) return false;
1350	>	D(bug("m68k_excp %08lx\n", base + 4));
1351	>	lp = (uint32 *)(ROM_BASE + base + 4);   // Don't activate 68k exception table
1352		*lp++ = htonl(0x39000000 + MODE_68K);           // li   r8,MODE_68K
1353		*lp = htonl(0x91000000 + XLM_RUN_MODE);         // stw  r8,XLM_RUN_MODE
1354
1355		// Patch 68k emulator trap routine
1356	<	lp = (uint32 *)(ROM_BASE + 0x312994);   // Always restore FPU state
1357	<	while (ntohl(*lp) != 0x39260040) lp++;
1358	<	lp--;
1356	>	static const uint8 restore_fpu_caller2_dat[] = {0x81, 0x86, 0x00, 0x8c, 0x80, 0x66, 0x00, 0x94, 0x80, 0x86, 0x00, 0x9c, 0x40};
1357	>	if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller2_dat, sizeof(restore_fpu_caller2_dat))) == 0) return false;
1358	>	D(bug("restore_fpu_caller2 %08lx\n", base + 12));
1359	>	loc = powerpc_branch_target(ROM_BASE + base + 12) - ROM_BASE;
1360	>	lp = (uint32 *)(ROM_BASE + base + 12);  // Always restore FPU state
1361		*lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312dd4
1362
1363	<	lp = (uint32 *)(ROM_BASE + 0x312dd8);   // Don't modify MSR to turn on FPU
1364	<	while (ntohl(*lp) != 0x810600e4) lp++;
1365	<	lp--;
1363	>	static const uint8 restore_fpu_dat[] = {0x55, 0x68, 0x04, 0xa5, 0x4c, 0x82, 0x00, 0x20, 0x81, 0x06, 0x00, 0xe4};
1364	>	if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_dat, sizeof(restore_fpu_dat))) == 0) return false;
1365	>	D(bug("restore_fpu %08lx\n", base));
1366	>	if (base != loc) return false;
1367	>	lp = (uint32 *)(ROM_BASE + base + 4);   // Don't modify MSR to turn on FPU
1368		*lp++ = htonl(POWERPC_NOP);
1369		lp += 2;
1370		*lp++ = htonl(POWERPC_NOP);
#	Line 1329 | Line 1374 | static bool patch_nanokernel(void)
1374		*lp = htonl(POWERPC_NOP);
1375
1376		// Patch trap return routine
1377	<	lp = (uint32 *)(ROM_BASE + 0x312c20);
1378	<	while (ntohl(*lp) != 0x7d5a03a6) lp++;
1377	>	static const uint8 trap_return_dat[] = {0x80, 0xc1, 0x00, 0x18, 0x80, 0x21, 0x00, 0x04, 0x4c, 0x00, 0x00, 0x64};
1378	>	if ((base = find_rom_data(0x312000, 0x320000, trap_return_dat, sizeof(trap_return_dat))) == 0) return false;
1379	>	D(bug("trap_return %08lx\n", base + 8));
1380	>	lp = (uint32 *)(ROM_BASE + base + 8);   // Replace rfi
1381	>	*lp = htonl(POWERPC_BCTR);
1382	>
1383	>	while (ntohl(*lp) != 0x7d5a03a6) lp--;
1384		*lp++ = htonl(0x7d4903a6);                                      // mtctr        r10
1385		*lp++ = htonl(0x7daff120);                                      // mtcr r13
1386	<	*lp = htonl(0x48000000 + 0x8000 - (((uint32)lp - ROM_BASE) & 0xffff));  // b            ROM_BASE+0x318000
1387	<	uint32 xlp = ((uint32)(lp+1) - ROM_BASE) & 0xffff;
1338	<
1339	<	lp = (uint32 *)(ROM_BASE + 0x312c50);   // Replace rfi
1340	<	while (ntohl(*lp) != 0x4c000064) lp++;
1341	<	*lp = htonl(POWERPC_BCTR);
1386	>	*lp = htonl(0x48000000 + ((0x318000 - ((uint32)lp - ROM_BASE)) & 0x03fffffc));  // b            ROM_BASE+0x318000
1387	>	uint32 npc = (uint32)(lp + 1) - ROM_BASE;
1388
1389		lp = (uint32 *)(ROM_BASE + 0x318000);
1390		#if EMULATED_PPC
1391	<	*lp++ = POWERPC_NATIVE_OP(NATIVE_ENABLE_INTERRUPT);
1392	<	*lp = htonl(0x48000000 + ((xlp - 0x8004) & 0x03fffffc));        // b            ROM_BASE+0x312c2c
1391	>	*lp++ = htonl(NativeOpcode(NATIVE_ENABLE_INTERRUPT));
1392	>	*lp = htonl(0x48000000 + ((npc - 0x318004) & 0x03fffffc));      // b            ROM_BASE+0x312c2c
1393		#else
1394		*lp++ = htonl(0x81400000 + XLM_IRQ_NEST);       // lwz  r10,XLM_IRQ_NEST
1395		*lp++ = htonl(0x394affff);                                      // subi r10,r10,1
1396		*lp++ = htonl(0x91400000 + XLM_IRQ_NEST);       // stw  r10,XLM_IRQ_NEST
1397	<	*lp = htonl(0x48000000 + ((xlp - 0x800c) & 0x03fffffc));        // b            ROM_BASE+0x312c2c
1397	>	*lp = htonl(0x48000000 + ((npc - 0x31800c) & 0x03fffffc));      // b            ROM_BASE+0x312c2c
1398		#endif
1399
1400		/*
#	Line 1370 | Line 1416 | static bool patch_68k(void)
1416		uint32 *lp;
1417		uint16 *wp;
1418		uint8 *bp;
1419	<	uint32 base;
1419	>	uint32 base, loc;
1420
1421		// Remove 68k RESET instruction
1422		static const uint8 reset_dat[] = {0x4e, 0x70};
#	Line 1611 | Line 1657 | static bool patch_68k(void)
1657		*wp = htons(M68K_NOP);
1658
1659		// Don't initialize SCC (via 0x1ac)
1660	<	static const uint8 scc_init_dat[] = {0x48, 0xe7, 0x38, 0xfe};
1661	<	if ((base = find_rom_data(0x190, 0x1f0, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1660	>	static const uint8 scc_init_caller_dat[] = {0x21, 0xce, 0x01, 0x08, 0x22, 0x78, 0x0d, 0xd8};
1661	>	if ((base = find_rom_data(0x180, 0x1f0, scc_init_caller_dat, sizeof(scc_init_caller_dat))) == 0) return false;
1662	>	D(bug("scc_init_caller %08lx\n", base + 12));
1663	>	wp = (uint16 *)(ROM_BASE + base + 12);
1664	>	loc = ntohs(wp[1]) + ((uintptr)wp - ROM_BASE) + 2;
1665	>	static const uint8 scc_init_dat[] = {0x20, 0x78, 0x01, 0xdc, 0x22, 0x78, 0x01, 0xd8};
1666	>	if ((base = find_rom_data(loc, loc + 0x80, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1667		D(bug("scc_init %08lx\n", base));
1668	<	wp = (uint16 *)(ROM_BASE + base - 2);
1618	<	wp = (uint16 *)(ROM_BASE + ntohs(*wp) + base - 2);
1668	>	wp = (uint16 *)(ROM_BASE + base);
1669		*wp++ = htons(M68K_EMUL_OP_RESET);
1670		*wp = htons(M68K_RTS);
1671
#	Line 1842 | Line 1892 | static bool patch_68k(void)
1892		*wp = htons(M68K_RTS);
1893
1894		// Don't install Time Manager task for 60Hz interrupt (Enable60HzInts, via 0x2b8)
1895	<	if (ROMType == ROMTYPE_NEWWORLD) {
1895	>	if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_GOSSAMER) {
1896		static const uint8 tm_task_dat[] = {0x30, 0x3c, 0x4e, 0x2b, 0xa9, 0xc9};
1897	<	if ((base = find_rom_data(0x2e0, 0x320, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1897	>	if ((base = find_rom_data(0x2a0, 0x320, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1898		D(bug("tm_task %08lx\n", base));
1899	<	wp = (uint16 *)(ROM_BASE + base + 28); // FIXME: this is not right for all nw ROMs
1899	>	wp = (uint16 *)(ROM_BASE + base + 28);
1900		*wp++ = htons(M68K_NOP);
1901		*wp++ = htons(M68K_NOP);
1902		*wp++ = htons(M68K_NOP);
1903		*wp++ = htons(M68K_NOP);
1904		*wp++ = htons(M68K_NOP);
1905		*wp = htons(M68K_NOP);
1856	–	} else if (ROMType == ROMTYPE_GOSSAMER) {
1857	–	static const uint8 tm_task_dat[] = {0x30, 0x3c, 0x4e, 0x2b, 0xa9, 0xc9};
1858	–	if ((base = find_rom_data(0x2a0, 0x2e0, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1859	–	D(bug("tm_task %08lx\n", base));
1860	–	wp = (uint16 *)(ROM_BASE + base + 28);
1861	–	*wp++ = htons(M68K_NOP);
1862	–	*wp++ = htons(M68K_NOP);
1863	–	*wp++ = htons(M68K_NOP);
1906		} else {
1907		static const uint8 tm_task_dat[] = {0x20, 0x3c, 0x73, 0x79, 0x73, 0x61};
1908		if ((base = find_rom_data(0x280, 0x300, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
#	Line 1907 | Line 1949 | static bool patch_68k(void)
1949		*lp = htonl(0x38600000);                // li   r3,0
1950		}
1951
1952	+	// FIXME: Fake reading from [HpChk]+4 (the callchain reports some function from DriverServicesLib)
1953	+	if (1) {
1954	+	uint32 hpchk_offset = find_rom_resource(FOURCC('n','l','i','b'), 10);
1955	+	static const uint8 hpchk_dat[] = {0x80, 0x80, 0x03, 0x16, 0x94, 0x21, 0xff, 0xb0, 0x83, 0xc4, 0x00, 0x04};
1956	+	if ((base = find_rom_data(hpchk_offset, hpchk_offset + 0x3000, hpchk_dat, sizeof(hpchk_dat))) == 0) return false;
1957	+	D(bug("hpchk %08lx\n", base));
1958	+	lp = (uint32 *)(ROM_BASE + base);
1959	+	*lp = htonl(0x80800000 + XLM_ZERO_PAGE);                // lwz  r4,(zero page)
1960	+	}
1961	+
1962		// Patch Name Registry
1963		static const uint8 name_reg_dat[] = {0x70, 0xff, 0xab, 0xeb};
1964		if ((base = find_rom_data(0x300, 0x380, name_reg_dat, sizeof(name_reg_dat))) == 0) return false;
#	Line 2030 | Line 2082 | static bool patch_68k(void)
2082		memcpy((void *)(ROM_BASE + sony_offset + 0x200), cdrom_driver, sizeof(cdrom_driver));
2083
2084		// Install serial drivers
2085	<	memcpy_powerpc_code((void *)(ROM_BASE + sony_offset + 0x300), ain_driver, sizeof(ain_driver));
2086	<	memcpy_powerpc_code((void *)(ROM_BASE + sony_offset + 0x400), aout_driver, sizeof(aout_driver));
2087	<	memcpy_powerpc_code((void *)(ROM_BASE + sony_offset + 0x500), bin_driver, sizeof(bin_driver));
2088	<	memcpy_powerpc_code((void *)(ROM_BASE + sony_offset + 0x600), bout_driver, sizeof(bout_driver));
2085	>	gen_ain_driver( ROM_BASE + sony_offset + 0x300);
2086	>	gen_aout_driver(ROM_BASE + sony_offset + 0x400);
2087	>	gen_bin_driver( ROM_BASE + sony_offset + 0x500);
2088	>	gen_bout_driver(ROM_BASE + sony_offset + 0x600);
2089
2090		// Copy icons to ROM
2091		SonyDiskIconAddr = ROM_BASE + sony_offset + 0x800;
#	Line 2235 | Line 2287 | void InstallDrivers(void)
2287		{
2288		D(bug("Installing drivers...\n"));
2289		M68kRegisters r;
2290	<	uint8 pb[SIZEOF_IOParam];
2290	>	SheepArray<SIZEOF_IOParam> pb_var;
2291	>	const uintptr pb = pb_var.addr();
2292
2293		// Install floppy driver
2294	<	if (ROMType == ROMTYPE_NEWWORLD) {
2294	>	if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_GOSSAMER) {
2295
2296	<	// Force installation of floppy driver with NewWorld ROMs
2296	>	// Force installation of floppy driver with NewWorld and Gossamer ROMs
2297		r.a[0] = ROM_BASE + sony_offset;
2298		r.d[0] = (uint32)SonyRefNum;
2299		Execute68kTrap(0xa43d, &r);             // DrvrInstallRsrvMem()
#	Line 2253 | Line 2306 | void InstallDrivers(void)
2306
2307		#if DISABLE_SCSI && 0
2308		// Fake SCSIGlobals
2309	<	static const uint8 fake_scsi_globals[32] = {0,};
2257	<	WriteMacInt32(0xc0c, (uint32)fake_scsi_globals);
2309	>	WriteMacInt32(0xc0c, SheepMem::ZeroPage());
2310		#endif
2311
2312		// Open .Sony driver
2313	<	WriteMacInt8((uint32)pb + ioPermssn, 0);
2314	<	WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Sony");
2315	<	r.a[0] = (uint32)pb;
2313	>	SheepString sony_str("\005.Sony");
2314	>	WriteMacInt8(pb + ioPermssn, 0);
2315	>	WriteMacInt32(pb + ioNamePtr, sony_str.addr());
2316	>	r.a[0] = pb;
2317		Execute68kTrap(0xa000, &r);             // Open()
2318
2319		// Install disk driver
#	Line 2274 | Line 2327 | void InstallDrivers(void)
2327		WriteMacInt16(dce + dCtlFlags, DiskDriverFlags);
2328
2329		// Open disk driver
2330	<	WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Disk");
2331	<	r.a[0] = (uint32)pb;
2330	>	SheepString disk_str("\005.Disk");
2331	>	WriteMacInt32(pb + ioNamePtr, disk_str.addr());
2332	>	r.a[0] = pb;
2333		Execute68kTrap(0xa000, &r);             // Open()
2334
2335		// Install CD-ROM driver unless nocdrom option given
#	Line 2292 | Line 2346 | void InstallDrivers(void)
2346		WriteMacInt16(dce + dCtlFlags, CDROMDriverFlags);
2347
2348		// Open CD-ROM driver
2349	<	WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\010.AppleCD");
2350	<	r.a[0] = (uint32)pb;
2349	>	SheepString apple_cd("\010.AppleCD");
2350	>	WriteMacInt32(pb + ioNamePtr, apple_cd.addr());
2351	>	r.a[0] = pb;
2352		Execute68kTrap(0xa000, &r);             // Open()
2353		}
2354

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