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root/cebix/SheepShaver/src/rom_patches.cpp

Comparing SheepShaver/src/rom_patches.cpp (file contents):
Revision 1.8 by gbeauche, 2003-09-28T21:27:33Z vs.
Revision 1.21 by gbeauche, 2003-12-15T15:23:59Z

#	Line 40 | Line 40
40		#include "audio_defs.h"
41		#include "serial.h"
42		#include "macos_util.h"
43	+	#include "thunks.h"
44
45		#define DEBUG 0
46		#include "debug.h"
#	Line 58 | Line 59
59
60
61		// Other ROM addresses
62	<	const uint32 CHECK_LOAD_PATCH_SPACE = 0x2f7f00;
63	<	const uint32 PUT_SCRAP_PATCH_SPACE = 0x2f7f80;
64	<	const uint32 GET_SCRAP_PATCH_SPACE = 0x2f7fc0;
65	<	const uint32 ADDR_MAP_PATCH_SPACE = 0x2f8000;
62	>	const uint32 CHECK_LOAD_PATCH_SPACE = 0x2fcf00;
63	>	const uint32 PUT_SCRAP_PATCH_SPACE = 0x2fcf80;
64	>	const uint32 GET_SCRAP_PATCH_SPACE = 0x2fcfc0;
65	>	const uint32 ADDR_MAP_PATCH_SPACE = 0x2fd100;
66
67		// Global variables
68		int ROMType;                            // ROM type
#	Line 131 | Line 132 | void decode_parcels(const uint8 *src, ui
132		(parcel_type >> 8) & 0xff, parcel_type & 0xff, &parcel_data[6]));
133		if (parcel_type == FOURCC('r','o','m',' ')) {
134		uint32 lzss_offset  = ntohl(parcel_data[2]);
135	<	uint32 lzss_size = ((uint32)src + parcel_offset) - ((uint32)parcel_data + lzss_offset);
135	>	uint32 lzss_size = ((uintptr)src + next_offset) - ((uintptr)parcel_data + lzss_offset);
136		decode_lzss((uint8 *)parcel_data + lzss_offset, dest, lzss_size);
137		}
138		parcel_offset = next_offset;
#	Line 269 | Line 270 | static uint32 find_rom_trap(uint16 trap)
270
271
272		/*
273	+	*  Return target of branch instruction specified at ADDR, or 0 if
274	+	*  there is no such instruction
275	+	*/
276	+
277	+	static uint32 powerpc_branch_target(uintptr addr)
278	+	{
279	+	uint32 opcode = ntohl(*(uint32 *)addr);
280	+	uint32 primop = opcode >> 26;
281	+	uint32 target = 0;
282	+
283	+	if (primop == 18) {                     // Branch
284	+	target = opcode & 0x3fffffc;
285	+	if (target & 0x2000000)
286	+	target |= 0xfc000000;
287	+	if ((opcode & 2) == 0)
288	+	target += addr;
289	+	}
290	+	else if (primop == 16) {        // Branch Conditional
291	+	target = (int32)(int16)(opcode & 0xfffc);
292	+	if ((opcode & 2) == 0)
293	+	target += addr;
294	+	}
295	+	return target;
296	+	}
297	+
298	+
299	+	/*
300	+	*  Search ROM for instruction branching to target address, return 0 if none found
301	+	*/
302	+
303	+	static uint32 find_rom_powerpc_branch(uint32 start, uint32 end, uint32 target)
304	+	{
305	+	for (uint32 addr = start; addr < end; addr += 4) {
306	+	if (powerpc_branch_target(ROM_BASE + addr) == ROM_BASE + target)
307	+	return addr;
308	+	}
309	+	return 0;
310	+	}
311	+
312	+
313	+	/*
314	+	*  Check that requested ROM patch space is really available
315	+	*/
316	+
317	+	static bool check_rom_patch_space(uint32 base, uint32 size)
318	+	{
319	+	size = (size + 3) & -4;
320	+	for (int i = 0; i < size; i += 4) {
321	+	uint32 x = ntohl(*(uint32 *)(ROM_BASE + base + i));
322	+	printf("%08x\n", x);
323	+	if (x != 0x6b636b63 && x != 0)
324	+	return false;
325	+	}
326	+	return true;
327	+	}
328	+
329	+
330	+	/*
331		*  List of audio sifters installed in ROM and System file
332		*/
333
#	Line 447 | Line 506 | static const uint8 cdrom_driver[] = {  //
506		0x4e, 0x75                                                      //  rts
507		};
508
509	<	#if EMULATED_PPC
451	<	#define SERIAL_TRAMPOLINES 1
452	<	static uint32 serial_nothing_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_NOTHING), 0};
453	<	static uint32 serial_open_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_OPEN), 0};
454	<	static uint32 serial_prime_in_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_PRIME_IN), 0};
455	<	static uint32 serial_prime_out_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_PRIME_OUT), 0};
456	<	static uint32 serial_control_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_CONTROL), 0};
457	<	static uint32 serial_status_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_STATUS), 0};
458	<	static uint32 serial_close_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_CLOSE), 0};
459	<	#elif defined(__linux__)
460	<	#define SERIAL_TRAMPOLINES 1
461	<	static uint32 serial_nothing_tvect[2] = {(uint32)SerialNothing, 0};
462	<	static uint32 serial_open_tvect[2] = {(uint32)SerialOpen, 0};
463	<	static uint32 serial_prime_in_tvect[2] = {(uint32)SerialPrimeIn, 0};
464	<	static uint32 serial_prime_out_tvect[2] = {(uint32)SerialPrimeOut, 0};
465	<	static uint32 serial_control_tvect[2] = {(uint32)SerialControl, 0};
466	<	static uint32 serial_status_tvect[2] = {(uint32)SerialStatus, 0};
467	<	static uint32 serial_close_tvect[2] = {(uint32)SerialClose, 0};
468	<	#endif
509	>	static uint32 long_ptr;
510
511	<	static const uint32 ain_driver[] = {    // .AIn driver header
512	<	0x4d000000, 0x00000000,
513	<	0x00200040, 0x00600080,
514	<	0x00a0042e, 0x41496e00,
515	<	0x00000000, 0x00000000,
516	<	0xaafe0700, 0x00000000,
517	<	0x00000000, 0x00179822,
518	<	#ifdef SERIAL_TRAMPOLINES
519	<	0x00010004, (uint32)serial_nothing_tvect,
520	<	#else
521	<	0x00010004, (uint32)SerialNothing,
522	<	#endif
523	<	0x00000000, 0x00000000,
524	<	0xaafe0700, 0x00000000,
525	<	0x00000000, 0x00179822,
526	<	#ifdef SERIAL_TRAMPOLINES
527	<	0x00010004, (uint32)serial_prime_in_tvect,
528	<	#else
529	<	0x00010004, (uint32)SerialPrimeIn,
530	<	#endif
531	<	0x00000000, 0x00000000,
532	<	0xaafe0700, 0x00000000,
533	<	0x00000000, 0x00179822,
534	<	#ifdef SERIAL_TRAMPOLINES
535	<	0x00010004, (uint32)serial_control_tvect,
536	<	#else
537	<	0x00010004, (uint32)SerialControl,
538	<	#endif
539	<	0x00000000, 0x00000000,
540	<	0xaafe0700, 0x00000000,
541	<	0x00000000, 0x00179822,
542	<	#ifdef SERIAL_TRAMPOLINES
543	<	0x00010004, (uint32)serial_status_tvect,
544	<	#else
545	<	0x00010004, (uint32)SerialStatus,
546	<	#endif
547	<	0x00000000, 0x00000000,
548	<	0xaafe0700, 0x00000000,
549	<	0x00000000, 0x00179822,
550	<	#ifdef SERIAL_TRAMPOLINES
510	<	0x00010004, (uint32)serial_nothing_tvect,
511	<	#else
512	<	0x00010004, (uint32)SerialNothing,
513	<	#endif
514	<	0x00000000, 0x00000000,
511	>	static void SetLongBase(uint32 addr)
512	>	{
513	>	long_ptr = addr;
514	>	}
515	>
516	>	static void Long(uint32 value)
517	>	{
518	>	WriteMacInt32(long_ptr, value);
519	>	long_ptr += 4;
520	>	}
521	>
522	>	static void gen_ain_driver(uintptr addr)
523	>	{
524	>	SetLongBase(addr);
525	>
526	>	// .AIn driver header
527	>	Long(0x4d000000); Long(0x00000000);
528	>	Long(0x00200040); Long(0x00600080);
529	>	Long(0x00a0042e); Long(0x41496e00);
530	>	Long(0x00000000); Long(0x00000000);
531	>	Long(0xaafe0700); Long(0x00000000);
532	>	Long(0x00000000); Long(0x00179822);
533	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
534	>	Long(0x00000000); Long(0x00000000);
535	>	Long(0xaafe0700); Long(0x00000000);
536	>	Long(0x00000000); Long(0x00179822);
537	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_IN));
538	>	Long(0x00000000); Long(0x00000000);
539	>	Long(0xaafe0700); Long(0x00000000);
540	>	Long(0x00000000); Long(0x00179822);
541	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
542	>	Long(0x00000000); Long(0x00000000);
543	>	Long(0xaafe0700); Long(0x00000000);
544	>	Long(0x00000000); Long(0x00179822);
545	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
546	>	Long(0x00000000); Long(0x00000000);
547	>	Long(0xaafe0700); Long(0x00000000);
548	>	Long(0x00000000); Long(0x00179822);
549	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
550	>	Long(0x00000000); Long(0x00000000);
551		};
552
553	<	static const uint32 aout_driver[] = {   // .AOut driver header
554	<	0x4d000000, 0x00000000,
555	<	0x00200040, 0x00600080,
556	<	0x00a0052e, 0x414f7574,
557	<	0x00000000, 0x00000000,
558	<	0xaafe0700, 0x00000000,
559	<	0x00000000, 0x00179822,
560	<	#ifdef SERIAL_TRAMPOLINES
561	<	0x00010004, (uint32)serial_open_tvect,
562	<	#else
563	<	0x00010004, (uint32)SerialOpen,
564	<	#endif
565	<	0x00000000, 0x00000000,
566	<	0xaafe0700, 0x00000000,
567	<	0x00000000, 0x00179822,
568	<	#ifdef SERIAL_TRAMPOLINES
569	<	0x00010004, (uint32)serial_prime_out_tvect,
570	<	#else
571	<	0x00010004, (uint32)SerialPrimeOut,
572	<	#endif
573	<	0x00000000, 0x00000000,
574	<	0xaafe0700, 0x00000000,
575	<	0x00000000, 0x00179822,
576	<	#ifdef SERIAL_TRAMPOLINES
577	<	0x00010004, (uint32)serial_control_tvect,
578	<	#else
579	<	0x00010004, (uint32)SerialControl,
580	<	#endif
581	<	0x00000000, 0x00000000,
546	<	0xaafe0700, 0x00000000,
547	<	0x00000000, 0x00179822,
548	<	#ifdef SERIAL_TRAMPOLINES
549	<	0x00010004, (uint32)serial_status_tvect,
550	<	#else
551	<	0x00010004, (uint32)SerialStatus,
552	<	#endif
553	<	0x00000000, 0x00000000,
554	<	0xaafe0700, 0x00000000,
555	<	0x00000000, 0x00179822,
556	<	#ifdef SERIAL_TRAMPOLINES
557	<	0x00010004, (uint32)serial_close_tvect,
558	<	#else
559	<	0x00010004, (uint32)SerialClose,
560	<	#endif
561	<	0x00000000, 0x00000000,
553	>	static void gen_aout_driver(uintptr addr)
554	>	{
555	>	SetLongBase(addr);
556	>
557	>	// .AOut driver header
558	>	Long(0x4d000000); Long(0x00000000);
559	>	Long(0x00200040); Long(0x00600080);
560	>	Long(0x00a0052e); Long(0x414f7574);
561	>	Long(0x00000000); Long(0x00000000);
562	>	Long(0xaafe0700); Long(0x00000000);
563	>	Long(0x00000000); Long(0x00179822);
564	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_OPEN));
565	>	Long(0x00000000); Long(0x00000000);
566	>	Long(0xaafe0700); Long(0x00000000);
567	>	Long(0x00000000); Long(0x00179822);
568	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_OUT));
569	>	Long(0x00000000); Long(0x00000000);
570	>	Long(0xaafe0700); Long(0x00000000);
571	>	Long(0x00000000); Long(0x00179822);
572	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
573	>	Long(0x00000000); Long(0x00000000);
574	>	Long(0xaafe0700); Long(0x00000000);
575	>	Long(0x00000000); Long(0x00179822);
576	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
577	>	Long(0x00000000); Long(0x00000000);
578	>	Long(0xaafe0700); Long(0x00000000);
579	>	Long(0x00000000); Long(0x00179822);
580	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CLOSE));
581	>	Long(0x00000000); Long(0x00000000);
582		};
583
584	<	static const uint32 bin_driver[] = {    // .BIn driver header
585	<	0x4d000000, 0x00000000,
586	<	0x00200040, 0x00600080,
587	<	0x00a0042e, 0x42496e00,
588	<	0x00000000, 0x00000000,
589	<	0xaafe0700, 0x00000000,
590	<	0x00000000, 0x00179822,
591	<	#ifdef SERIAL_TRAMPOLINES
592	<	0x00010004, (uint32)serial_nothing_tvect,
593	<	#else
594	<	0x00010004, (uint32)SerialNothing,
595	<	#endif
596	<	0x00000000, 0x00000000,
597	<	0xaafe0700, 0x00000000,
598	<	0x00000000, 0x00179822,
599	<	#ifdef SERIAL_TRAMPOLINES
600	<	0x00010004, (uint32)serial_prime_in_tvect,
601	<	#else
602	<	0x00010004, (uint32)SerialPrimeIn,
603	<	#endif
604	<	0x00000000, 0x00000000,
605	<	0xaafe0700, 0x00000000,
606	<	0x00000000, 0x00179822,
607	<	#ifdef SERIAL_TRAMPOLINES
608	<	0x00010004, (uint32)serial_control_tvect,
609	<	#else
610	<	0x00010004, (uint32)SerialControl,
611	<	#endif
612	<	0x00000000, 0x00000000,
593	<	0xaafe0700, 0x00000000,
594	<	0x00000000, 0x00179822,
595	<	#ifdef SERIAL_TRAMPOLINES
596	<	0x00010004, (uint32)serial_status_tvect,
597	<	#else
598	<	0x00010004, (uint32)SerialStatus,
599	<	#endif
600	<	0x00000000, 0x00000000,
601	<	0xaafe0700, 0x00000000,
602	<	0x00000000, 0x00179822,
603	<	#ifdef SERIAL_TRAMPOLINES
604	<	0x00010004, (uint32)serial_nothing_tvect,
605	<	#else
606	<	0x00010004, (uint32)SerialNothing,
607	<	#endif
608	<	0x00000000, 0x00000000,
584	>	static void gen_bin_driver(uintptr addr)
585	>	{
586	>	SetLongBase(addr);
587	>
588	>	// .BIn driver header
589	>	Long(0x4d000000); Long(0x00000000);
590	>	Long(0x00200040); Long(0x00600080);
591	>	Long(0x00a0042e); Long(0x42496e00);
592	>	Long(0x00000000); Long(0x00000000);
593	>	Long(0xaafe0700); Long(0x00000000);
594	>	Long(0x00000000); Long(0x00179822);
595	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
596	>	Long(0x00000000); Long(0x00000000);
597	>	Long(0xaafe0700); Long(0x00000000);
598	>	Long(0x00000000); Long(0x00179822);
599	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_IN));
600	>	Long(0x00000000); Long(0x00000000);
601	>	Long(0xaafe0700); Long(0x00000000);
602	>	Long(0x00000000); Long(0x00179822);
603	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
604	>	Long(0x00000000); Long(0x00000000);
605	>	Long(0xaafe0700); Long(0x00000000);
606	>	Long(0x00000000); Long(0x00179822);
607	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
608	>	Long(0x00000000); Long(0x00000000);
609	>	Long(0xaafe0700); Long(0x00000000);
610	>	Long(0x00000000); Long(0x00179822);
611	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
612	>	Long(0x00000000); Long(0x00000000);
613		};
614
615	<	static const uint32 bout_driver[] = {   // .BOut driver header
616	<	0x4d000000, 0x00000000,
617	<	0x00200040, 0x00600080,
618	<	0x00a0052e, 0x424f7574,
619	<	0x00000000, 0x00000000,
620	<	0xaafe0700, 0x00000000,
621	<	0x00000000, 0x00179822,
622	<	#ifdef SERIAL_TRAMPOLINES
623	<	0x00010004, (uint32)serial_open_tvect,
624	<	#else
625	<	0x00010004, (uint32)SerialOpen,
626	<	#endif
627	<	0x00000000, 0x00000000,
628	<	0xaafe0700, 0x00000000,
629	<	0x00000000, 0x00179822,
630	<	#ifdef SERIAL_TRAMPOLINES
631	<	0x00010004, (uint32)serial_prime_out_tvect,
632	<	#else
633	<	0x00010004, (uint32)SerialPrimeOut,
634	<	#endif
635	<	0x00000000, 0x00000000,
636	<	0xaafe0700, 0x00000000,
637	<	0x00000000, 0x00179822,
638	<	#ifdef SERIAL_TRAMPOLINES
639	<	0x00010004, (uint32)serial_control_tvect,
640	<	#else
641	<	0x00010004, (uint32)SerialControl,
642	<	#endif
643	<	0x00000000, 0x00000000,
640	<	0xaafe0700, 0x00000000,
641	<	0x00000000, 0x00179822,
642	<	#ifdef SERIAL_TRAMPOLINES
643	<	0x00010004, (uint32)serial_status_tvect,
644	<	#else
645	<	0x00010004, (uint32)SerialStatus,
646	<	#endif
647	<	0x00000000, 0x00000000,
648	<	0xaafe0700, 0x00000000,
649	<	0x00000000, 0x00179822,
650	<	#ifdef SERIAL_TRAMPOLINES
651	<	0x00010004, (uint32)serial_close_tvect,
652	<	#else
653	<	0x00010004, (uint32)SerialClose,
654	<	#endif
655	<	0x00000000, 0x00000000,
615	>	static void gen_bout_driver(uintptr addr)
616	>	{
617	>	SetLongBase(addr);
618	>
619	>	// .BOut driver header
620	>	Long(0x4d000000); Long(0x00000000);
621	>	Long(0x00200040); Long(0x00600080);
622	>	Long(0x00a0052e); Long(0x424f7574);
623	>	Long(0x00000000); Long(0x00000000);
624	>	Long(0xaafe0700); Long(0x00000000);
625	>	Long(0x00000000); Long(0x00179822);
626	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_OPEN));
627	>	Long(0x00000000); Long(0x00000000);
628	>	Long(0xaafe0700); Long(0x00000000);
629	>	Long(0x00000000); Long(0x00179822);
630	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_OUT));
631	>	Long(0x00000000); Long(0x00000000);
632	>	Long(0xaafe0700); Long(0x00000000);
633	>	Long(0x00000000); Long(0x00179822);
634	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
635	>	Long(0x00000000); Long(0x00000000);
636	>	Long(0xaafe0700); Long(0x00000000);
637	>	Long(0x00000000); Long(0x00179822);
638	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
639	>	Long(0x00000000); Long(0x00000000);
640	>	Long(0xaafe0700); Long(0x00000000);
641	>	Long(0x00000000); Long(0x00179822);
642	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CLOSE));
643	>	Long(0x00000000); Long(0x00000000);
644		};
645
646		static const uint8 adbop_patch[] = {    // Call ADBOp() completion procedure
#	Line 679 | Line 667 | static const uint8 adbop_patch[] = {   //
667
668
669		/*
670	+	*  Copy PowerPC code to ROM image and reverse bytes if necessary
671	+	*/
672	+
673	+	static inline void memcpy_powerpc_code(void *dst, const void *src, size_t len)
674	+	{
675	+	#ifdef WORDS_BIGENDIAN
676	+	(void)memcpy(dst, src, len);
677	+	#else
678	+	uint32 *d = (uint32 *)dst;
679	+	uint32 *s = (uint32 *)src;
680	+	for (int i = 0; i < len/4; i++)
681	+	d[i] = htonl(s[i]);
682	+	#endif
683	+	}
684	+
685	+
686	+	/*
687		*  Install ROM patches (RAMBase and KernelDataAddr must be set)
688		*/
689
#	Line 701 | Line 706 | bool PatchROM(void)
706		ROMType = ROMTYPE_ZANZIBAR;
707		else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Gazelle", 12))
708		ROMType = ROMTYPE_GAZELLE;
709	+	else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Gossamer", 13))
710	+	ROMType = ROMTYPE_GOSSAMER;
711		else if (!memcmp((void *)(ROM_BASE + 0x30d064), "NewWorld", 8))
712		ROMType = ROMTYPE_NEWWORLD;
713		else
714		return false;
715
716	+	// Check that other ROM addresses point to really free regions
717	+	if (!check_rom_patch_space(CHECK_LOAD_PATCH_SPACE, 0x40))
718	+	return false;
719	+	if (!check_rom_patch_space(PUT_SCRAP_PATCH_SPACE, 0x40))
720	+	return false;
721	+	if (!check_rom_patch_space(GET_SCRAP_PATCH_SPACE, 0x40))
722	+	return false;
723	+	if (!check_rom_patch_space(ADDR_MAP_PATCH_SPACE - 10 * 4, 0x100))
724	+	return false;
725	+
726		// Apply patches
727		if (!patch_nanokernel_boot()) return false;
728		if (!patch_68k_emul()) return false;
#	Line 738 | Line 755 | bool PatchROM(void)
755		static bool patch_nanokernel_boot(void)
756		{
757		uint32 *lp;
758	+	uint32 base, loc;
759
760		// ROM boot structure patches
761		lp = (uint32 *)(ROM_BASE + 0x30d000);
#	Line 750 | Line 768 | static bool patch_nanokernel_boot(void)
768		lp[0xfd8 >> 2] = htonl(ROM_BASE + 0x2a);                // 68k reset vector
769
770		// Skip SR/BAT/SDR init
771	<	if (ROMType == ROMTYPE_GAZELLE || ROMType == ROMTYPE_NEWWORLD) {
772	<	lp = (uint32 *)(ROM_BASE + 0x310000);
771	>	loc = 0x310000;
772	>	if (ROMType == ROMTYPE_GAZELLE || ROMType == ROMTYPE_GOSSAMER || ROMType == ROMTYPE_NEWWORLD) {
773	>	lp = (uint32 *)(ROM_BASE + loc);
774		*lp++ = htonl(POWERPC_NOP);
775		*lp = htonl(0x38000000);
776		}
777	<	static const uint32 sr_init_loc[] = {0x3101b0, 0x3101b0, 0x3101b0, 0x3101ec, 0x310200};
778	<	lp = (uint32 *)(ROM_BASE + 0x310008);
779	<	*lp = htonl(0x48000000 | (sr_init_loc[ROMType] - 8) & 0xffff);  // b            ROM_BASE+0x3101b0
780	<	lp = (uint32 *)(ROM_BASE + sr_init_loc[ROMType]);
777	>	static const uint8 sr_init_dat[] = {0x35, 0x4a, 0xff, 0xfc, 0x7d, 0x86, 0x50, 0x2e};
778	>	if ((base = find_rom_data(0x3101b0, 0x3105b0, sr_init_dat, sizeof(sr_init_dat))) == 0) return false;
779	>	D(bug("sr_init %08lx\n", base));
780	>	lp = (uint32 *)(ROM_BASE + loc + 8);
781	>	*lp = htonl(0x48000000 | ((base - loc - 8) & 0x3fffffc));       // b            ROM_BASE+0x3101b0
782	>	lp = (uint32 *)(ROM_BASE + base);
783		*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);            // lwz  r1,(pointer to Kernel Data)
784		*lp++ = htonl(0x3da0dead);              // lis  r13,0xdead      (start of kernel memory)
785		*lp++ = htonl(0x3dc00010);              // lis  r14,0x0010      (size of page table)
786		*lp = htonl(0x3de00010);                // lis  r15,0x0010      (size of kernel memory)
787
788		// Don't read PVR
789	<	static const uint32 pvr_loc[] = {0x3103b0, 0x3103b4, 0x3103b4, 0x310400, 0x310438};
790	<	lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
789	>	static const uint8 pvr_read_dat[] = {0x7d, 0x9f, 0x42, 0xa6};
790	>	if ((base = find_rom_data(0x3103b0, 0x3108b0, pvr_read_dat, sizeof(pvr_read_dat))) == 0) return false;
791	>	D(bug("pvr_read %08lx\n", base));
792	>	lp = (uint32 *)(ROM_BASE + base);
793		*lp = htonl(0x81800000 + XLM_PVR);      // lwz  r12,(theoretical PVR)
794
795		// Set CPU specific data (even if ROM doesn't have support for that CPU)
773	–	lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
796		if (ntohl(lp[6]) != 0x2c0c0001)
797		return false;
798		uint32 ofs = ntohl(lp[7]) & 0xffff;
799		D(bug("ofs %08lx\n", ofs));
800		lp[8] = htonl((ntohl(lp[8]) & 0xffff) | 0x48000000);    // beq -> b
801	<	uint32 loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
801	>	loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
802		D(bug("loc %08lx\n", loc));
803		lp = (uint32 *)(ROM_BASE + ofs + 0x310000);
804		switch (PVR >> 16) {
#	Line 891 | Line 913 | static bool patch_nanokernel_boot(void)
913		}
914
915		// Don't set SPRG3, don't test MQ
916	<	lp = (uint32 *)(ROM_BASE + loc + 0x20);
917	<	*lp++ = htonl(POWERPC_NOP);
918	<	lp++;
919	<	*lp++ = htonl(POWERPC_NOP);
920	<	lp++;
921	<	*lp = htonl(POWERPC_NOP);
916	>	static const uint8 sprg3_mq_dat[] = {0x7d, 0x13, 0x43, 0xa6, 0x3d, 0x00, 0x00, 0x04, 0x7d, 0x00, 0x03, 0xa6, 0x39, 0x00, 0x00, 0x00, 0x7d, 0x00, 0x02, 0xa6};
917	>	if ((base = find_rom_data(loc + 0x20, loc + 0x60, sprg3_mq_dat, sizeof(sprg3_mq_dat))) == 0) return false;
918	>	D(bug("sprg3/mq %08lx\n", base));
919	>	lp = (uint32 *)(ROM_BASE + base);
920	>	lp[0] = htonl(POWERPC_NOP);
921	>	lp[2] = htonl(POWERPC_NOP);
922	>	lp[4] = htonl(POWERPC_NOP);
923
924		// Don't read MSR
925	<	lp = (uint32 *)(ROM_BASE + loc + 0x40);
925	>	static const uint8 msr_dat[] = {0x7d, 0xc0, 0x00, 0xa6};
926	>	if ((base = find_rom_data(loc + 0x40, loc + 0x80, msr_dat, sizeof(msr_dat))) == 0) return false;
927	>	D(bug("msr %08lx\n", base));
928	>	lp = (uint32 *)(ROM_BASE + base);
929		*lp = htonl(0x39c00000);                // li   r14,0
930
931		// Don't write to DEC
#	Line 909 | Line 935 | static bool patch_nanokernel_boot(void)
935		D(bug("loc %08lx\n", loc));
936
937		// Don't set SPRG3
938	<	lp = (uint32 *)(ROM_BASE + loc + 0x2c);
938	>	static const uint8 sprg3_dat[] = {0x39, 0x21, 0x03, 0x60, 0x7d, 0x33, 0x43, 0xa6, 0x39, 0x01, 0x04, 0x20};
939	>	if ((base = find_rom_data(0x310000, 0x314000, sprg3_dat, sizeof(sprg3_dat))) == 0) return false;
940	>	D(bug("sprg3 %08lx\n", base + 4));
941	>	lp = (uint32 *)(ROM_BASE + base + 4);
942		*lp = htonl(POWERPC_NOP);
943
944		// Don't read PVR
945	<	static const uint32 pvr_ofs[] = {0x138, 0x138, 0x138, 0x140, 0x148};
946	<	lp = (uint32 *)(ROM_BASE + loc + pvr_ofs[ROMType]);
945	>	static const uint8 pvr_read2_dat[] = {0x7e, 0xff, 0x42, 0xa6, 0x56, 0xf7, 0x84, 0x3e};
946	>	if ((base = find_rom_data(0x310000, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) == 0) return false;
947	>	D(bug("pvr_read2 %08lx\n", base));
948	>	lp = (uint32 *)(ROM_BASE + base);
949		*lp = htonl(0x82e00000 + XLM_PVR);              // lwz  r23,(theoretical PVR)
950	<	lp = (uint32 *)(ROM_BASE + loc + 0x170);
951	<	if (ntohl(*lp) == 0x7eff42a6)   // NewWorld ROM
950	>	if ((base = find_rom_data(base + 4, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) != 0) {
951	>	D(bug("pvr_read2 %08lx\n", base));
952	>	lp = (uint32 *)(ROM_BASE + base);
953		*lp = htonl(0x82e00000 + XLM_PVR);      // lwz  r23,(theoretical PVR)
954	<	lp = (uint32 *)(ROM_BASE + 0x313134);
955	<	if (ntohl(*lp) == 0x7e5f42a6)
956	<	*lp = htonl(0x82400000 + XLM_PVR);      // lwz  r18,(theoretical PVR)
957	<	lp = (uint32 *)(ROM_BASE + 0x3131f4);
958	<	if (ntohl(*lp) == 0x7e5f42a6)   // NewWorld ROM
954	>	}
955	>	static const uint8 pvr_read3_dat[] = {0x7e, 0x5f, 0x42, 0xa6, 0x56, 0x52, 0x84, 0x3e};
956	>	if ((base = find_rom_data(0x310000, 0x320000, pvr_read3_dat, sizeof(pvr_read3_dat))) != 0) {
957	>	D(bug("pvr_read3 %08lx\n", base));
958	>	lp = (uint32 *)(ROM_BASE + base);
959		*lp = htonl(0x82400000 + XLM_PVR);      // lwz  r18,(theoretical PVR)
960	<	lp = (uint32 *)(ROM_BASE + 0x314600);
961	<	if (ntohl(*lp) == 0x7d3f42a6)
960	>	}
961	>	static const uint8 pvr_read4_dat[] = {0x7d, 0x3f, 0x42, 0xa6, 0x55, 0x29, 0x84, 0x3e};
962	>	if ((base = find_rom_data(0x310000, 0x320000, pvr_read4_dat, sizeof(pvr_read4_dat))) != 0) {
963	>	D(bug("pvr_read4 %08lx\n", base));
964	>	lp = (uint32 *)(ROM_BASE + base);
965		*lp = htonl(0x81200000 + XLM_PVR);      // lzw  r9,(theoritical PVR)
966	+	}
967
968		// Don't read SDR1
969	<	static const uint32 sdr1_ofs[] = {0x174, 0x174, 0x174, 0x17c, 0x19c};
970	<	lp = (uint32 *)(ROM_BASE + loc + sdr1_ofs[ROMType]);
969	>	static const uint8 sdr1_read_dat[] = {0x7d, 0x19, 0x02, 0xa6, 0x55, 0x16, 0x81, 0xde};
970	>	if ((base = find_rom_data(0x310000, 0x320000, sdr1_read_dat, sizeof(sdr1_read_dat))) == 0) return false;
971	>	D(bug("sdr1_read %08lx\n", base));
972	>	lp = (uint32 *)(ROM_BASE + base);
973		*lp++ = htonl(0x3d00dead);              // lis  r8,0xdead               (pointer to page table)
974		*lp++ = htonl(0x3ec0001f);              // lis  r22,0x001f      (size of page table)
975		*lp = htonl(POWERPC_NOP);
976
977	<	// Don't clear page table
978	<	static const uint32 pgtb_ofs[] = {0x198, 0x198, 0x198, 0x1a0, 0x1c4};
979	<	lp = (uint32 *)(ROM_BASE + loc + pgtb_ofs[ROMType]);
977	>	// Don't clear page table, don't invalidate TLB
978	>	static const uint8 pgtb_clear_dat[] = {0x36, 0xd6, 0xff, 0xfc, 0x7e, 0xe8, 0xb1, 0x2e, 0x41, 0x81, 0xff, 0xf8};
979	>	if ((base = find_rom_data(0x310000, 0x320000, pgtb_clear_dat, sizeof(pgtb_clear_dat))) == 0) return false;
980	>	D(bug("pgtb_clear %08lx\n", base + 4));
981	>	lp = (uint32 *)(ROM_BASE + base + 4);
982		*lp = htonl(POWERPC_NOP);
983	<
984	<	// Don't invalidate TLB
945	<	static const uint32 tlb_ofs[] = {0x1a0, 0x1a0, 0x1a0, 0x1a8, 0x1cc};
946	<	lp = (uint32 *)(ROM_BASE + loc + tlb_ofs[ROMType]);
983	>	D(bug("tblie %08lx\n", base + 12));
984	>	lp = (uint32 *)(ROM_BASE + base + 12);
985		*lp = htonl(POWERPC_NOP);
986
987		// Don't create RAM descriptor table
988	<	static const uint32 desc_ofs[] = {0x350, 0x350, 0x350, 0x358, 0x37c};
989	<	lp = (uint32 *)(ROM_BASE + loc + desc_ofs[ROMType]);
988	>	static const uint8 desc_create_dat[] = {0x97, 0xfd, 0x00, 0x04, 0x3b, 0xff, 0x10, 0x00, 0x4b, 0xff, 0xff, 0xdc};
989	>	if ((base = find_rom_data(0x310000, 0x320000, desc_create_dat, sizeof(desc_create_dat))) == 0) return false;
990	>	D(bug("desc_create %08lx\n", base))
991	>	lp = (uint32 *)(ROM_BASE + base);
992		*lp = htonl(POWERPC_NOP);
993
994		// Don't load SRs and BATs
995	<	static const uint32 sr_ofs[] = {0x3d8, 0x3d8, 0x3d8, 0x3e0, 0x404};
996	<	lp = (uint32 *)(ROM_BASE + loc + sr_ofs[ROMType]);
995	>	static const uint8 sr_load[] = {0x7c, 0x00, 0x04, 0xac, 0x83, 0x9d, 0x00, 0x00, 0x93, 0x81, 0x05, 0xe8};
996	>	if ((loc = find_rom_data(0x310000, 0x320000, sr_load, sizeof(sr_load))) == 0) return false;
997	>	static const uint8 sr_load_caller[] = {0x3e, 0xd6, 0xff, 0xff, 0x41, 0x81, 0xff, 0xdc, 0xb2, 0xc8, 0x00, 0x02};
998	>	if ((base = find_rom_data(0x310000, 0x320000, sr_load_caller, sizeof(sr_load_caller))) == 0) return false;
999	>	if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false;
1000	>	D(bug("sr_load %08lx, called from %08lx\n", loc, base));
1001	>	lp = (uint32 *)(ROM_BASE + base);
1002		*lp = htonl(POWERPC_NOP);
1003
1004		// Don't mess with SRs
1005	<	static const uint32 sr2_ofs[] = {0x312118, 0x312118, 0x312118, 0x312118, 0x3121b4};
1006	<	lp = (uint32 *)(ROM_BASE + sr2_ofs[ROMType]);
1005	>	static const uint8 sr_load2_dat[] = {0x83, 0xa1, 0x05, 0xe8, 0x57, 0x7c, 0x3e, 0x78, 0x7f, 0xbd, 0xe0, 0x2e};
1006	>	if ((base = find_rom_data(0x310000, 0x320000, sr_load2_dat, sizeof(sr_load2_dat))) == 0) return false;
1007	>	D(bug("sr_load2 %08lx\n", base));
1008	>	lp = (uint32 *)(ROM_BASE + base);
1009		*lp = htonl(POWERPC_BLR);
1010
1011		// Don't check performance monitor
1012	<	static const uint32 pm_ofs[] = {0x313148, 0x313148, 0x313148, 0x313148, 0x313218};
1013	<	lp = (uint32 *)(ROM_BASE + pm_ofs[ROMType]);
1014	<	while (ntohl(*lp) != 0x7e58eba6) lp++;
1015	<	*lp++ = htonl(POWERPC_NOP);
1016	<	while (ntohl(*lp) != 0x7e78eaa6) lp++;
1017	<	*lp++ = htonl(POWERPC_NOP);
1018	<	while (ntohl(*lp) != 0x7e59eba6) lp++;
1019	<	*lp++ = htonl(POWERPC_NOP);
1020	<	while (ntohl(*lp) != 0x7e79eaa6) lp++;
1021	<	*lp++ = htonl(POWERPC_NOP);
1022	<	while (ntohl(*lp) != 0x7e5aeba6) lp++;
1023	<	*lp++ = htonl(POWERPC_NOP);
1024	<	while (ntohl(*lp) != 0x7e7aeaa6) lp++;
1025	<	*lp++ = htonl(POWERPC_NOP);
1026	<	while (ntohl(*lp) != 0x7e5beba6) lp++;
1027	<	*lp++ = htonl(POWERPC_NOP);
1028	<	while (ntohl(*lp) != 0x7e7beaa6) lp++;
1029	<	*lp++ = htonl(POWERPC_NOP);
1030	<	while (ntohl(*lp) != 0x7e5feba6) lp++;
1031	<	*lp++ = htonl(POWERPC_NOP);
1032	<	while (ntohl(*lp) != 0x7e7feaa6) lp++;
1033	<	*lp++ = htonl(POWERPC_NOP);
1034	<	while (ntohl(*lp) != 0x7e5ceba6) lp++;
1035	<	*lp++ = htonl(POWERPC_NOP);
989	<	while (ntohl(*lp) != 0x7e7ceaa6) lp++;
990	<	*lp++ = htonl(POWERPC_NOP);
991	<	while (ntohl(*lp) != 0x7e5deba6) lp++;
992	<	*lp++ = htonl(POWERPC_NOP);
993	<	while (ntohl(*lp) != 0x7e7deaa6) lp++;
994	<	*lp++ = htonl(POWERPC_NOP);
995	<	while (ntohl(*lp) != 0x7e5eeba6) lp++;
996	<	*lp++ = htonl(POWERPC_NOP);
997	<	while (ntohl(*lp) != 0x7e7eeaa6) lp++;
998	<	*lp++ = htonl(POWERPC_NOP);
1012	>	static const uint8 pm_check_dat[] = {0x7e, 0x58, 0xeb, 0xa6, 0x7e, 0x53, 0x90, 0xf8, 0x7e, 0x78, 0xea, 0xa6};
1013	>	if ((base = find_rom_data(0x310000, 0x320000, pm_check_dat, sizeof(pm_check_dat))) == 0) return false;
1014	>	D(bug("pm_check %08lx\n", base));
1015	>	lp = (uint32 *)(ROM_BASE + base);
1016	>
1017	>	static const int spr_check_list[] = {
1018	>	952 /* mmcr0 */, 953 /* pmc1 */, 954 /* pmc2 */, 955 /* sia */,
1019	>	956 /* mmcr1 */, 957 /* pmc3 */, 958 /* pmc4 */, 959 /* sda */
1020	>	};
1021	>
1022	>	for (int i = 0; i < sizeof(spr_check_list)/sizeof(spr_check_list[0]); i++) {
1023	>	int spr = spr_check_list[i];
1024	>	uint32 mtspr = 0x7e4003a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6);
1025	>	uint32 mfspr = 0x7e6002a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6);
1026	>	for (int ofs = 0; ofs < 64; ofs++) {
1027	>	if (ntohl(lp[ofs]) == mtspr) {
1028	>	if (ntohl(lp[ofs + 2]) != mfspr)
1029	>	return false;
1030	>	D(bug("  SPR%d %08lx\n", spr, base + 4*ofs));
1031	>	lp[ofs] = htonl(POWERPC_NOP);
1032	>	lp[ofs + 2] = htonl(POWERPC_NOP);
1033	>	}
1034	>	}
1035	>	}
1036
1037		// Jump to 68k emulator
1038	<	static const uint32 jump68k_ofs[] = {0x40c, 0x40c, 0x40c, 0x414, 0x438};
1039	<	lp = (uint32 *)(ROM_BASE + loc + jump68k_ofs[ROMType]);
1038	>	static const uint8 jump68k_dat[] = {0x7d, 0x92, 0x43, 0xa6, 0x7d, 0x5a, 0x03, 0xa6, 0x7d, 0x7b, 0x03, 0xa6};
1039	>	if ((loc = find_rom_data(0x310000, 0x320000, jump68k_dat, sizeof(jump68k_dat))) == 0) return false;
1040	>	static const uint8 jump68k_caller_dat[] = {0x85, 0x13, 0x00, 0x08, 0x56, 0xbf, 0x50, 0x3e, 0x63, 0xff, 0x0c, 0x00};
1041	>	if ((base = find_rom_data(0x310000, 0x320000, jump68k_caller_dat, sizeof(jump68k_caller_dat))) == 0) return false;
1042	>	if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false;
1043	>	D(bug("jump68k %08lx, called from %08lx\n", loc, base));
1044	>	lp = (uint32 *)(ROM_BASE + base);
1045		*lp++ = htonl(0x80610634);              // lwz  r3,0x0634(r1)   (pointer to Emulator Data)
1046		*lp++ = htonl(0x8081119c);              // lwz  r4,0x119c(r1)   (pointer to opcode table)
1047		*lp++ = htonl(0x80011184);              // lwz  r0,0x1184(r1)   (pointer to emulator init routine)
#	Line 1019 | Line 1061 | static bool patch_68k_emul(void)
1061		uint32 base;
1062
1063		// Overwrite twi instructions
1064	<	static const uint32 twi_loc[] = {0x36e680, 0x36e6c0, 0x36e6c0, 0x36e6c0, 0x36e740};
1065	<	base = twi_loc[ROMType];
1064	>	static const uint8 twi_dat[] = {0x0f, 0xff, 0x00, 0x00, 0x0f, 0xff, 0x00, 0x01, 0x0f, 0xff, 0x00, 0x02};
1065	>	if ((base = find_rom_data(0x36e600, 0x36ea00, twi_dat, sizeof(twi_dat))) == 0) return false;
1066	>	D(bug("twi %08lx\n", base));
1067		lp = (uint32 *)(ROM_BASE + base);
1068		*lp++ = htonl(0x48000000 + 0x36f900 - base);            // b 0x36f900 (Emulator start)
1069		*lp++ = htonl(0x48000000 + 0x36fa00 - base - 4);        // b 0x36fa00 (Mixed mode)
#	Line 1080 | Line 1123 | static bool patch_68k_emul(void)
1123		lp = (uint32 *)(ROM_BASE + 0x36f900);
1124		*lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1125		#if EMULATED_PPC
1126	<	*lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1126	>	*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1127		#else
1128		*lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1129		*lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
#	Line 1114 | Line 1157 | static bool patch_68k_emul(void)
1157		lp = (uint32 *)(ROM_BASE + 0x36fa00);
1158		*lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1159		#if EMULATED_PPC
1160	<	*lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1160	>	*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1161		#else
1162		*lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1163		*lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
#	Line 1148 | Line 1191 | static bool patch_68k_emul(void)
1191		lp = (uint32 *)(ROM_BASE + 0x36fb00);
1192		*lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1193		#if EMULATED_PPC
1194	<	*lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1194	>	*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1195		#else
1196		*lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1197		*lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
#	Line 1182 | Line 1225 | static bool patch_68k_emul(void)
1225		lp = (uint32 *)(ROM_BASE + 0x36fc00);
1226		*lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1227		#if EMULATED_PPC
1228	<	*lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1228	>	*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1229		#else
1230		*lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1231		*lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
#	Line 1240 | Line 1283 | dr_found:
1283		static bool patch_nanokernel(void)
1284		{
1285		uint32 *lp;
1286	+	uint32 base, loc;
1287
1288		// Patch Mixed Mode trap
1289	<	lp = (uint32 *)(ROM_BASE + 0x313c90);   // Don't translate virtual->physical
1290	<	while (ntohl(*lp) != 0x3ba10320) lp++;
1291	<	lp++;
1292	<	*lp++ = htonl(0x7f7fdb78);                                      // mr           r31,r27
1293	<	lp++;
1294	<	*lp = htonl(POWERPC_NOP);
1295	<
1296	<	lp = (uint32 *)(ROM_BASE + 0x313c3c);   // Don't activate PPC exception table
1297	<	while (ntohl(*lp) != 0x39010420) lp++;
1289	>	static const uint8 virt2phys_dat[] = {0x7d, 0x1b, 0x43, 0x78, 0x3b, 0xa1, 0x03, 0x20};
1290	>	if ((base = find_rom_data(0x313000, 0x314000, virt2phys_dat, sizeof(virt2phys_dat))) == 0) return false;
1291	>	D(bug("virt2phys %08lx\n", base + 8));
1292	>	lp = (uint32 *)(ROM_BASE + base + 8);   // Don't translate virtual->physical
1293	>	lp[0] = htonl(0x7f7fdb78);                                      // mr           r31,r27
1294	>	lp[2] = htonl(POWERPC_NOP);
1295	>
1296	>	static const uint8 ppc_excp_tbl_dat[] = {0x39, 0x01, 0x04, 0x20, 0x7d, 0x13, 0x43, 0xa6};
1297	>	if ((base = find_rom_data(0x313000, 0x314000, ppc_excp_tbl_dat, sizeof(ppc_excp_tbl_dat))) == 0) return false;
1298	>	D(bug("ppc_excp_tbl %08lx\n", base));
1299	>	lp = (uint32 *)(ROM_BASE + base);               // Don't activate PPC exception table
1300		*lp++ = htonl(0x39000000 + MODE_NATIVE);        // li   r8,MODE_NATIVE
1301	<	*lp = htonl(0x91000000 + XLM_RUN_MODE); // stw  r8,XLM_RUN_MODE
1301	>	*lp = htonl(0x91000000 + XLM_RUN_MODE);         // stw  r8,XLM_RUN_MODE
1302
1303	<	lp = (uint32 *)(ROM_BASE + 0x312e88);   // Don't modify MSR to turn on FPU
1304	<	while (ntohl(*lp) != 0x556b04e2) lp++;
1305	<	lp -= 4;
1303	>	static const uint8 save_fpu_dat[] = {0x7d, 0x00, 0x00, 0xa6, 0x61, 0x08, 0x20, 0x00, 0x7d, 0x00, 0x01, 0x24};
1304	>	if ((base = find_rom_data(0x310000, 0x314000, save_fpu_dat, sizeof(save_fpu_dat))) == 0) return false;
1305	>	D(bug("save_fpu %08lx\n", base));
1306	>	lp = (uint32 *)(ROM_BASE + base);               // Don't modify MSR to turn on FPU
1307	>	if (ntohl(lp[4]) != 0x556b04e2) return false;
1308	>	loc = ROM_BASE + base;
1309	>	#if 1
1310	>	// FIXME: is that really intended?
1311		*lp++ = htonl(POWERPC_NOP);
1312		lp++;
1313		*lp++ = htonl(POWERPC_NOP);
1314		lp++;
1315		*lp = htonl(POWERPC_NOP);
1316	+	#else
1317	+	lp[0] = htonl(POWERPC_NOP);
1318	+	lp[1] = htonl(POWERPC_NOP);
1319	+	lp[2] = htonl(POWERPC_NOP);
1320	+	lp[3] = htonl(POWERPC_NOP);
1321	+	#endif
1322
1323	<	lp = (uint32 *)(ROM_BASE + 0x312b3c);   // Always save FPU state
1324	<	while (ntohl(*lp) != 0x81010668) lp++;
1325	<	lp--;
1323	>	static const uint8 save_fpu_caller_dat[] = {0x93, 0xa6, 0x01, 0xec, 0x93, 0xc6, 0x01, 0xf4, 0x93, 0xe6, 0x01, 0xfc, 0x40};
1324	>	if ((base = find_rom_data(0x310000, 0x314000, save_fpu_caller_dat, sizeof(save_fpu_caller_dat))) == 0) return false;
1325	>	D(bug("save_fpu_caller %08lx\n", base + 12));
1326	>	if (powerpc_branch_target(ROM_BASE + base + 12) != loc) return false;
1327	>	lp = (uint32 *)(ROM_BASE + base + 12);  // Always save FPU state
1328		*lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312e88
1329
1330	<	lp = (uint32 *)(ROM_BASE + 0x312b44);   // Don't read DEC
1331	<	while (ntohl(*lp) != 0x7ff602a6) lp++;
1332	<	*lp = htonl(0x3be00000);                                        // li   r31,0
1333	<
1334	<	lp = (uint32 *)(ROM_BASE + 0x312b50);   // Don't write DEC
1276	<	while (ntohl(*lp) != 0x7d1603a6) lp++;
1330	>	static const uint8 mdec_dat[] = {0x7f, 0xf6, 0x02, 0xa6, 0x2c, 0x08, 0x00, 0x00, 0x93, 0xe1, 0x06, 0x68, 0x7d, 0x16, 0x03, 0xa6};
1331	>	if ((base = find_rom_data(0x310000, 0x314000, mdec_dat, sizeof(mdec_dat))) == 0) return false;
1332	>	D(bug("mdec %08lx\n", base));
1333	>	lp = (uint32 *)(ROM_BASE + base);               // Don't modify DEC
1334	>	lp[0] = htonl(0x3be00000);                                      // li   r31,0
1335		#if 1
1336	<	*lp++ = htonl(POWERPC_NOP);
1337	<	*lp = htonl(POWERPC_NOP);
1336	>	lp[3] = htonl(POWERPC_NOP);
1337	>	lp[4] = htonl(POWERPC_NOP);
1338		#else
1339	<	*lp++ = htonl(0x39000040);                                      // li   r8,0x40
1340	<	*lp = htonl(0x990600e4);                                        // stb  r8,0xe4(r6)
1339	>	lp[3] = htonl(0x39000040);                                      // li   r8,0x40
1340	>	lp[4] = htonl(0x990600e4);                                      // stb  r8,0xe4(r6)
1341		#endif
1342
1343	<	lp = (uint32 *)(ROM_BASE + 0x312b9c);   // Always restore FPU state
1344	<	while (ntohl(*lp) != 0x7c00092d) lp++;
1345	<	lp--;
1343	>	static const uint8 restore_fpu_caller_dat[] = {0x81, 0x06, 0x00, 0xf4, 0x81, 0x46, 0x00, 0xfc, 0x7d, 0x09, 0x03, 0xa6, 0x40};
1344	>	if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller_dat, sizeof(restore_fpu_caller_dat))) == 0) return false;
1345	>	D(bug("restore_fpu_caller %08lx\n", base + 12));
1346	>	lp = (uint32 *)(ROM_BASE + base + 12);  // Always restore FPU state
1347		*lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312ddc
1348
1349	<	lp = (uint32 *)(ROM_BASE + 0x312a68);   // Don't activate 68k exception table
1350	<	while (ntohl(*lp) != 0x39010360) lp++;
1349	>	static const uint8 m68k_excp_tbl_dat[] = {0x81, 0x21, 0x06, 0x58, 0x39, 0x01, 0x03, 0x60, 0x7d, 0x13, 0x43, 0xa6};
1350	>	if ((base = find_rom_data(0x310000, 0x314000, m68k_excp_tbl_dat, sizeof(m68k_excp_tbl_dat))) == 0) return false;
1351	>	D(bug("m68k_excp %08lx\n", base + 4));
1352	>	lp = (uint32 *)(ROM_BASE + base + 4);   // Don't activate 68k exception table
1353		*lp++ = htonl(0x39000000 + MODE_68K);           // li   r8,MODE_68K
1354		*lp = htonl(0x91000000 + XLM_RUN_MODE);         // stw  r8,XLM_RUN_MODE
1355
1356		// Patch 68k emulator trap routine
1357	<	lp = (uint32 *)(ROM_BASE + 0x312994);   // Always restore FPU state
1358	<	while (ntohl(*lp) != 0x39260040) lp++;
1359	<	lp--;
1357	>	static const uint8 restore_fpu_caller2_dat[] = {0x81, 0x86, 0x00, 0x8c, 0x80, 0x66, 0x00, 0x94, 0x80, 0x86, 0x00, 0x9c, 0x40};
1358	>	if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller2_dat, sizeof(restore_fpu_caller2_dat))) == 0) return false;
1359	>	D(bug("restore_fpu_caller2 %08lx\n", base + 12));
1360	>	loc = powerpc_branch_target(ROM_BASE + base + 12) - ROM_BASE;
1361	>	lp = (uint32 *)(ROM_BASE + base + 12);  // Always restore FPU state
1362		*lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312dd4
1363
1364	<	lp = (uint32 *)(ROM_BASE + 0x312dd8);   // Don't modify MSR to turn on FPU
1365	<	while (ntohl(*lp) != 0x810600e4) lp++;
1366	<	lp--;
1364	>	static const uint8 restore_fpu_dat[] = {0x55, 0x68, 0x04, 0xa5, 0x4c, 0x82, 0x00, 0x20, 0x81, 0x06, 0x00, 0xe4};
1365	>	if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_dat, sizeof(restore_fpu_dat))) == 0) return false;
1366	>	D(bug("restore_fpu %08lx\n", base));
1367	>	if (base != loc) return false;
1368	>	lp = (uint32 *)(ROM_BASE + base + 4);   // Don't modify MSR to turn on FPU
1369		*lp++ = htonl(POWERPC_NOP);
1370		lp += 2;
1371		*lp++ = htonl(POWERPC_NOP);
#	Line 1310 | Line 1375 | static bool patch_nanokernel(void)
1375		*lp = htonl(POWERPC_NOP);
1376
1377		// Patch trap return routine
1378	<	lp = (uint32 *)(ROM_BASE + 0x312c20);
1379	<	while (ntohl(*lp) != 0x7d5a03a6) lp++;
1378	>	static const uint8 trap_return_dat[] = {0x80, 0xc1, 0x00, 0x18, 0x80, 0x21, 0x00, 0x04, 0x4c, 0x00, 0x00, 0x64};
1379	>	if ((base = find_rom_data(0x312000, 0x320000, trap_return_dat, sizeof(trap_return_dat))) == 0) return false;
1380	>	D(bug("trap_return %08lx\n", base + 8));
1381	>	lp = (uint32 *)(ROM_BASE + base + 8);   // Replace rfi
1382	>	*lp = htonl(POWERPC_BCTR);
1383	>
1384	>	while (ntohl(*lp) != 0x7d5a03a6) lp--;
1385		*lp++ = htonl(0x7d4903a6);                                      // mtctr        r10
1386		*lp++ = htonl(0x7daff120);                                      // mtcr r13
1387	<	*lp = htonl(0x48000000 + 0x8000 - (((uint32)lp - ROM_BASE) & 0xffff));  // b            ROM_BASE+0x318000
1388	<	uint32 xlp = ((uint32)(lp+1) - ROM_BASE) & 0xffff;
1319	<
1320	<	lp = (uint32 *)(ROM_BASE + 0x312c50);   // Replace rfi
1321	<	while (ntohl(*lp) != 0x4c000064) lp++;
1322	<	*lp = htonl(POWERPC_BCTR);
1387	>	*lp = htonl(0x48000000 + ((0x318000 - ((uint32)lp - ROM_BASE)) & 0x03fffffc));  // b            ROM_BASE+0x318000
1388	>	uint32 npc = (uint32)(lp + 1) - ROM_BASE;
1389
1390		lp = (uint32 *)(ROM_BASE + 0x318000);
1391		#if EMULATED_PPC
1392	<	*lp++ = POWERPC_NATIVE_OP(NATIVE_ENABLE_INTERRUPT);
1393	<	*lp = htonl(0x48000000 + ((xlp - 0x8004) & 0x03fffffc));        // b            ROM_BASE+0x312c2c
1392	>	*lp++ = htonl(NativeOpcode(NATIVE_ENABLE_INTERRUPT));
1393	>	*lp = htonl(0x48000000 + ((npc - 0x318004) & 0x03fffffc));      // b            ROM_BASE+0x312c2c
1394		#else
1395		*lp++ = htonl(0x81400000 + XLM_IRQ_NEST);       // lwz  r10,XLM_IRQ_NEST
1396		*lp++ = htonl(0x394affff);                                      // subi r10,r10,1
1397		*lp++ = htonl(0x91400000 + XLM_IRQ_NEST);       // stw  r10,XLM_IRQ_NEST
1398	<	*lp = htonl(0x48000000 + ((xlp - 0x800c) & 0x03fffffc));        // b            ROM_BASE+0x312c2c
1398	>	*lp = htonl(0x48000000 + ((npc - 0x31800c) & 0x03fffffc));      // b            ROM_BASE+0x312c2c
1399		#endif
1400
1401		/*
#	Line 1351 | Line 1417 | static bool patch_68k(void)
1417		uint32 *lp;
1418		uint16 *wp;
1419		uint8 *bp;
1420	<	uint32 base;
1420	>	uint32 base, loc;
1421
1422		// Remove 68k RESET instruction
1423		static const uint8 reset_dat[] = {0x4e, 0x70};
#	Line 1401 | Line 1467 | static bool patch_68k(void)
1467		lp[0x28 >> 2] = htonl(0x00000861);
1468		lp[0x58 >> 2] = htonl(0x30200000);
1469		lp[0x60 >> 2] = htonl(0x0000003d);
1470	+	} else if (ROMType == ROMTYPE_GOSSAMER) {
1471	+	base = 0x12d20;
1472	+	lp = (uint32 *)(ROM_BASE + base - 0x14);
1473	+	lp[0x00 >> 2] = htonl(ADDR_MAP_PATCH_SPACE - (base - 0x14));
1474	+	lp[0x10 >> 2] = htonl(0xcc003d11);              // Make it like the PowerMac 9500 UniversalInfo
1475	+	lp[0x14 >> 2] = htonl(0x3fff0401);
1476	+	lp[0x18 >> 2] = htonl(0x0300001c);
1477	+	lp[0x1c >> 2] = htonl(0x000108c4);
1478	+	lp[0x24 >> 2] = htonl(0xc301bf26);
1479	+	lp[0x28 >> 2] = htonl(0x00000861);
1480	+	lp[0x58 >> 2] = htonl(0x30410000);
1481	+	lp[0x60 >> 2] = htonl(0x0000003d);
1482		}
1483
1484		// Construct AddrMap for NewWorld ROM
1485	<	if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_ZANZIBAR) {
1485	>	if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GOSSAMER) {
1486		lp = (uint32 *)(ROM_BASE + ADDR_MAP_PATCH_SPACE);
1487		memset(lp - 10, 0, 0x128);
1488		lp[-10] = htonl(0x0300001c);
#	Line 1530 | Line 1608 | static bool patch_68k(void)
1608		*wp++ = htons(M68K_EMUL_OP_XPRAM2);
1609		*wp = htons(0x4ed3);                    // jmp  (a3)
1610
1611	<	static const uint32 nvram3_loc[] = {0x582f0, 0xa0a0, 0x7e50, 0xa1d0, 0};
1612	<	wp = (uint16 *)(ROM_BASE + nvram3_loc[ROMType]);
1611	>	static const uint8 nvram3_dat[] = {0x4e, 0xd3, 0x06, 0x41, 0x13, 0x00};
1612	>	if ((base = find_rom_data(0x7000, 0xb000, nvram3_dat, sizeof(nvram3_dat))) == 0) return false;
1613	>	D(bug("nvram3 %08lx\n", base));
1614	>	wp = (uint16 *)(ROM_BASE + base + 2);
1615	>	*wp++ = htons(M68K_EMUL_OP_XPRAM3);
1616	>	*wp = htons(0x4ed3);                    // jmp  (a3)
1617	>
1618	>	static const uint32 nvram4_loc[] = {0x582f0, 0xa0a0, 0x7e50, 0xa1d0, 0x538d0, 0};
1619	>	wp = (uint16 *)(ROM_BASE + nvram4_loc[ROMType]);
1620		*wp++ = htons(0x202f);                  // move.l       4(sp),d0
1621		*wp++ = htons(0x0004);
1622		*wp++ = htons(M68K_EMUL_OP_NVRAM1);
#	Line 1544 | Line 1629 | static bool patch_68k(void)
1629		*wp = htons(0x0004);
1630		}
1631
1632	<	static const uint32 nvram4_loc[] = {0x58460, 0xa0f0, 0x7f40, 0xa220, 0};
1633	<	wp = (uint16 *)(ROM_BASE + nvram4_loc[ROMType]);
1632	>	static const uint32 nvram5_loc[] = {0x58460, 0xa0f0, 0x7f40, 0xa220, 0x53a20, 0};
1633	>	wp = (uint16 *)(ROM_BASE + nvram5_loc[ROMType]);
1634		if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GAZELLE) {
1635		*wp++ = htons(0x202f);                  // move.l       4(sp),d0
1636		*wp++ = htons(0x0004);
#	Line 1573 | Line 1658 | static bool patch_68k(void)
1658		*wp = htons(M68K_NOP);
1659
1660		// Don't initialize SCC (via 0x1ac)
1661	<	static const uint8 scc_init_dat[] = {0x48, 0xe7, 0x38, 0xfe};
1662	<	if ((base = find_rom_data(0x190, 0x1f0, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1661	>	static const uint8 scc_init_caller_dat[] = {0x21, 0xce, 0x01, 0x08, 0x22, 0x78, 0x0d, 0xd8};
1662	>	if ((base = find_rom_data(0x180, 0x1f0, scc_init_caller_dat, sizeof(scc_init_caller_dat))) == 0) return false;
1663	>	D(bug("scc_init_caller %08lx\n", base + 12));
1664	>	wp = (uint16 *)(ROM_BASE + base + 12);
1665	>	loc = ntohs(wp[1]) + ((uintptr)wp - ROM_BASE) + 2;
1666	>	static const uint8 scc_init_dat[] = {0x20, 0x78, 0x01, 0xdc, 0x22, 0x78, 0x01, 0xd8};
1667	>	if ((base = find_rom_data(loc, loc + 0x80, scc_init_dat, sizeof(scc_init_dat))) != loc) return false;
1668		D(bug("scc_init %08lx\n", base));
1669	<	wp = (uint16 *)(ROM_BASE + base - 2);
1580	<	wp = (uint16 *)(ROM_BASE + ntohs(*wp) + base - 2);
1669	>	wp = (uint16 *)(ROM_BASE + base);
1670		*wp++ = htons(M68K_EMUL_OP_RESET);
1671		*wp = htons(M68K_RTS);
1672
#	Line 1722 | Line 1811 | static bool patch_68k(void)
1811		if ((base = find_rom_data(0x13000, 0x20000, gc_mask2_dat, sizeof(gc_mask2_dat))) == 0) return false;
1812		D(bug("gc_mask2 %08lx\n", base));
1813		wp = (uint16 *)(ROM_BASE + base);
1814	+	if (ROMType == ROMTYPE_GOSSAMER)
1815	+	*wp++ = htons(M68K_NOP);
1816		for (int i=0; i<5; i++) {
1817		*wp++ = htons(M68K_NOP);
1818		*wp++ = htons(M68K_NOP);
#	Line 1729 | Line 1820 | static bool patch_68k(void)
1820		*wp++ = htons(M68K_NOP);
1821		wp += 2;
1822		}
1823	<	if (ROMType == ROMTYPE_ZANZIBAR) {
1823	>	if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GOSSAMER) {
1824		for (int i=0; i<6; i++) {
1825		*wp++ = htons(M68K_NOP);
1826		*wp++ = htons(M68K_NOP);
#	Line 1802 | Line 1893 | static bool patch_68k(void)
1893		*wp = htons(M68K_RTS);
1894
1895		// Don't install Time Manager task for 60Hz interrupt (Enable60HzInts, via 0x2b8)
1896	<	if (ROMType == ROMTYPE_NEWWORLD) {
1896	>	if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_GOSSAMER) {
1897		static const uint8 tm_task_dat[] = {0x30, 0x3c, 0x4e, 0x2b, 0xa9, 0xc9};
1898	<	if ((base = find_rom_data(0x2e0, 0x320, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1898	>	if ((base = find_rom_data(0x2a0, 0x320, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1899		D(bug("tm_task %08lx\n", base));
1900		wp = (uint16 *)(ROM_BASE + base + 28);
1901		*wp++ = htons(M68K_NOP);
#	Line 1824 | Line 1915 | static bool patch_68k(void)
1915		}
1916
1917		// Don't read PVR from 0x5fffef80 in DriverServicesLib (via 0x316)
1918	<	if (ROMType != ROMTYPE_NEWWORLD) {
1918	>	if (ROMType != ROMTYPE_NEWWORLD && ROMType != ROMTYPE_GOSSAMER) {
1919		uint32 dsl_offset = find_rom_resource(FOURCC('n','l','i','b'), -16401);
1920		if (ROMType == ROMTYPE_ZANZIBAR) {
1921		static const uint8 dsl_pvr_dat[] = {0x40, 0x82, 0x00, 0x40, 0x38, 0x60, 0xef, 0x80, 0x3c, 0x63, 0x60, 0x00, 0x80, 0x83, 0x00, 0x00, 0x54, 0x84, 0x84, 0x3e};
#	Line 1859 | Line 1950 | static bool patch_68k(void)
1950		*lp = htonl(0x38600000);                // li   r3,0
1951		}
1952
1953	+	// FIXME: Fake reading from [HpChk]+4 (the callchain reports some function from DriverServicesLib)
1954	+	if (1) {
1955	+	uint32 hpchk_offset = find_rom_resource(FOURCC('n','l','i','b'), 10);
1956	+	static const uint8 hpchk_dat[] = {0x80, 0x80, 0x03, 0x16, 0x94, 0x21, 0xff, 0xb0, 0x83, 0xc4, 0x00, 0x04};
1957	+	if ((base = find_rom_data(hpchk_offset, hpchk_offset + 0x3000, hpchk_dat, sizeof(hpchk_dat))) == 0) return false;
1958	+	D(bug("hpchk %08lx\n", base));
1959	+	lp = (uint32 *)(ROM_BASE + base);
1960	+	*lp = htonl(0x80800000 + XLM_ZERO_PAGE);                // lwz  r4,(zero page)
1961	+	}
1962	+
1963		// Patch Name Registry
1964		static const uint8 name_reg_dat[] = {0x70, 0xff, 0xab, 0xeb};
1965		if ((base = find_rom_data(0x300, 0x380, name_reg_dat, sizeof(name_reg_dat))) == 0) return false;
#	Line 1910 | Line 2011 | static bool patch_68k(void)
2011		D(bug("scsi_var2 %08lx\n", base));
2012		wp = (uint16 *)(ROM_BASE + base);
2013		*wp++ = htons(0x7000);  // moveq #0,d0
2014	<	*wp = htons(M68K_RTS);  // bra
2014	>	*wp = htons(M68K_RTS);
2015	>	}
2016	>	}
2017	>	else if (ROMType == ROMTYPE_GOSSAMER) {
2018	>	static const uint8 scsi_var_dat[] = {0x70, 0x01, 0xa0, 0x89, 0x4a, 0x6e, 0xfe, 0xac, 0x4f, 0xef, 0x00, 0x10, 0x66, 0x00};
2019	>	if ((base = find_rom_data(0x1d700, 0x1d800, scsi_var_dat, sizeof(scsi_var_dat))) != 0) {
2020	>	D(bug("scsi_var %08lx\n", base));
2021	>	wp = (uint16 *)(ROM_BASE + base + 12);
2022	>	*wp = htons(0x6000);    // bra
2023	>	}
2024	>
2025	>	static const uint8 scsi_var2_dat[] = {0x4e, 0x56, 0xfc, 0x5a, 0x48, 0xe7, 0x1f, 0x38};
2026	>	if ((base = find_rom_data(0x1d900, 0x1da00, scsi_var2_dat, sizeof(scsi_var2_dat))) != 0) {
2027	>	D(bug("scsi_var2 %08lx\n", base));
2028	>	wp = (uint16 *)(ROM_BASE + base);
2029	>	*wp++ = htons(0x7000);  // moveq #0,d0
2030	>	*wp = htons(M68K_RTS);
2031		}
2032		}
2033		#endif
#	Line 1966 | Line 2083 | static bool patch_68k(void)
2083		memcpy((void *)(ROM_BASE + sony_offset + 0x200), cdrom_driver, sizeof(cdrom_driver));
2084
2085		// Install serial drivers
2086	<	memcpy((void *)(ROM_BASE + sony_offset + 0x300), ain_driver, sizeof(ain_driver));
2087	<	memcpy((void *)(ROM_BASE + sony_offset + 0x400), aout_driver, sizeof(aout_driver));
2088	<	memcpy((void *)(ROM_BASE + sony_offset + 0x500), bin_driver, sizeof(bin_driver));
2089	<	memcpy((void *)(ROM_BASE + sony_offset + 0x600), bout_driver, sizeof(bout_driver));
2086	>	gen_ain_driver( ROM_BASE + sony_offset + 0x300);
2087	>	gen_aout_driver(ROM_BASE + sony_offset + 0x400);
2088	>	gen_bin_driver( ROM_BASE + sony_offset + 0x500);
2089	>	gen_bout_driver(ROM_BASE + sony_offset + 0x600);
2090
2091		// Copy icons to ROM
2092		SonyDiskIconAddr = ROM_BASE + sony_offset + 0x800;
#	Line 1990 | Line 2107 | static bool patch_68k(void)
2107		*wp = htons(M68K_RTS);
2108
2109		// Don't install serial drivers from ROM
2110	<	if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_NEWWORLD) {
2110	>	if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_GOSSAMER) {
2111		wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('S','E','R','D'), 0));
2112		*wp = htons(M68K_RTS);
2113		} else {
#	Line 2171 | Line 2288 | void InstallDrivers(void)
2288		{
2289		D(bug("Installing drivers...\n"));
2290		M68kRegisters r;
2291	<	uint8 pb[SIZEOF_IOParam];
2291	>	SheepArray<SIZEOF_IOParam> pb_var;
2292	>	const uintptr pb = pb_var.addr();
2293
2294		// Install floppy driver
2295	<	if (ROMType == ROMTYPE_NEWWORLD) {
2295	>	if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_GOSSAMER) {
2296
2297	<	// Force installation of floppy driver with NewWorld ROMs
2297	>	// Force installation of floppy driver with NewWorld and Gossamer ROMs
2298		r.a[0] = ROM_BASE + sony_offset;
2299		r.d[0] = (uint32)SonyRefNum;
2300		Execute68kTrap(0xa43d, &r);             // DrvrInstallRsrvMem()
#	Line 2189 | Line 2307 | void InstallDrivers(void)
2307
2308		#if DISABLE_SCSI && 0
2309		// Fake SCSIGlobals
2310	<	static const uint8 fake_scsi_globals[32] = {0,};
2193	<	WriteMacInt32(0xc0c, (uint32)fake_scsi_globals);
2310	>	WriteMacInt32(0xc0c, SheepMem::ZeroPage());
2311		#endif
2312
2313		// Open .Sony driver
2314	<	WriteMacInt8((uint32)pb + ioPermssn, 0);
2315	<	WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Sony");
2316	<	r.a[0] = (uint32)pb;
2314	>	SheepString sony_str("\005.Sony");
2315	>	WriteMacInt8(pb + ioPermssn, 0);
2316	>	WriteMacInt32(pb + ioNamePtr, sony_str.addr());
2317	>	r.a[0] = pb;
2318		Execute68kTrap(0xa000, &r);             // Open()
2319
2320		// Install disk driver
#	Line 2210 | Line 2328 | void InstallDrivers(void)
2328		WriteMacInt16(dce + dCtlFlags, DiskDriverFlags);
2329
2330		// Open disk driver
2331	<	WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Disk");
2332	<	r.a[0] = (uint32)pb;
2331	>	SheepString disk_str("\005.Disk");
2332	>	WriteMacInt32(pb + ioNamePtr, disk_str.addr());
2333	>	r.a[0] = pb;
2334		Execute68kTrap(0xa000, &r);             // Open()
2335
2336		// Install CD-ROM driver unless nocdrom option given
#	Line 2228 | Line 2347 | void InstallDrivers(void)
2347		WriteMacInt16(dce + dCtlFlags, CDROMDriverFlags);
2348
2349		// Open CD-ROM driver
2350	<	WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\010.AppleCD");
2351	<	r.a[0] = (uint32)pb;
2350	>	SheepString apple_cd("\010.AppleCD");
2351	>	WriteMacInt32(pb + ioNamePtr, apple_cd.addr());
2352	>	r.a[0] = pb;
2353		Execute68kTrap(0xa000, &r);             // Open()
2354		}
2355

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