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root/cebix/SheepShaver/src/rom_patches.cpp
Revision: 1.2
Committed: 2002-04-21T15:07:07Z (22 years, 7 months ago) by gbeauche
Branch: MAIN
Changes since 1.1: +123 -0 lines
Log Message: 
Add support to decode parcels-based ROMs
- include/rom_patches.h (DecodeROM): Declare.
- rom_patches.cpp (DecodeROM): Define.
- Unix/main_unix.cpp, BeOS/main_beos.cpp (decode_lzss): Move to...
- rom_patches.cpp (decode_lzss): ... here.
- Unix/main_unix.cpp (main): Call DecodeROM().
- BeOS/main_beos.cpp (SheepShaver::load_rom): Call DecodeROM().

File Contents

# User Rev Content
1 cebix 1.1 /*
2     * rom_patches.cpp - ROM patches
3     *
4     * SheepShaver (C) 1997-2002 Christian Bauer and Marc Hellwig
5     *
6     * This program is free software; you can redistribute it and/or modify
7     * it under the terms of the GNU General Public License as published by
8     * the Free Software Foundation; either version 2 of the License, or
9     * (at your option) any later version.
10     *
11     * This program is distributed in the hope that it will be useful,
12     * but WITHOUT ANY WARRANTY; without even the implied warranty of
13     * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14     * GNU General Public License for more details.
15     *
16     * You should have received a copy of the GNU General Public License
17     * along with this program; if not, write to the Free Software
18     * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19     */
20    
21     /*
22     * TODO:
23     * IRQ_NEST must be handled atomically
24     * Don't use r1 in extra routines
25     */
26    
27     #include <string.h>
28    
29     #include "sysdeps.h"
30     #include "rom_patches.h"
31     #include "main.h"
32     #include "prefs.h"
33     #include "cpu_emulation.h"
34     #include "emul_op.h"
35     #include "xlowmem.h"
36     #include "sony.h"
37     #include "disk.h"
38     #include "cdrom.h"
39     #include "audio.h"
40     #include "audio_defs.h"
41     #include "serial.h"
42     #include "macos_util.h"
43    
44     #define DEBUG 0
45     #include "debug.h"
46    
47    
48     // 68k breakpoint address
49     //#define M68K_BREAK_POINT 0x29e0 // BootMe
50     //#define M68K_BREAK_POINT 0x2a1e // Boot block code returned
51     //#define M68K_BREAK_POINT 0x3150 // CritError
52     //#define M68K_BREAK_POINT 0x187ce // Unimplemented trap
53    
54     // PowerPC breakpoint address
55     //#define POWERPC_BREAK_POINT 0x36e6c0 // 68k emulator start
56    
57     #define DISABLE_SCSI 1
58    
59    
60     // Other ROM addresses
61     const uint32 CHECK_LOAD_PATCH_SPACE = 0x2f7f00;
62     const uint32 PUT_SCRAP_PATCH_SPACE = 0x2f7f80;
63     const uint32 GET_SCRAP_PATCH_SPACE = 0x2f7fc0;
64     const uint32 ADDR_MAP_PATCH_SPACE = 0x2f8000;
65    
66     // Global variables
67     int ROMType; // ROM type
68     static uint32 sony_offset; // Offset of .Sony driver resource
69    
70     // Prototypes
71     static bool patch_nanokernel_boot(void);
72     static bool patch_68k_emul(void);
73     static bool patch_nanokernel(void);
74     static bool patch_68k(void);
75    
76    
77 gbeauche 1.2 // Decode LZSS data
78     static void decode_lzss(const uint8 *src, uint8 *dest, int size)
79     {
80     char dict[0x1000];
81     int run_mask = 0, dict_idx = 0xfee;
82     for (;;) {
83     if (run_mask < 0x100) {
84     // Start new run
85     if (--size < 0)
86     break;
87     run_mask = *src++ | 0xff00;
88     }
89     bool bit = run_mask & 1;
90     run_mask >>= 1;
91     if (bit) {
92     // Verbatim copy
93     if (--size < 0)
94     break;
95     int c = *src++;
96     dict[dict_idx++] = c;
97     *dest++ = c;
98     dict_idx &= 0xfff;
99     } else {
100     // Copy from dictionary
101     if (--size < 0)
102     break;
103     int idx = *src++;
104     if (--size < 0)
105     break;
106     int cnt = *src++;
107     idx |= (cnt << 4) & 0xf00;
108     cnt = (cnt & 0x0f) + 3;
109     while (cnt--) {
110     char c = dict[idx++];
111     dict[dict_idx++] = c;
112     *dest++ = c;
113     idx &= 0xfff;
114     dict_idx &= 0xfff;
115     }
116     }
117     }
118     }
119    
120     // Decode parcels of ROM image (MacOS 9.X and even earlier)
121     void decode_parcels(const uint8 *src, uint8 *dest, int size)
122     {
123     uint32 parcel_offset = 0x14;
124     D(bug("Offset Type Name\n"));
125     while (parcel_offset != 0) {
126     const uint32 *parcel_data = (uint32 *)(src + parcel_offset);
127     parcel_offset = ntohl(parcel_data[0]);
128     uint32 parcel_type = ntohl(parcel_data[1]);
129     D(bug("%08x %c%c%c%c %s\n", parcel_offset,
130     (parcel_type >> 24) & 0xff, (parcel_type >> 16) & 0xff,
131     (parcel_type >> 8) & 0xff, parcel_type & 0xff, &parcel_data[6]));
132     if (parcel_type == FOURCC('r','o','m',' ')) {
133     uint32 lzss_offset = ntohl(parcel_data[2]);
134     uint32 lzss_size = ((uint32)src + parcel_offset) - ((uint32)parcel_data + lzss_offset);
135     decode_lzss((uint8 *)parcel_data + lzss_offset, dest, lzss_size);
136     }
137     }
138     }
139    
140    
141     /*
142     * Decode ROM image, 4 MB plain images or NewWorld images
143     */
144    
145     bool DecodeROM(uint8 *data, uint32 size)
146     {
147     if (size == ROM_SIZE) {
148     // Plain ROM image
149     memcpy((void *)ROM_BASE, data, ROM_SIZE);
150     return true;
151     }
152     else if (strncmp((char *)data, "<CHRP-BOOT>", 11) == 0) {
153     // CHRP compressed ROM image
154     uint32 image_offset, image_size;
155     bool decode_info_ok = false;
156    
157     char *s = strstr((char *)data, "constant lzss-offset");
158     if (s != NULL) {
159     // Probably a plain LZSS compressed ROM image
160     if (sscanf(s - 7, "%06x", &image_offset) == 1) {
161     s = strstr((char *)data, "constant lzss-size");
162     if (s != NULL && (sscanf(s - 7, "%06x", &image_size) == 1))
163     decode_info_ok = true;
164     }
165     }
166     else {
167     // Probably a MacOS 9.2.x ROM image
168     s = strstr((char *)data, "constant parcels-offset");
169     if (s != NULL) {
170     if (sscanf(s - 7, "%06x", &image_offset) == 1) {
171     s = strstr((char *)data, "constant parcels-size");
172     if (s != NULL && (sscanf(s - 7, "%06x", &image_size) == 1))
173     decode_info_ok = true;
174     }
175     }
176     }
177    
178     // No valid information to decode the ROM found?
179     if (!decode_info_ok)
180     return false;
181    
182     // Check signature, this could be a parcels-based ROM image
183     uint32 rom_signature = ntohl(*(uint32 *)(data + image_offset));
184     if (rom_signature == FOURCC('p','r','c','l')) {
185     D(bug("Offset of parcels data: %08x\n", image_offset));
186     D(bug("Size of parcels data: %08x\n", image_size));
187     decode_parcels(data + image_offset, (uint8 *)ROM_BASE, image_size);
188     }
189     else {
190     D(bug("Offset of compressed data: %08x\n", image_offset));
191     D(bug("Size of compressed data: %08x\n", image_size));
192     decode_lzss(data + image_offset, (uint8 *)ROM_BASE, image_size);
193     }
194     return true;
195     }
196     return false;
197     }
198    
199    
200 cebix 1.1 /*
201     * Search ROM for byte string, return ROM offset (or 0)
202     */
203    
204     static uint32 find_rom_data(uint32 start, uint32 end, const uint8 *data, uint32 data_len)
205     {
206     uint32 ofs = start;
207     while (ofs < end) {
208     if (!memcmp((void *)(ROM_BASE + ofs), data, data_len))
209     return ofs;
210     ofs++;
211     }
212     return 0;
213     }
214    
215    
216     /*
217     * Search ROM resource by type/ID, return ROM offset of resource data
218     */
219    
220     static uint32 rsrc_ptr = 0;
221    
222     // id = 4711 means "find any ID"
223     static uint32 find_rom_resource(uint32 s_type, int16 s_id = 4711, bool cont = false)
224     {
225     uint32 *lp = (uint32 *)(ROM_BASE + 0x1a);
226     uint32 x = ntohl(*lp);
227     uint8 *bp = (uint8 *)(ROM_BASE + x + 5);
228     uint32 header_size = *bp;
229    
230     if (!cont)
231     rsrc_ptr = x;
232     else if (rsrc_ptr == 0)
233     return 0;
234    
235     for (;;) {
236     lp = (uint32 *)(ROM_BASE + rsrc_ptr);
237     rsrc_ptr = ntohl(*lp);
238     if (rsrc_ptr == 0)
239     break;
240    
241     rsrc_ptr += header_size;
242    
243     lp = (uint32 *)(ROM_BASE + rsrc_ptr + 4);
244     uint32 data = ntohl(*lp); lp++;
245     uint32 type = ntohl(*lp); lp++;
246     int16 id = ntohs(*(int16 *)lp);
247     if (type == s_type && (id == s_id || s_id == 4711))
248     return data;
249     }
250     return 0;
251     }
252    
253    
254     /*
255     * Search offset of A-Trap routine in ROM
256     */
257    
258     static uint32 find_rom_trap(uint16 trap)
259     {
260     uint32 *lp = (uint32 *)(ROM_BASE + 0x22);
261     lp = (uint32 *)(ROM_BASE + ntohl(*lp));
262    
263     if (trap > 0xa800)
264     return ntohl(lp[trap & 0x3ff]);
265     else
266     return ntohl(lp[(trap & 0xff) + 0x400]);
267     }
268    
269    
270     /*
271     * List of audio sifters installed in ROM and System file
272     */
273    
274     struct sift_entry {
275     uint32 type;
276     int16 id;
277     };
278     static sift_entry sifter_list[32];
279     static int num_sifters;
280    
281     void AddSifter(uint32 type, int16 id)
282     {
283     if (FindSifter(type, id))
284     return;
285     D(bug(" adding sifter type %c%c%c%c (%08x), id %d\n", type >> 24, (type >> 16) & 0xff, (type >> 8) & 0xff, type & 0xff, type, id));
286     sifter_list[num_sifters].type = type;
287     sifter_list[num_sifters].id = id;
288     num_sifters++;
289     }
290    
291     bool FindSifter(uint32 type, int16 id)
292     {
293     for (int i=0; i<num_sifters; i++) {
294     if (sifter_list[i].type == type && sifter_list[i].id == id)
295     return true;
296     }
297     return false;
298     }
299    
300    
301     /*
302     * Driver stubs
303     */
304    
305     static const uint8 sony_driver[] = { // Replacement for .Sony driver
306     // Driver header
307     SonyDriverFlags >> 8, SonyDriverFlags & 0xff, 0, 0, 0, 0, 0, 0,
308     0x00, 0x18, // Open() offset
309     0x00, 0x1c, // Prime() offset
310     0x00, 0x20, // Control() offset
311     0x00, 0x2c, // Status() offset
312     0x00, 0x52, // Close() offset
313     0x05, 0x2e, 0x53, 0x6f, 0x6e, 0x79, // ".Sony"
314    
315     // Open()
316     M68K_EMUL_OP_SONY_OPEN >> 8, M68K_EMUL_OP_SONY_OPEN & 0xff,
317     0x4e, 0x75, // rts
318    
319     // Prime()
320     M68K_EMUL_OP_SONY_PRIME >> 8, M68K_EMUL_OP_SONY_PRIME & 0xff,
321     0x60, 0x0e, // bra IOReturn
322    
323     // Control()
324     M68K_EMUL_OP_SONY_CONTROL >> 8, M68K_EMUL_OP_SONY_CONTROL & 0xff,
325     0x0c, 0x68, 0x00, 0x01, 0x00, 0x1a, // cmp.w #1,$1a(a0)
326     0x66, 0x04, // bne IOReturn
327     0x4e, 0x75, // rts
328    
329     // Status()
330     M68K_EMUL_OP_SONY_STATUS >> 8, M68K_EMUL_OP_SONY_STATUS & 0xff,
331    
332     // IOReturn
333     0x32, 0x28, 0x00, 0x06, // move.w 6(a0),d1
334     0x08, 0x01, 0x00, 0x09, // btst #9,d1
335     0x67, 0x0c, // beq 1
336     0x4a, 0x40, // tst.w d0
337     0x6f, 0x02, // ble 2
338     0x42, 0x40, // clr.w d0
339     0x31, 0x40, 0x00, 0x10, //2 move.w d0,$10(a0)
340     0x4e, 0x75, // rts
341     0x4a, 0x40, //1 tst.w d0
342     0x6f, 0x04, // ble 3
343     0x42, 0x40, // clr.w d0
344     0x4e, 0x75, // rts
345     0x2f, 0x38, 0x08, 0xfc, //3 move.l $8fc,-(sp)
346     0x4e, 0x75, // rts
347    
348     // Close()
349     0x70, 0xe8, // moveq #-24,d0
350     0x4e, 0x75 // rts
351     };
352    
353     static const uint8 disk_driver[] = { // Generic disk driver
354     // Driver header
355     DiskDriverFlags >> 8, DiskDriverFlags & 0xff, 0, 0, 0, 0, 0, 0,
356     0x00, 0x18, // Open() offset
357     0x00, 0x1c, // Prime() offset
358     0x00, 0x20, // Control() offset
359     0x00, 0x2c, // Status() offset
360     0x00, 0x52, // Close() offset
361     0x05, 0x2e, 0x44, 0x69, 0x73, 0x6b, // ".Disk"
362    
363     // Open()
364     M68K_EMUL_OP_DISK_OPEN >> 8, M68K_EMUL_OP_DISK_OPEN & 0xff,
365     0x4e, 0x75, // rts
366    
367     // Prime()
368     M68K_EMUL_OP_DISK_PRIME >> 8, M68K_EMUL_OP_DISK_PRIME & 0xff,
369     0x60, 0x0e, // bra IOReturn
370    
371     // Control()
372     M68K_EMUL_OP_DISK_CONTROL >> 8, M68K_EMUL_OP_DISK_CONTROL & 0xff,
373     0x0c, 0x68, 0x00, 0x01, 0x00, 0x1a, // cmp.w #1,$1a(a0)
374     0x66, 0x04, // bne IOReturn
375     0x4e, 0x75, // rts
376    
377     // Status()
378     M68K_EMUL_OP_DISK_STATUS >> 8, M68K_EMUL_OP_DISK_STATUS & 0xff,
379    
380     // IOReturn
381     0x32, 0x28, 0x00, 0x06, // move.w 6(a0),d1
382     0x08, 0x01, 0x00, 0x09, // btst #9,d1
383     0x67, 0x0c, // beq 1
384     0x4a, 0x40, // tst.w d0
385     0x6f, 0x02, // ble 2
386     0x42, 0x40, // clr.w d0
387     0x31, 0x40, 0x00, 0x10, //2 move.w d0,$10(a0)
388     0x4e, 0x75, // rts
389     0x4a, 0x40, //1 tst.w d0
390     0x6f, 0x04, // ble 3
391     0x42, 0x40, // clr.w d0
392     0x4e, 0x75, // rts
393     0x2f, 0x38, 0x08, 0xfc, //3 move.l $8fc,-(sp)
394     0x4e, 0x75, // rts
395    
396     // Close()
397     0x70, 0xe8, // moveq #-24,d0
398     0x4e, 0x75 // rts
399     };
400    
401     static const uint8 cdrom_driver[] = { // CD-ROM driver
402     // Driver header
403     CDROMDriverFlags >> 8, CDROMDriverFlags & 0xff, 0, 0, 0, 0, 0, 0,
404     0x00, 0x1c, // Open() offset
405     0x00, 0x20, // Prime() offset
406     0x00, 0x24, // Control() offset
407     0x00, 0x30, // Status() offset
408     0x00, 0x56, // Close() offset
409     0x08, 0x2e, 0x41, 0x70, 0x70, 0x6c, 0x65, 0x43, 0x44, 0x00, // ".AppleCD"
410    
411     // Open()
412     M68K_EMUL_OP_CDROM_OPEN >> 8, M68K_EMUL_OP_CDROM_OPEN & 0xff,
413     0x4e, 0x75, // rts
414    
415     // Prime()
416     M68K_EMUL_OP_CDROM_PRIME >> 8, M68K_EMUL_OP_CDROM_PRIME & 0xff,
417     0x60, 0x0e, // bra IOReturn
418    
419     // Control()
420     M68K_EMUL_OP_CDROM_CONTROL >> 8, M68K_EMUL_OP_CDROM_CONTROL & 0xff,
421     0x0c, 0x68, 0x00, 0x01, 0x00, 0x1a, // cmp.w #1,$1a(a0)
422     0x66, 0x04, // bne IOReturn
423     0x4e, 0x75, // rts
424    
425     // Status()
426     M68K_EMUL_OP_CDROM_STATUS >> 8, M68K_EMUL_OP_CDROM_STATUS & 0xff,
427    
428     // IOReturn
429     0x32, 0x28, 0x00, 0x06, // move.w 6(a0),d1
430     0x08, 0x01, 0x00, 0x09, // btst #9,d1
431     0x67, 0x0c, // beq 1
432     0x4a, 0x40, // tst.w d0
433     0x6f, 0x02, // ble 2
434     0x42, 0x40, // clr.w d0
435     0x31, 0x40, 0x00, 0x10, //2 move.w d0,$10(a0)
436     0x4e, 0x75, // rts
437     0x4a, 0x40, //1 tst.w d0
438     0x6f, 0x04, // ble 3
439     0x42, 0x40, // clr.w d0
440     0x4e, 0x75, // rts
441     0x2f, 0x38, 0x08, 0xfc, //3 move.l $8fc,-(sp)
442     0x4e, 0x75, // rts
443    
444     // Close()
445     0x70, 0xe8, // moveq #-24,d0
446     0x4e, 0x75 // rts
447     };
448    
449     #ifdef __linux__
450     static uint32 serial_nothing_tvect[2] = {(uint32)SerialNothing, 0};
451     static uint32 serial_open_tvect[2] = {(uint32)SerialOpen, 0};
452     static uint32 serial_prime_in_tvect[2] = {(uint32)SerialPrimeIn, 0};
453     static uint32 serial_prime_out_tvect[2] = {(uint32)SerialPrimeOut, 0};
454     static uint32 serial_control_tvect[2] = {(uint32)SerialControl, 0};
455     static uint32 serial_status_tvect[2] = {(uint32)SerialStatus, 0};
456     static uint32 serial_close_tvect[2] = {(uint32)SerialClose, 0};
457     #endif
458    
459     static const uint32 ain_driver[] = { // .AIn driver header
460     0x4d000000, 0x00000000,
461     0x00200040, 0x00600080,
462     0x00a0042e, 0x41496e00,
463     0x00000000, 0x00000000,
464     0xaafe0700, 0x00000000,
465     0x00000000, 0x00179822,
466     #ifdef __linux__
467     0x00010004, (uint32)serial_nothing_tvect,
468     #else
469     0x00010004, (uint32)SerialNothing,
470     #endif
471     0x00000000, 0x00000000,
472     0xaafe0700, 0x00000000,
473     0x00000000, 0x00179822,
474     #ifdef __linux__
475     0x00010004, (uint32)serial_prime_in_tvect,
476     #else
477     0x00010004, (uint32)SerialPrimeIn,
478     #endif
479     0x00000000, 0x00000000,
480     0xaafe0700, 0x00000000,
481     0x00000000, 0x00179822,
482     #ifdef __linux__
483     0x00010004, (uint32)serial_control_tvect,
484     #else
485     0x00010004, (uint32)SerialControl,
486     #endif
487     0x00000000, 0x00000000,
488     0xaafe0700, 0x00000000,
489     0x00000000, 0x00179822,
490     #ifdef __linux__
491     0x00010004, (uint32)serial_status_tvect,
492     #else
493     0x00010004, (uint32)SerialStatus,
494     #endif
495     0x00000000, 0x00000000,
496     0xaafe0700, 0x00000000,
497     0x00000000, 0x00179822,
498     #ifdef __linux__
499     0x00010004, (uint32)serial_nothing_tvect,
500     #else
501     0x00010004, (uint32)SerialNothing,
502     #endif
503     0x00000000, 0x00000000,
504     };
505    
506     static const uint32 aout_driver[] = { // .AOut driver header
507     0x4d000000, 0x00000000,
508     0x00200040, 0x00600080,
509     0x00a0052e, 0x414f7574,
510     0x00000000, 0x00000000,
511     0xaafe0700, 0x00000000,
512     0x00000000, 0x00179822,
513     #ifdef __linux__
514     0x00010004, (uint32)serial_open_tvect,
515     #else
516     0x00010004, (uint32)SerialOpen,
517     #endif
518     0x00000000, 0x00000000,
519     0xaafe0700, 0x00000000,
520     0x00000000, 0x00179822,
521     #ifdef __linux__
522     0x00010004, (uint32)serial_prime_out_tvect,
523     #else
524     0x00010004, (uint32)SerialPrimeOut,
525     #endif
526     0x00000000, 0x00000000,
527     0xaafe0700, 0x00000000,
528     0x00000000, 0x00179822,
529     #ifdef __linux__
530     0x00010004, (uint32)serial_control_tvect,
531     #else
532     0x00010004, (uint32)SerialControl,
533     #endif
534     0x00000000, 0x00000000,
535     0xaafe0700, 0x00000000,
536     0x00000000, 0x00179822,
537     #ifdef __linux__
538     0x00010004, (uint32)serial_status_tvect,
539     #else
540     0x00010004, (uint32)SerialStatus,
541     #endif
542     0x00000000, 0x00000000,
543     0xaafe0700, 0x00000000,
544     0x00000000, 0x00179822,
545     #ifdef __linux__
546     0x00010004, (uint32)serial_close_tvect,
547     #else
548     0x00010004, (uint32)SerialClose,
549     #endif
550     0x00000000, 0x00000000,
551     };
552    
553     static const uint32 bin_driver[] = { // .BIn driver header
554     0x4d000000, 0x00000000,
555     0x00200040, 0x00600080,
556     0x00a0042e, 0x42496e00,
557     0x00000000, 0x00000000,
558     0xaafe0700, 0x00000000,
559     0x00000000, 0x00179822,
560     #ifdef __linux__
561     0x00010004, (uint32)serial_nothing_tvect,
562     #else
563     0x00010004, (uint32)SerialNothing,
564     #endif
565     0x00000000, 0x00000000,
566     0xaafe0700, 0x00000000,
567     0x00000000, 0x00179822,
568     #ifdef __linux__
569     0x00010004, (uint32)serial_prime_in_tvect,
570     #else
571     0x00010004, (uint32)SerialPrimeIn,
572     #endif
573     0x00000000, 0x00000000,
574     0xaafe0700, 0x00000000,
575     0x00000000, 0x00179822,
576     #ifdef __linux__
577     0x00010004, (uint32)serial_control_tvect,
578     #else
579     0x00010004, (uint32)SerialControl,
580     #endif
581     0x00000000, 0x00000000,
582     0xaafe0700, 0x00000000,
583     0x00000000, 0x00179822,
584     #ifdef __linux__
585     0x00010004, (uint32)serial_status_tvect,
586     #else
587     0x00010004, (uint32)SerialStatus,
588     #endif
589     0x00000000, 0x00000000,
590     0xaafe0700, 0x00000000,
591     0x00000000, 0x00179822,
592     #ifdef __linux__
593     0x00010004, (uint32)serial_nothing_tvect,
594     #else
595     0x00010004, (uint32)SerialNothing,
596     #endif
597     0x00000000, 0x00000000,
598     };
599    
600     static const uint32 bout_driver[] = { // .BOut driver header
601     0x4d000000, 0x00000000,
602     0x00200040, 0x00600080,
603     0x00a0052e, 0x424f7574,
604     0x00000000, 0x00000000,
605     0xaafe0700, 0x00000000,
606     0x00000000, 0x00179822,
607     #ifdef __linux__
608     0x00010004, (uint32)serial_open_tvect,
609     #else
610     0x00010004, (uint32)SerialOpen,
611     #endif
612     0x00000000, 0x00000000,
613     0xaafe0700, 0x00000000,
614     0x00000000, 0x00179822,
615     #ifdef __linux__
616     0x00010004, (uint32)serial_prime_out_tvect,
617     #else
618     0x00010004, (uint32)SerialPrimeOut,
619     #endif
620     0x00000000, 0x00000000,
621     0xaafe0700, 0x00000000,
622     0x00000000, 0x00179822,
623     #ifdef __linux__
624     0x00010004, (uint32)serial_control_tvect,
625     #else
626     0x00010004, (uint32)SerialControl,
627     #endif
628     0x00000000, 0x00000000,
629     0xaafe0700, 0x00000000,
630     0x00000000, 0x00179822,
631     #ifdef __linux__
632     0x00010004, (uint32)serial_status_tvect,
633     #else
634     0x00010004, (uint32)SerialStatus,
635     #endif
636     0x00000000, 0x00000000,
637     0xaafe0700, 0x00000000,
638     0x00000000, 0x00179822,
639     #ifdef __linux__
640     0x00010004, (uint32)serial_close_tvect,
641     #else
642     0x00010004, (uint32)SerialClose,
643     #endif
644     0x00000000, 0x00000000,
645     };
646    
647     static const uint8 adbop_patch[] = { // Call ADBOp() completion procedure
648     // The completion procedure may call ADBOp() again!
649     0x40, 0xe7, // move sr,-(sp)
650     0x00, 0x7c, 0x07, 0x00, // ori #$0700,sr
651     M68K_EMUL_OP_ADBOP >> 8, M68K_EMUL_OP_ADBOP & 0xff,
652     0x48, 0xe7, 0x70, 0xf0, // movem.l d1-d3/a0-a3,-(sp)
653     0x26, 0x48, // move.l a0,a3
654     0x4a, 0xab, 0x00, 0x04, // tst.l 4(a3)
655     0x67, 0x00, 0x00, 0x18, // beq 1
656     0x20, 0x53, // move.l (a3),a0
657     0x22, 0x6b, 0x00, 0x04, // move.l 4(a3),a1
658     0x24, 0x6b, 0x00, 0x08, // move.l 8(a3),a2
659     0x26, 0x78, 0x0c, 0xf8, // move.l $cf8,a3
660     0x4e, 0x91, // jsr (a1)
661     0x70, 0x00, // moveq #0,d0
662     0x60, 0x00, 0x00, 0x04, // bra 2
663     0x70, 0xff, //1 moveq #-1,d0
664     0x4c, 0xdf, 0x0f, 0x0e, //2 movem.l (sp)+,d1-d3/a0-a3
665     0x46, 0xdf, // move (sp)+,sr
666     0x4e, 0x75 // rts
667     };
668    
669    
670     /*
671     * Install ROM patches (RAMBase and KernelDataAddr must be set)
672     */
673    
674     bool PatchROM(void)
675     {
676     // Print ROM info
677     D(bug("Checksum: %08lx\n", ntohl(*(uint32 *)ROM_BASE)));
678     D(bug("Version: %04x\n", ntohs(*(uint16 *)(ROM_BASE + 8))));
679     D(bug("Sub Version: %04x\n", ntohs(*(uint16 *)(ROM_BASE + 18))));
680     D(bug("Nanokernel ID: %s\n", (char *)ROM_BASE + 0x30d064));
681     D(bug("Resource Map at %08lx\n", ntohl(*(uint32 *)(ROM_BASE + 26))));
682     D(bug("Trap Tables at %08lx\n\n", ntohl(*(uint32 *)(ROM_BASE + 34))));
683    
684     // Detect ROM type
685     if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot TNT", 8))
686     ROMType = ROMTYPE_TNT;
687     else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Alchemy", 12))
688     ROMType = ROMTYPE_ALCHEMY;
689     else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Zanzibar", 13))
690     ROMType = ROMTYPE_ZANZIBAR;
691     else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Gazelle", 12))
692     ROMType = ROMTYPE_GAZELLE;
693     else if (!memcmp((void *)(ROM_BASE + 0x30d064), "NewWorld", 8))
694     ROMType = ROMTYPE_NEWWORLD;
695     else
696     return false;
697    
698     // Apply patches
699     if (!patch_nanokernel_boot()) return false;
700     if (!patch_68k_emul()) return false;
701     if (!patch_nanokernel()) return false;
702     if (!patch_68k()) return false;
703    
704     #ifdef M68K_BREAK_POINT
705     // Install 68k breakpoint
706     uint16 *wp = (uint16 *)(ROM_BASE + M68K_BREAK_POINT);
707     *wp++ = htons(M68K_EMUL_BREAK);
708     *wp = htons(M68K_EMUL_RETURN);
709     #endif
710    
711     #ifdef POWERPC_BREAK_POINT
712     // Install PowerPC breakpoint
713     uint32 *lp = (uint32 *)(ROM_BASE + POWERPC_BREAK_POINT);
714     *lp = htonl(0);
715     #endif
716    
717     // Copy 68k emulator to 2MB boundary
718     memcpy((void *)(ROM_BASE + ROM_SIZE), (void *)(ROM_BASE + ROM_SIZE - 0x100000), 0x100000);
719     return true;
720     }
721    
722    
723     /*
724     * Nanokernel boot routine patches
725     */
726    
727     static bool patch_nanokernel_boot(void)
728     {
729     uint32 *lp;
730    
731     // ROM boot structure patches
732     lp = (uint32 *)(ROM_BASE + 0x30d000);
733     lp[0x9c >> 2] = htonl(KernelDataAddr); // LA_InfoRecord
734     lp[0xa0 >> 2] = htonl(KernelDataAddr); // LA_KernelData
735     lp[0xa4 >> 2] = htonl(KernelDataAddr + 0x1000); // LA_EmulatorData
736     lp[0xa8 >> 2] = htonl(ROM_BASE + 0x480000); // LA_DispatchTable
737     lp[0xac >> 2] = htonl(ROM_BASE + 0x460000); // LA_EmulatorCode
738     lp[0x360 >> 2] = htonl(0); // Physical RAM base (? on NewWorld ROM, this contains -1)
739     lp[0xfd8 >> 2] = htonl(ROM_BASE + 0x2a); // 68k reset vector
740    
741     // Skip SR/BAT/SDR init
742     if (ROMType == ROMTYPE_GAZELLE || ROMType == ROMTYPE_NEWWORLD) {
743     lp = (uint32 *)(ROM_BASE + 0x310000);
744     *lp++ = htonl(POWERPC_NOP);
745     *lp = htonl(0x38000000);
746     }
747     static const uint32 sr_init_loc[] = {0x3101b0, 0x3101b0, 0x3101b0, 0x3101ec, 0x310200};
748     lp = (uint32 *)(ROM_BASE + 0x310008);
749     *lp = htonl(0x48000000 | (sr_init_loc[ROMType] - 8) & 0xffff); // b ROM_BASE+0x3101b0
750     lp = (uint32 *)(ROM_BASE + sr_init_loc[ROMType]);
751     *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA); // lwz r1,(pointer to Kernel Data)
752     *lp++ = htonl(0x3da0dead); // lis r13,0xdead (start of kernel memory)
753     *lp++ = htonl(0x3dc00010); // lis r14,0x0010 (size of page table)
754     *lp = htonl(0x3de00010); // lis r15,0x0010 (size of kernel memory)
755    
756     // Don't read PVR
757     static const uint32 pvr_loc[] = {0x3103b0, 0x3103b4, 0x3103b4, 0x310400, 0x310438};
758     lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
759     *lp = htonl(0x81800000 + XLM_PVR); // lwz r12,(theoretical PVR)
760    
761     // Set CPU specific data (even if ROM doesn't have support for that CPU)
762     lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
763     if (ntohl(lp[6]) != 0x2c0c0001)
764     return false;
765     uint32 ofs = ntohl(lp[7]) & 0xffff;
766     D(bug("ofs %08lx\n", ofs));
767     lp[8] = htonl((ntohl(lp[8]) & 0xffff) | 0x48000000); // beq -> b
768     uint32 loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
769     D(bug("loc %08lx\n", loc));
770     lp = (uint32 *)(ROM_BASE + ofs + 0x310000);
771     switch (PVR >> 16) {
772     case 1: // 601
773     lp[0] = htonl(0x1000); // Page size
774     lp[1] = htonl(0x8000); // Data cache size
775     lp[2] = htonl(0x8000); // Inst cache size
776     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
777     lp[4] = htonl(0x00010040); // Unified caches/Inst cache line size
778     lp[5] = htonl(0x00400020); // Data cache line size/Data cache block size touch
779     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
780     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
781     lp[8] = htonl(0x01000002); // TLB total size/TLB assoc
782     break;
783     case 3: // 603
784     lp[0] = htonl(0x1000); // Page size
785     lp[1] = htonl(0x2000); // Data cache size
786     lp[2] = htonl(0x2000); // Inst cache size
787     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
788     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
789     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
790     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
791     lp[7] = htonl(0x00020002); // Inst cache assoc/Data cache assoc
792     lp[8] = htonl(0x00400002); // TLB total size/TLB assoc
793     break;
794     case 4: // 604
795     lp[0] = htonl(0x1000); // Page size
796     lp[1] = htonl(0x4000); // Data cache size
797     lp[2] = htonl(0x4000); // Inst cache size
798     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
799     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
800     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
801     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
802     lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc
803     lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
804     break;
805     // case 5: // 740?
806     case 6: // 603e
807     case 7: // 603ev
808     lp[0] = htonl(0x1000); // Page size
809     lp[1] = htonl(0x4000); // Data cache size
810     lp[2] = htonl(0x4000); // Inst cache size
811     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
812     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
813     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
814     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
815     lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc
816     lp[8] = htonl(0x00400002); // TLB total size/TLB assoc
817     break;
818     case 8: // 750
819     lp[0] = htonl(0x1000); // Page size
820     lp[1] = htonl(0x8000); // Data cache size
821     lp[2] = htonl(0x8000); // Inst cache size
822     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
823     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
824     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
825     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
826     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
827     lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
828     break;
829     case 9: // 604e
830     case 10: // 604ev5
831     lp[0] = htonl(0x1000); // Page size
832     lp[1] = htonl(0x8000); // Data cache size
833     lp[2] = htonl(0x8000); // Inst cache size
834     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
835     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
836     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
837     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
838     lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc
839     lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
840     break;
841     // case 11: // X704?
842     case 12: // ???
843     lp[0] = htonl(0x1000); // Page size
844     lp[1] = htonl(0x8000); // Data cache size
845     lp[2] = htonl(0x8000); // Inst cache size
846     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
847     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
848     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
849     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
850     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
851     lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
852     break;
853     case 13: // ???
854     lp[0] = htonl(0x1000); // Page size
855     lp[1] = htonl(0x8000); // Data cache size
856     lp[2] = htonl(0x8000); // Inst cache size
857     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
858     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
859     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
860     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
861     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
862     lp[8] = htonl(0x01000004); // TLB total size/TLB assoc
863     break;
864     // case 50: // 821
865     // case 80: // 860
866     case 96: // ???
867     lp[0] = htonl(0x1000); // Page size
868     lp[1] = htonl(0x8000); // Data cache size
869     lp[2] = htonl(0x8000); // Inst cache size
870     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
871     lp[4] = htonl(0x00010020); // Unified caches/Inst cache line size
872     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
873     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
874     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
875     lp[8] = htonl(0x00800004); // TLB total size/TLB assoc
876     break;
877     default:
878     printf("WARNING: Unknown CPU type\n");
879     break;
880     }
881    
882     // Don't set SPRG3, don't test MQ
883     lp = (uint32 *)(ROM_BASE + loc + 0x20);
884     *lp++ = htonl(POWERPC_NOP);
885     lp++;
886     *lp++ = htonl(POWERPC_NOP);
887     lp++;
888     *lp = htonl(POWERPC_NOP);
889    
890     // Don't read MSR
891     lp = (uint32 *)(ROM_BASE + loc + 0x40);
892     *lp = htonl(0x39c00000); // li r14,0
893    
894     // Don't write to DEC
895     lp = (uint32 *)(ROM_BASE + loc + 0x70);
896     *lp++ = htonl(POWERPC_NOP);
897     loc = (ntohl(lp[0]) & 0xffff) + (uint32)lp - ROM_BASE;
898     D(bug("loc %08lx\n", loc));
899    
900     // Don't set SPRG3
901     lp = (uint32 *)(ROM_BASE + loc + 0x2c);
902     *lp = htonl(POWERPC_NOP);
903    
904     // Don't read PVR
905     static const uint32 pvr_ofs[] = {0x138, 0x138, 0x138, 0x140, 0x148};
906     lp = (uint32 *)(ROM_BASE + loc + pvr_ofs[ROMType]);
907     *lp = htonl(0x82e00000 + XLM_PVR); // lwz r23,(theoretical PVR)
908     lp = (uint32 *)(ROM_BASE + loc + 0x170);
909     if (ntohl(*lp) == 0x7eff42a6) // NewWorld ROM
910     *lp = htonl(0x82e00000 + XLM_PVR); // lwz r23,(theoretical PVR)
911     lp = (uint32 *)(ROM_BASE + 0x313134);
912     if (ntohl(*lp) == 0x7e5f42a6)
913     *lp = htonl(0x82400000 + XLM_PVR); // lwz r18,(theoretical PVR)
914     lp = (uint32 *)(ROM_BASE + 0x3131f4);
915     if (ntohl(*lp) == 0x7e5f42a6) // NewWorld ROM
916     *lp = htonl(0x82400000 + XLM_PVR); // lwz r18,(theoretical PVR)
917    
918     // Don't read SDR1
919     static const uint32 sdr1_ofs[] = {0x174, 0x174, 0x174, 0x17c, 0x19c};
920     lp = (uint32 *)(ROM_BASE + loc + sdr1_ofs[ROMType]);
921     *lp++ = htonl(0x3d00dead); // lis r8,0xdead (pointer to page table)
922     *lp++ = htonl(0x3ec0001f); // lis r22,0x001f (size of page table)
923     *lp = htonl(POWERPC_NOP);
924    
925     // Don't clear page table
926     static const uint32 pgtb_ofs[] = {0x198, 0x198, 0x198, 0x1a0, 0x1c4};
927     lp = (uint32 *)(ROM_BASE + loc + pgtb_ofs[ROMType]);
928     *lp = htonl(POWERPC_NOP);
929    
930     // Don't invalidate TLB
931     static const uint32 tlb_ofs[] = {0x1a0, 0x1a0, 0x1a0, 0x1a8, 0x1cc};
932     lp = (uint32 *)(ROM_BASE + loc + tlb_ofs[ROMType]);
933     *lp = htonl(POWERPC_NOP);
934    
935     // Don't create RAM descriptor table
936     static const uint32 desc_ofs[] = {0x350, 0x350, 0x350, 0x358, 0x37c};
937     lp = (uint32 *)(ROM_BASE + loc + desc_ofs[ROMType]);
938     *lp = htonl(POWERPC_NOP);
939    
940     // Don't load SRs and BATs
941     static const uint32 sr_ofs[] = {0x3d8, 0x3d8, 0x3d8, 0x3e0, 0x404};
942     lp = (uint32 *)(ROM_BASE + loc + sr_ofs[ROMType]);
943     *lp = htonl(POWERPC_NOP);
944    
945     // Don't mess with SRs
946     static const uint32 sr2_ofs[] = {0x312118, 0x312118, 0x312118, 0x312118, 0x3121b4};
947     lp = (uint32 *)(ROM_BASE + sr2_ofs[ROMType]);
948     *lp = htonl(POWERPC_BLR);
949    
950     // Don't check performance monitor
951     static const uint32 pm_ofs[] = {0x313148, 0x313148, 0x313148, 0x313148, 0x313218};
952     lp = (uint32 *)(ROM_BASE + pm_ofs[ROMType]);
953     while (ntohl(*lp) != 0x7e58eba6) lp++;
954     *lp++ = htonl(POWERPC_NOP);
955     while (ntohl(*lp) != 0x7e78eaa6) lp++;
956     *lp++ = htonl(POWERPC_NOP);
957     while (ntohl(*lp) != 0x7e59eba6) lp++;
958     *lp++ = htonl(POWERPC_NOP);
959     while (ntohl(*lp) != 0x7e79eaa6) lp++;
960     *lp++ = htonl(POWERPC_NOP);
961     while (ntohl(*lp) != 0x7e5aeba6) lp++;
962     *lp++ = htonl(POWERPC_NOP);
963     while (ntohl(*lp) != 0x7e7aeaa6) lp++;
964     *lp++ = htonl(POWERPC_NOP);
965     while (ntohl(*lp) != 0x7e5beba6) lp++;
966     *lp++ = htonl(POWERPC_NOP);
967     while (ntohl(*lp) != 0x7e7beaa6) lp++;
968     *lp++ = htonl(POWERPC_NOP);
969     while (ntohl(*lp) != 0x7e5feba6) lp++;
970     *lp++ = htonl(POWERPC_NOP);
971     while (ntohl(*lp) != 0x7e7feaa6) lp++;
972     *lp++ = htonl(POWERPC_NOP);
973     while (ntohl(*lp) != 0x7e5ceba6) lp++;
974     *lp++ = htonl(POWERPC_NOP);
975     while (ntohl(*lp) != 0x7e7ceaa6) lp++;
976     *lp++ = htonl(POWERPC_NOP);
977     while (ntohl(*lp) != 0x7e5deba6) lp++;
978     *lp++ = htonl(POWERPC_NOP);
979     while (ntohl(*lp) != 0x7e7deaa6) lp++;
980     *lp++ = htonl(POWERPC_NOP);
981     while (ntohl(*lp) != 0x7e5eeba6) lp++;
982     *lp++ = htonl(POWERPC_NOP);
983     while (ntohl(*lp) != 0x7e7eeaa6) lp++;
984     *lp++ = htonl(POWERPC_NOP);
985    
986     // Jump to 68k emulator
987     static const uint32 jump68k_ofs[] = {0x40c, 0x40c, 0x40c, 0x414, 0x438};
988     lp = (uint32 *)(ROM_BASE + loc + jump68k_ofs[ROMType]);
989     *lp++ = htonl(0x80610634); // lwz r3,0x0634(r1) (pointer to Emulator Data)
990     *lp++ = htonl(0x8081119c); // lwz r4,0x119c(r1) (pointer to opcode table)
991     *lp++ = htonl(0x80011184); // lwz r0,0x1184(r1) (pointer to emulator init routine)
992     *lp++ = htonl(0x7c0903a6); // mtctr r0
993     *lp = htonl(POWERPC_BCTR);
994     return true;
995     }
996    
997    
998     /*
999     * 68k emulator patches
1000     */
1001    
1002     static bool patch_68k_emul(void)
1003     {
1004     uint32 *lp;
1005     uint32 base;
1006    
1007     // Overwrite twi instructions
1008     static const uint32 twi_loc[] = {0x36e680, 0x36e6c0, 0x36e6c0, 0x36e6c0, 0x36e740};
1009     base = twi_loc[ROMType];
1010     lp = (uint32 *)(ROM_BASE + base);
1011     *lp++ = htonl(0x48000000 + 0x36f900 - base); // b 0x36f900 (Emulator start)
1012     *lp++ = htonl(0x48000000 + 0x36fa00 - base - 4); // b 0x36fa00 (Mixed mode)
1013     *lp++ = htonl(0x48000000 + 0x36fb00 - base - 8); // b 0x36fb00 (Reset/FC1E opcode)
1014     *lp++ = htonl(0x48000000 + 0x36fc00 - base - 12); // FE0A opcode
1015     *lp++ = htonl(POWERPC_ILLEGAL); // Interrupt
1016     *lp++ = htonl(POWERPC_ILLEGAL); // ?
1017     *lp++ = htonl(POWERPC_ILLEGAL);
1018     *lp++ = htonl(POWERPC_ILLEGAL);
1019     *lp++ = htonl(POWERPC_ILLEGAL);
1020     *lp++ = htonl(POWERPC_ILLEGAL);
1021     *lp++ = htonl(POWERPC_ILLEGAL);
1022     *lp++ = htonl(POWERPC_ILLEGAL);
1023     *lp++ = htonl(POWERPC_ILLEGAL);
1024     *lp++ = htonl(POWERPC_ILLEGAL);
1025     *lp++ = htonl(POWERPC_ILLEGAL);
1026     *lp = htonl(POWERPC_ILLEGAL);
1027    
1028     #if EMULATED_PPC
1029     // Install EMUL_RETURN, EXEC_RETURN and EMUL_OP opcodes
1030     lp = (uint32 *)(ROM_BASE + 0x380000 + (M68K_EMUL_RETURN << 3));
1031     *lp++ = htonl(POWERPC_EMUL_OP);
1032     *lp++ = htonl(0x4bf66e80); // b 0x366084
1033     *lp++ = htonl(POWERPC_EMUL_OP | 1);
1034     *lp++ = htonl(0x4bf66e78); // b 0x366084
1035     for (int i=0; i<OP_MAX; i++) {
1036     *lp++ = htonl(POWERPC_EMUL_OP | (i + 2));
1037     *lp++ = htonl(0x4bf66e70 - i*8); // b 0x366084
1038     }
1039     #else
1040     // Install EMUL_RETURN, EXEC_RETURN and EMUL_OP opcodes
1041     lp = (uint32 *)(ROM_BASE + 0x380000 + (M68K_EMUL_RETURN << 3));
1042     *lp++ = htonl(0x80000000 + XLM_EMUL_RETURN_PROC); // lwz r0,XLM_EMUL_RETURN_PROC
1043     *lp++ = htonl(0x4bf705fc); // b 0x36f800
1044     *lp++ = htonl(0x80000000 + XLM_EXEC_RETURN_PROC); // lwz r0,XLM_EXEC_RETURN_PROC
1045     *lp++ = htonl(0x4bf705f4); // b 0x36f800
1046     for (int i=0; i<OP_MAX; i++) {
1047     *lp++ = htonl(0x38a00000 + i); // li r5,OP_*
1048     *lp++ = htonl(0x4bf705f4 - i*8); // b 0x36f808
1049     }
1050    
1051     // Extra routines for EMUL_RETURN/EXEC_RETURN/EMUL_OP
1052     lp = (uint32 *)(ROM_BASE + 0x36f800);
1053     *lp++ = htonl(0x7c0803a6); // mtlr r0
1054     *lp++ = htonl(0x4e800020); // blr
1055    
1056     *lp++ = htonl(0x80000000 + XLM_EMUL_OP_PROC); // lwz r0,XLM_EMUL_OP_PROC
1057     *lp++ = htonl(0x7c0803a6); // mtlr r0
1058     *lp = htonl(0x4e800020); // blr
1059     #endif
1060    
1061     // Extra routine for 68k emulator start
1062     lp = (uint32 *)(ROM_BASE + 0x36f900);
1063     *lp++ = htonl(0x7c2903a6); // mtctr r1
1064     *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1065     *lp++ = htonl(0x38210001); // addi r1,r1,1
1066     *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1067     *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1068     *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1069     *lp++ = htonl(0x7cc902a6); // mfctr r6
1070     *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1071     *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1072     *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1073     *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1074     *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1075     *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1076     *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1077     *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1078     *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1079     *lp++ = htonl(0x7da00026); // mfcr r13
1080     *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1081     *lp++ = htonl(0x7d8802a6); // mflr r12
1082     *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1083     *lp++ = htonl(0x814105f0); // lwz r10,0x05f0(r1)
1084     *lp++ = htonl(0x7d4803a6); // mtlr r10
1085     *lp++ = htonl(0x7d8a6378); // mr r10,r12
1086     *lp++ = htonl(0x3d600002); // lis r11,0x0002
1087     *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1088     *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1089     *lp = htonl(0x4e800020); // blr
1090    
1091     // Extra routine for Mixed Mode
1092     lp = (uint32 *)(ROM_BASE + 0x36fa00);
1093     *lp++ = htonl(0x7c2903a6); // mtctr r1
1094     *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1095     *lp++ = htonl(0x38210001); // addi r1,r1,1
1096     *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1097     *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1098     *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1099     *lp++ = htonl(0x7cc902a6); // mfctr r6
1100     *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1101     *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1102     *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1103     *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1104     *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1105     *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1106     *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1107     *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1108     *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1109     *lp++ = htonl(0x7da00026); // mfcr r13
1110     *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1111     *lp++ = htonl(0x7d8802a6); // mflr r12
1112     *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1113     *lp++ = htonl(0x814105f4); // lwz r10,0x05f4(r1)
1114     *lp++ = htonl(0x7d4803a6); // mtlr r10
1115     *lp++ = htonl(0x7d8a6378); // mr r10,r12
1116     *lp++ = htonl(0x3d600002); // lis r11,0x0002
1117     *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1118     *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1119     *lp = htonl(0x4e800020); // blr
1120    
1121     // Extra routine for Reset/FC1E opcode
1122     lp = (uint32 *)(ROM_BASE + 0x36fc00);
1123     *lp++ = htonl(0x7c2903a6); // mtctr r1
1124     *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1125     *lp++ = htonl(0x38210001); // addi r1,r1,1
1126     *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1127     *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1128     *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1129     *lp++ = htonl(0x7cc902a6); // mfctr r6
1130     *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1131     *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1132     *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1133     *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1134     *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1135     *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1136     *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1137     *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1138     *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1139     *lp++ = htonl(0x7da00026); // mfcr r13
1140     *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1141     *lp++ = htonl(0x7d8802a6); // mflr r12
1142     *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1143     *lp++ = htonl(0x814105f4); // lwz r10,0x05f8(r1)
1144     *lp++ = htonl(0x7d4803a6); // mtlr r10
1145     *lp++ = htonl(0x7d8a6378); // mr r10,r12
1146     *lp++ = htonl(0x3d600002); // lis r11,0x0002
1147     *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1148     *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1149     *lp = htonl(0x4e800020); // blr
1150    
1151     // Extra routine for FE0A opcode (QuickDraw 3D needs this)
1152     lp = (uint32 *)(ROM_BASE + 0x36fc00);
1153     *lp++ = htonl(0x7c2903a6); // mtctr r1
1154     *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1155     *lp++ = htonl(0x38210001); // addi r1,r1,1
1156     *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1157     *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1158     *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1159     *lp++ = htonl(0x7cc902a6); // mfctr r6
1160     *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1161     *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1162     *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1163     *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1164     *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1165     *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1166     *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1167     *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1168     *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1169     *lp++ = htonl(0x7da00026); // mfcr r13
1170     *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1171     *lp++ = htonl(0x7d8802a6); // mflr r12
1172     *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1173     *lp++ = htonl(0x814105f4); // lwz r10,0x05fc(r1)
1174     *lp++ = htonl(0x7d4803a6); // mtlr r10
1175     *lp++ = htonl(0x7d8a6378); // mr r10,r12
1176     *lp++ = htonl(0x3d600002); // lis r11,0x0002
1177     *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1178     *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1179     *lp = htonl(0x4e800020); // blr
1180    
1181     // Patch DR emulator to jump to right address when an interrupt occurs
1182     lp = (uint32 *)(ROM_BASE + 0x370000);
1183     while (lp < (uint32 *)(ROM_BASE + 0x380000)) {
1184     if (ntohl(*lp) == 0x4ca80020) // bclr 5,8
1185     goto dr_found;
1186     lp++;
1187     }
1188     D(bug("DR emulator patch location not found\n"));
1189     return false;
1190     dr_found:
1191     lp++;
1192     *lp = htonl(0x48000000 + 0xf000 - (((uint32)lp - ROM_BASE) & 0xffff)); // b DR_CACHE_BASE+0x1f000
1193     lp = (uint32 *)(ROM_BASE + 0x37f000);
1194     *lp++ = htonl(0x3c000000 + ((ROM_BASE + 0x46d0a4) >> 16)); // lis r0,xxx
1195     *lp++ = htonl(0x60000000 + ((ROM_BASE + 0x46d0a4) & 0xffff)); // ori r0,r0,xxx
1196     *lp++ = htonl(0x7c0903a6); // mtctr r0
1197     *lp = htonl(POWERPC_BCTR); // bctr
1198     return true;
1199     }
1200    
1201    
1202     /*
1203     * Nanokernel patches
1204     */
1205    
1206     static bool patch_nanokernel(void)
1207     {
1208     uint32 *lp;
1209    
1210     // Patch Mixed Mode trap
1211     lp = (uint32 *)(ROM_BASE + 0x313c90); // Don't translate virtual->physical
1212     while (ntohl(*lp) != 0x3ba10320) lp++;
1213     lp++;
1214     *lp++ = htonl(0x7f7fdb78); // mr r31,r27
1215     lp++;
1216     *lp = htonl(POWERPC_NOP);
1217    
1218     lp = (uint32 *)(ROM_BASE + 0x313c3c); // Don't activate PPC exception table
1219     while (ntohl(*lp) != 0x39010420) lp++;
1220     *lp++ = htonl(0x39000000 + MODE_NATIVE); // li r8,MODE_NATIVE
1221     *lp = htonl(0x91000000 + XLM_RUN_MODE); // stw r8,XLM_RUN_MODE
1222    
1223     lp = (uint32 *)(ROM_BASE + 0x312e88); // Don't modify MSR to turn on FPU
1224     while (ntohl(*lp) != 0x556b04e2) lp++;
1225     lp -= 4;
1226     *lp++ = htonl(POWERPC_NOP);
1227     lp++;
1228     *lp++ = htonl(POWERPC_NOP);
1229     lp++;
1230     *lp = htonl(POWERPC_NOP);
1231    
1232     lp = (uint32 *)(ROM_BASE + 0x312b3c); // Always save FPU state
1233     while (ntohl(*lp) != 0x81010668) lp++;
1234     lp--;
1235     *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312e88
1236    
1237     lp = (uint32 *)(ROM_BASE + 0x312b44); // Don't read DEC
1238     while (ntohl(*lp) != 0x7ff602a6) lp++;
1239     *lp = htonl(0x3be00000); // li r31,0
1240    
1241     lp = (uint32 *)(ROM_BASE + 0x312b50); // Don't write DEC
1242     while (ntohl(*lp) != 0x7d1603a6) lp++;
1243     #if 1
1244     *lp++ = htonl(POWERPC_NOP);
1245     *lp = htonl(POWERPC_NOP);
1246     #else
1247     *lp++ = htonl(0x39000040); // li r8,0x40
1248     *lp = htonl(0x990600e4); // stb r8,0xe4(r6)
1249     #endif
1250    
1251     lp = (uint32 *)(ROM_BASE + 0x312b9c); // Always restore FPU state
1252     while (ntohl(*lp) != 0x7c00092d) lp++;
1253     lp--;
1254     *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312ddc
1255    
1256     lp = (uint32 *)(ROM_BASE + 0x312a68); // Don't activate 68k exception table
1257     while (ntohl(*lp) != 0x39010360) lp++;
1258     *lp++ = htonl(0x39000000 + MODE_68K); // li r8,MODE_68K
1259     *lp = htonl(0x91000000 + XLM_RUN_MODE); // stw r8,XLM_RUN_MODE
1260    
1261     // Patch 68k emulator trap routine
1262     lp = (uint32 *)(ROM_BASE + 0x312994); // Always restore FPU state
1263     while (ntohl(*lp) != 0x39260040) lp++;
1264     lp--;
1265     *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312dd4
1266    
1267     lp = (uint32 *)(ROM_BASE + 0x312dd8); // Don't modify MSR to turn on FPU
1268     while (ntohl(*lp) != 0x810600e4) lp++;
1269     lp--;
1270     *lp++ = htonl(POWERPC_NOP);
1271     lp += 2;
1272     *lp++ = htonl(POWERPC_NOP);
1273     lp++;
1274     *lp++ = htonl(POWERPC_NOP);
1275     *lp++ = htonl(POWERPC_NOP);
1276     *lp = htonl(POWERPC_NOP);
1277    
1278     // Patch trap return routine
1279     lp = (uint32 *)(ROM_BASE + 0x312c20);
1280     while (ntohl(*lp) != 0x7d5a03a6) lp++;
1281     *lp++ = htonl(0x7d4903a6); // mtctr r10
1282     *lp++ = htonl(0x7daff120); // mtcr r13
1283     *lp = htonl(0x48000000 + 0x8000 - (((uint32)lp - ROM_BASE) & 0xffff)); // b ROM_BASE+0x318000
1284     uint32 xlp = ((uint32)(lp+1) - ROM_BASE) & 0xffff;
1285    
1286     lp = (uint32 *)(ROM_BASE + 0x312c50); // Replace rfi
1287     while (ntohl(*lp) != 0x4c000064) lp++;
1288     *lp = htonl(POWERPC_BCTR);
1289    
1290     lp = (uint32 *)(ROM_BASE + 0x318000);
1291     *lp++ = htonl(0x81400000 + XLM_IRQ_NEST); // lwz r10,XLM_IRQ_NEST
1292     *lp++ = htonl(0x394affff); // subi r10,r10,1
1293     *lp++ = htonl(0x91400000 + XLM_IRQ_NEST); // stw r10,XLM_IRQ_NEST
1294     *lp = htonl(0x48000000 + ((xlp - 0x800c) & 0x03fffffc)); // b ROM_BASE+0x312c2c
1295     /*
1296     // Disable FE0A/FE06 opcodes
1297     lp = (uint32 *)(ROM_BASE + 0x3144ac);
1298     *lp++ = htonl(POWERPC_NOP);
1299     *lp += 8;
1300     */
1301     return true;
1302     }
1303    
1304    
1305     /*
1306     * 68k boot routine patches
1307     */
1308    
1309     static bool patch_68k(void)
1310     {
1311     uint32 *lp;
1312     uint16 *wp;
1313     uint8 *bp;
1314     uint32 base;
1315    
1316     // Remove 68k RESET instruction
1317     static const uint8 reset_dat[] = {0x4e, 0x70};
1318     if ((base = find_rom_data(0xc8, 0x120, reset_dat, sizeof(reset_dat))) == 0) return false;
1319     D(bug("reset %08lx\n", base));
1320     wp = (uint16 *)(ROM_BASE + base);
1321     *wp = htons(M68K_NOP);
1322    
1323     // Fake reading PowerMac ID (via Universal)
1324     static const uint8 powermac_id_dat[] = {0x45, 0xf9, 0x5f, 0xff, 0xff, 0xfc, 0x20, 0x12, 0x72, 0x00};
1325     if ((base = find_rom_data(0xe000, 0x15000, powermac_id_dat, sizeof(powermac_id_dat))) == 0) return false;
1326     D(bug("powermac_id %08lx\n", base));
1327     wp = (uint16 *)(ROM_BASE + base);
1328     *wp++ = htons(0x203c); // move.l #id,d0
1329     *wp++ = htons(0);
1330     // if (ROMType == ROMTYPE_NEWWORLD)
1331     // *wp++ = htons(0x3035); // (PowerMac 9500 ID)
1332     // else
1333     *wp++ = htons(0x3020); // (PowerMac 9500 ID)
1334     *wp++ = htons(0xb040); // cmp.w d0,d0
1335     *wp = htons(0x4ed6); // jmp (a6)
1336    
1337     // Patch UniversalInfo
1338     if (ROMType == ROMTYPE_NEWWORLD) {
1339     static const uint8 univ_info_dat[] = {0x3f, 0xff, 0x04, 0x00};
1340     if ((base = find_rom_data(0x14000, 0x16000, univ_info_dat, sizeof(univ_info_dat))) == 0) return false;
1341     D(bug("universal_info %08lx\n", base));
1342     lp = (uint32 *)(ROM_BASE + base - 0x14);
1343     lp[0x00 >> 2] = htonl(ADDR_MAP_PATCH_SPACE - (base - 0x14));
1344     lp[0x10 >> 2] = htonl(0xcc003d11); // Make it like the PowerMac 9500 UniversalInfo
1345     lp[0x14 >> 2] = htonl(0x3fff0401);
1346     lp[0x18 >> 2] = htonl(0x0300001c);
1347     lp[0x1c >> 2] = htonl(0x000108c4);
1348     lp[0x24 >> 2] = htonl(0xc301bf26);
1349     lp[0x28 >> 2] = htonl(0x00000861);
1350     lp[0x58 >> 2] = htonl(0x30200000);
1351     lp[0x60 >> 2] = htonl(0x0000003d);
1352     } else if (ROMType == ROMTYPE_ZANZIBAR) {
1353     base = 0x12b70;
1354     lp = (uint32 *)(ROM_BASE + base - 0x14);
1355     lp[0x00 >> 2] = htonl(ADDR_MAP_PATCH_SPACE - (base - 0x14));
1356     lp[0x10 >> 2] = htonl(0xcc003d11); // Make it like the PowerMac 9500 UniversalInfo
1357     lp[0x14 >> 2] = htonl(0x3fff0401);
1358     lp[0x18 >> 2] = htonl(0x0300001c);
1359     lp[0x1c >> 2] = htonl(0x000108c4);
1360     lp[0x24 >> 2] = htonl(0xc301bf26);
1361     lp[0x28 >> 2] = htonl(0x00000861);
1362     lp[0x58 >> 2] = htonl(0x30200000);
1363     lp[0x60 >> 2] = htonl(0x0000003d);
1364     }
1365    
1366     // Construct AddrMap for NewWorld ROM
1367     if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_ZANZIBAR) {
1368     lp = (uint32 *)(ROM_BASE + ADDR_MAP_PATCH_SPACE);
1369     memset(lp - 10, 0, 0x128);
1370     lp[-10] = htonl(0x0300001c);
1371     lp[-9] = htonl(0x000108c4);
1372     lp[-4] = htonl(0x00300000);
1373     lp[-2] = htonl(0x11010000);
1374     lp[-1] = htonl(0xf8000000);
1375     lp[0] = htonl(0xffc00000);
1376     lp[2] = htonl(0xf3016000);
1377     lp[3] = htonl(0xf3012000);
1378     lp[4] = htonl(0xf3012000);
1379     lp[24] = htonl(0xf3018000);
1380     lp[25] = htonl(0xf3010000);
1381     lp[34] = htonl(0xf3011000);
1382     lp[38] = htonl(0xf3015000);
1383     lp[39] = htonl(0xf3014000);
1384     lp[43] = htonl(0xf3000000);
1385     lp[48] = htonl(0xf8000000);
1386     }
1387    
1388     // Don't initialize VIA (via Universal)
1389     static const uint8 via_init_dat[] = {0x08, 0x00, 0x00, 0x02, 0x67, 0x00, 0x00, 0x2c, 0x24, 0x68, 0x00, 0x08};
1390     if ((base = find_rom_data(0xe000, 0x15000, via_init_dat, sizeof(via_init_dat))) == 0) return false;
1391     D(bug("via_init %08lx\n", base));
1392     wp = (uint16 *)(ROM_BASE + base + 4);
1393     *wp = htons(0x6000); // bra
1394    
1395     static const uint8 via_init2_dat[] = {0x24, 0x68, 0x00, 0x08, 0x00, 0x12, 0x00, 0x30, 0x4e, 0x71};
1396     if ((base = find_rom_data(0xa000, 0x10000, via_init2_dat, sizeof(via_init2_dat))) == 0) return false;
1397     D(bug("via_init2 %08lx\n", base));
1398     wp = (uint16 *)(ROM_BASE + base);
1399     *wp = htons(0x4ed6); // jmp (a6)
1400    
1401     static const uint8 via_init3_dat[] = {0x22, 0x68, 0x00, 0x08, 0x28, 0x3c, 0x20, 0x00, 0x01, 0x00};
1402     if ((base = find_rom_data(0xa000, 0x10000, via_init3_dat, sizeof(via_init3_dat))) == 0) return false;
1403     D(bug("via_init3 %08lx\n", base));
1404     wp = (uint16 *)(ROM_BASE + base);
1405     *wp = htons(0x4ed6); // jmp (a6)
1406    
1407     // Don't RunDiags, get BootGlobs pointer directly
1408     if (ROMType == ROMTYPE_NEWWORLD) {
1409     static const uint8 run_diags_dat[] = {0x60, 0xff, 0x00, 0x0c};
1410     if ((base = find_rom_data(0x110, 0x128, run_diags_dat, sizeof(run_diags_dat))) == 0) return false;
1411     D(bug("run_diags %08lx\n", base));
1412     wp = (uint16 *)(ROM_BASE + base);
1413     *wp++ = htons(0x4df9); // lea xxx,a6
1414     *wp++ = htons((RAMBase + RAMSize - 0x1c) >> 16);
1415     *wp = htons((RAMBase + RAMSize - 0x1c) & 0xffff);
1416     } else {
1417     static const uint8 run_diags_dat[] = {0x74, 0x00, 0x2f, 0x0e};
1418     if ((base = find_rom_data(0xd0, 0xf0, run_diags_dat, sizeof(run_diags_dat))) == 0) return false;
1419     D(bug("run_diags %08lx\n", base));
1420     wp = (uint16 *)(ROM_BASE + base - 6);
1421     *wp++ = htons(0x4df9); // lea xxx,a6
1422     *wp++ = htons((RAMBase + RAMSize - 0x1c) >> 16);
1423     *wp = htons((RAMBase + RAMSize - 0x1c) & 0xffff);
1424     }
1425    
1426     // Replace NVRAM routines
1427     static const uint8 nvram1_dat[] = {0x48, 0xe7, 0x01, 0x0e, 0x24, 0x68, 0x00, 0x08, 0x08, 0x83, 0x00, 0x1f};
1428     if ((base = find_rom_data(0x7000, 0xc000, nvram1_dat, sizeof(nvram1_dat))) == 0) return false;
1429     D(bug("nvram1 %08lx\n", base));
1430     wp = (uint16 *)(ROM_BASE + base);
1431     *wp++ = htons(M68K_EMUL_OP_XPRAM1);
1432     *wp = htons(M68K_RTS);
1433    
1434     if (ROMType == ROMTYPE_NEWWORLD) {
1435     static const uint8 nvram2_dat[] = {0x48, 0xe7, 0x1c, 0xe0, 0x4f, 0xef, 0xff, 0xb4};
1436     if ((base = find_rom_data(0xa000, 0xd000, nvram2_dat, sizeof(nvram2_dat))) == 0) return false;
1437     D(bug("nvram2 %08lx\n", base));
1438     wp = (uint16 *)(ROM_BASE + base);
1439     *wp++ = htons(M68K_EMUL_OP_XPRAM2);
1440     *wp = htons(0x4ed3); // jmp (a3)
1441    
1442     static const uint8 nvram3_dat[] = {0x48, 0xe7, 0xdc, 0xe0, 0x4f, 0xef, 0xff, 0xb4};
1443     if ((base = find_rom_data(0xa000, 0xd000, nvram3_dat, sizeof(nvram3_dat))) == 0) return false;
1444     D(bug("nvram3 %08lx\n", base));
1445     wp = (uint16 *)(ROM_BASE + base);
1446     *wp++ = htons(M68K_EMUL_OP_XPRAM3);
1447     *wp = htons(0x4ed3); // jmp (a3)
1448    
1449     static const uint8 nvram4_dat[] = {0x4e, 0x56, 0xff, 0xa8, 0x48, 0xe7, 0x1f, 0x38, 0x16, 0x2e, 0x00, 0x13};
1450     if ((base = find_rom_data(0xa000, 0xd000, nvram4_dat, sizeof(nvram4_dat))) == 0) return false;
1451     D(bug("nvram4 %08lx\n", base));
1452     wp = (uint16 *)(ROM_BASE + base + 16);
1453     *wp++ = htons(0x1a2e); // move.b ($000f,a6),d5
1454     *wp++ = htons(0x000f);
1455     *wp++ = htons(M68K_EMUL_OP_NVRAM3);
1456     *wp++ = htons(0x4cee); // movem.l ($ff88,a6),d3-d7/a2-a4
1457     *wp++ = htons(0x1cf8);
1458     *wp++ = htons(0xff88);
1459     *wp++ = htons(0x4e5e); // unlk a6
1460     *wp = htons(M68K_RTS);
1461    
1462     static const uint8 nvram5_dat[] = {0x0c, 0x80, 0x03, 0x00, 0x00, 0x00, 0x66, 0x0a, 0x70, 0x00, 0x21, 0xf8, 0x02, 0x0c, 0x01, 0xe4};
1463     if ((base = find_rom_data(0xa000, 0xd000, nvram5_dat, sizeof(nvram5_dat))) == 0) return false;
1464     D(bug("nvram5 %08lx\n", base));
1465     wp = (uint16 *)(ROM_BASE + base + 6);
1466     *wp = htons(M68K_NOP);
1467    
1468     static const uint8 nvram6_dat[] = {0x2f, 0x0a, 0x24, 0x48, 0x4f, 0xef, 0xff, 0xa0, 0x20, 0x0f};
1469     if ((base = find_rom_data(0x9000, 0xb000, nvram6_dat, sizeof(nvram6_dat))) == 0) return false;
1470     D(bug("nvram6 %08lx\n", base));
1471     wp = (uint16 *)(ROM_BASE + base);
1472     *wp++ = htons(0x7000); // moveq #0,d0
1473     *wp++ = htons(0x2080); // move.l d0,(a0)
1474     *wp++ = htons(0x4228); // clr.b 4(a0)
1475     *wp++ = htons(0x0004);
1476     *wp = htons(M68K_RTS);
1477    
1478     static const uint8 nvram7_dat[] = {0x42, 0x2a, 0x00, 0x04, 0x4f, 0xef, 0x00, 0x60, 0x24, 0x5f, 0x4e, 0x75, 0x4f, 0xef, 0xff, 0xa0, 0x20, 0x0f};
1479     base = find_rom_data(0x9000, 0xb000, nvram7_dat, sizeof(nvram7_dat));
1480     if (base) {
1481     D(bug("nvram7 %08lx\n", base));
1482     wp = (uint16 *)(ROM_BASE + base + 12);
1483     *wp = htons(M68K_RTS);
1484     }
1485     } else {
1486     static const uint8 nvram2_dat[] = {0x4e, 0xd6, 0x06, 0x41, 0x13, 0x00};
1487     if ((base = find_rom_data(0x7000, 0xb000, nvram2_dat, sizeof(nvram2_dat))) == 0) return false;
1488     D(bug("nvram2 %08lx\n", base));
1489     wp = (uint16 *)(ROM_BASE + base + 2);
1490     *wp++ = htons(M68K_EMUL_OP_XPRAM2);
1491     *wp = htons(0x4ed3); // jmp (a3)
1492    
1493     static const uint32 nvram3_loc[] = {0x582f0, 0xa0a0, 0x7e50, 0xa1d0, 0};
1494     wp = (uint16 *)(ROM_BASE + nvram3_loc[ROMType]);
1495     *wp++ = htons(0x202f); // move.l 4(sp),d0
1496     *wp++ = htons(0x0004);
1497     *wp++ = htons(M68K_EMUL_OP_NVRAM1);
1498     if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GAZELLE)
1499     *wp = htons(M68K_RTS);
1500     else {
1501     *wp++ = htons(0x1f40); // move.b d0,8(sp)
1502     *wp++ = htons(0x0008);
1503     *wp++ = htons(0x4e74); // rtd #4
1504     *wp = htons(0x0004);
1505     }
1506    
1507     static const uint32 nvram4_loc[] = {0x58460, 0xa0f0, 0x7f40, 0xa220, 0};
1508     wp = (uint16 *)(ROM_BASE + nvram4_loc[ROMType]);
1509     if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GAZELLE) {
1510     *wp++ = htons(0x202f); // move.l 4(sp),d0
1511     *wp++ = htons(0x0004);
1512     *wp++ = htons(0x122f); // move.b 11(sp),d1
1513     *wp++ = htons(0x000b);
1514     *wp++ = htons(M68K_EMUL_OP_NVRAM2);
1515     *wp = htons(M68K_RTS);
1516     } else {
1517     *wp++ = htons(0x202f); // move.l 6(sp),d0
1518     *wp++ = htons(0x0006);
1519     *wp++ = htons(0x122f); // move.b 4(sp),d1
1520     *wp++ = htons(0x0004);
1521     *wp++ = htons(M68K_EMUL_OP_NVRAM2);
1522     *wp++ = htons(0x4e74); // rtd #6
1523     *wp = htons(0x0006);
1524     }
1525     }
1526    
1527     // Fix MemTop/BootGlobs during system startup
1528     static const uint8 mem_top_dat[] = {0x2c, 0x6c, 0xff, 0xec, 0x2a, 0x4c, 0xdb, 0xec, 0xff, 0xf4};
1529     if ((base = find_rom_data(0x120, 0x180, mem_top_dat, sizeof(mem_top_dat))) == 0) return false;
1530     D(bug("mem_top %08lx\n", base));
1531     wp = (uint16 *)(ROM_BASE + base);
1532     *wp++ = htons(M68K_EMUL_OP_FIX_MEMTOP);
1533     *wp = htons(M68K_NOP);
1534    
1535     // Don't initialize SCC (via 0x1ac)
1536     static const uint8 scc_init_dat[] = {0x48, 0xe7, 0x38, 0xfe};
1537     if ((base = find_rom_data(0x190, 0x1f0, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1538     D(bug("scc_init %08lx\n", base));
1539     wp = (uint16 *)(ROM_BASE + base - 2);
1540     wp = (uint16 *)(ROM_BASE + ntohs(*wp) + base - 2);
1541     *wp++ = htons(M68K_EMUL_OP_RESET);
1542     *wp = htons(M68K_RTS);
1543    
1544     // Don't EnableExtCache (via 0x1f6) and don't DisableIntSources(via 0x1fc)
1545     static const uint8 ext_cache_dat[] = {0x4e, 0x7b, 0x00, 0x02};
1546     if ((base = find_rom_data(0x1d0, 0x230, ext_cache_dat, sizeof(ext_cache_dat))) == 0) return false;
1547     D(bug("ext_cache %08lx\n", base));
1548     lp = (uint32 *)(ROM_BASE + base + 6);
1549     wp = (uint16 *)(ROM_BASE + ntohl(*lp) + base + 6);
1550     *wp = htons(M68K_RTS);
1551     lp = (uint32 *)(ROM_BASE + base + 12);
1552     wp = (uint16 *)(ROM_BASE + ntohl(*lp) + base + 12);
1553     *wp = htons(M68K_RTS);
1554    
1555     // Fake CPU speed test (SetupTimeK)
1556     static const uint8 timek_dat[] = {0x0c, 0x38, 0x00, 0x04, 0x01, 0x2f, 0x6d, 0x3c};
1557     if ((base = find_rom_data(0x400, 0x500, timek_dat, sizeof(timek_dat))) == 0) return false;
1558     D(bug("timek %08lx\n", base));
1559     wp = (uint16 *)(ROM_BASE + base);
1560     *wp++ = htons(0x31fc); // move.w #xxx,TimeDBRA
1561     *wp++ = htons(100);
1562     *wp++ = htons(0x0d00);
1563     *wp++ = htons(0x31fc); // move.w #xxx,TimeSCCDBRA
1564     *wp++ = htons(100);
1565     *wp++ = htons(0x0d02);
1566     *wp++ = htons(0x31fc); // move.w #xxx,TimeSCSIDBRA
1567     *wp++ = htons(100);
1568     *wp++ = htons(0x0b24);
1569     *wp++ = htons(0x31fc); // move.w #xxx,TimeRAMDBRA
1570     *wp++ = htons(100);
1571     *wp++ = htons(0x0cea);
1572     *wp = htons(M68K_RTS);
1573    
1574     // Relocate jump tables ($2000..)
1575     static const uint8 jump_tab_dat[] = {0x41, 0xfa, 0x00, 0x0e, 0x21, 0xc8, 0x20, 0x10, 0x4e, 0x75};
1576     if ((base = find_rom_data(0x3000, 0x6000, jump_tab_dat, sizeof(jump_tab_dat))) == 0) return false;
1577     D(bug("jump_tab %08lx\n", base));
1578     lp = (uint32 *)(ROM_BASE + base + 16);
1579     for (;;) {
1580     D(bug(" %08lx\n", (uint32)lp - ROM_BASE));
1581     while ((ntohl(*lp) & 0xff000000) == 0xff000000) {
1582     *lp = htonl((ntohl(*lp) & (ROM_SIZE-1)) + ROM_BASE);
1583     lp++;
1584     }
1585     while (!ntohl(*lp)) lp++;
1586     if (ntohl(*lp) != 0x41fa000e)
1587     break;
1588     lp += 4;
1589     }
1590    
1591     // Create SysZone at start of Mac RAM (SetSysAppZone, via 0x22a)
1592     static const uint8 sys_zone_dat[] = {0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x40, 0x00};
1593     if ((base = find_rom_data(0x600, 0x900, sys_zone_dat, sizeof(sys_zone_dat))) == 0) return false;
1594     D(bug("sys_zone %08lx\n", base));
1595     lp = (uint32 *)(ROM_BASE + base);
1596     *lp++ = htonl(RAMBase ? RAMBase : 0x3000);
1597     *lp = htonl(RAMBase ? RAMBase + 0x1800 : 0x4800);
1598    
1599     // Set boot stack at RAMBase+4MB and fix logical/physical RAM size (CompBootStack)
1600     // The RAM size fix must be done after InitMemMgr!
1601     static const uint8 boot_stack_dat[] = {0x08, 0x38, 0x00, 0x06, 0x24, 0x0b};
1602     if ((base = find_rom_data(0x580, 0x800, boot_stack_dat, sizeof(boot_stack_dat))) == 0) return false;
1603     D(bug("boot_stack %08lx\n", base));
1604     wp = (uint16 *)(ROM_BASE + base);
1605     *wp++ = htons(0x207c); // move.l #RAMBase+0x3ffffe,a0
1606     *wp++ = htons((RAMBase + 0x3ffffe) >> 16);
1607     *wp++ = htons((RAMBase + 0x3ffffe) & 0xffff);
1608     *wp++ = htons(M68K_EMUL_OP_FIX_MEMSIZE);
1609     *wp = htons(M68K_RTS);
1610    
1611     // Get PowerPC page size (InitVMemMgr, via 0x240)
1612     static const uint8 page_size_dat[] = {0x20, 0x30, 0x81, 0xf2, 0x5f, 0xff, 0xef, 0xd8, 0x00, 0x10};
1613     if ((base = find_rom_data(0xb000, 0x12000, page_size_dat, sizeof(page_size_dat))) == 0) return false;
1614     D(bug("page_size %08lx\n", base));
1615     wp = (uint16 *)(ROM_BASE + base);
1616     *wp++ = htons(0x203c); // move.l #$1000,d0
1617     *wp++ = htons(0);
1618     *wp++ = htons(0x1000);
1619     *wp++ = htons(M68K_NOP);
1620     *wp = htons(M68K_NOP);
1621    
1622     // Gestalt PowerPC page size, RAM size (InitGestalt, via 0x25c)
1623     static const uint8 page_size2_dat[] = {0x26, 0x79, 0x5f, 0xff, 0xef, 0xd8, 0x25, 0x6b, 0x00, 0x10, 0x00, 0x1e};
1624     if ((base = find_rom_data(0x50000, 0x70000, page_size2_dat, sizeof(page_size2_dat))) == 0) return false;
1625     D(bug("page_size2 %08lx\n", base));
1626     wp = (uint16 *)(ROM_BASE + base);
1627     *wp++ = htons(0x257c); // move.l #$1000,$1e(a2)
1628     *wp++ = htons(0);
1629     *wp++ = htons(0x1000);
1630     *wp++ = htons(0x001e);
1631     *wp++ = htons(0x157c); // move.b #PVR,$1d(a2)
1632     *wp++ = htons(PVR >> 16);
1633     *wp++ = htons(0x001d);
1634     *wp++ = htons(0x263c); // move.l #RAMSize,d3
1635     *wp++ = htons(RAMSize >> 16);
1636     *wp++ = htons(RAMSize & 0xffff);
1637     *wp++ = htons(M68K_NOP);
1638     *wp++ = htons(M68K_NOP);
1639     *wp = htons(M68K_NOP);
1640     if (ROMType == ROMTYPE_NEWWORLD)
1641     wp = (uint16 *)(ROM_BASE + base + 0x4a);
1642     else
1643     wp = (uint16 *)(ROM_BASE + base + 0x28);
1644     *wp++ = htons(M68K_NOP);
1645     *wp = htons(M68K_NOP);
1646    
1647     // Gestalt CPU/bus clock speed (InitGestalt, via 0x25c)
1648     if (ROMType == ROMTYPE_ZANZIBAR) {
1649     wp = (uint16 *)(ROM_BASE + 0x5d87a);
1650     *wp++ = htons(0x203c); // move.l #Hz,d0
1651     *wp++ = htons(BusClockSpeed >> 16);
1652     *wp++ = htons(BusClockSpeed & 0xffff);
1653     *wp++ = htons(M68K_NOP);
1654     *wp = htons(M68K_NOP);
1655     wp = (uint16 *)(ROM_BASE + 0x5d888);
1656     *wp++ = htons(0x203c); // move.l #Hz,d0
1657     *wp++ = htons(CPUClockSpeed >> 16);
1658     *wp++ = htons(CPUClockSpeed & 0xffff);
1659     *wp++ = htons(M68K_NOP);
1660     *wp = htons(M68K_NOP);
1661     }
1662    
1663     // Don't write to GC interrupt mask register (via 0x262)
1664     if (ROMType != ROMTYPE_NEWWORLD) {
1665     static const uint8 gc_mask_dat[] = {0x83, 0xa8, 0x00, 0x24, 0x4e, 0x71};
1666     if ((base = find_rom_data(0x13000, 0x20000, gc_mask_dat, sizeof(gc_mask_dat))) == 0) return false;
1667     D(bug("gc_mask %08lx\n", base));
1668     wp = (uint16 *)(ROM_BASE + base);
1669     *wp++ = htons(M68K_NOP);
1670     *wp = htons(M68K_NOP);
1671     wp = (uint16 *)(ROM_BASE + base + 0x40);
1672     *wp++ = htons(M68K_NOP);
1673     *wp = htons(M68K_NOP);
1674     wp = (uint16 *)(ROM_BASE + base + 0x78);
1675     *wp++ = htons(M68K_NOP);
1676     *wp = htons(M68K_NOP);
1677     wp = (uint16 *)(ROM_BASE + base + 0x96);
1678     *wp++ = htons(M68K_NOP);
1679     *wp = htons(M68K_NOP);
1680    
1681     static const uint8 gc_mask2_dat[] = {0x02, 0xa8, 0x00, 0x00, 0x00, 0x80, 0x00, 0x24};
1682     if ((base = find_rom_data(0x13000, 0x20000, gc_mask2_dat, sizeof(gc_mask2_dat))) == 0) return false;
1683     D(bug("gc_mask2 %08lx\n", base));
1684     wp = (uint16 *)(ROM_BASE + base);
1685     for (int i=0; i<5; i++) {
1686     *wp++ = htons(M68K_NOP);
1687     *wp++ = htons(M68K_NOP);
1688     *wp++ = htons(M68K_NOP);
1689     *wp++ = htons(M68K_NOP);
1690     wp += 2;
1691     }
1692     if (ROMType == ROMTYPE_ZANZIBAR) {
1693     for (int i=0; i<6; i++) {
1694     *wp++ = htons(M68K_NOP);
1695     *wp++ = htons(M68K_NOP);
1696     *wp++ = htons(M68K_NOP);
1697     *wp++ = htons(M68K_NOP);
1698     wp += 2;
1699     }
1700     }
1701     }
1702    
1703     // Don't initialize Cuda (via 0x274)
1704     static const uint8 cuda_init_dat[] = {0x08, 0xa9, 0x00, 0x04, 0x16, 0x00, 0x4e, 0x71, 0x13, 0x7c, 0x00, 0x84, 0x1c, 0x00, 0x4e, 0x71};
1705     if ((base = find_rom_data(0xa000, 0x12000, cuda_init_dat, sizeof(cuda_init_dat))) == 0) return false;
1706     D(bug("cuda_init %08lx\n", base));
1707     wp = (uint16 *)(ROM_BASE + base);
1708     *wp++ = htons(M68K_NOP);
1709     *wp++ = htons(M68K_NOP);
1710     *wp++ = htons(M68K_NOP);
1711     *wp++ = htons(M68K_NOP);
1712     *wp++ = htons(M68K_NOP);
1713     *wp++ = htons(M68K_NOP);
1714     *wp = htons(M68K_NOP);
1715    
1716     // Patch GetCPUSpeed (via 0x27a) (some ROMs have two of them)
1717     static const uint8 cpu_speed_dat[] = {0x20, 0x30, 0x81, 0xf2, 0x5f, 0xff, 0xef, 0xd8, 0x00, 0x04, 0x4c, 0x7c};
1718     if ((base = find_rom_data(0x6000, 0x9000, cpu_speed_dat, sizeof(cpu_speed_dat))) == 0) return false;
1719     D(bug("cpu_speed %08lx\n", base));
1720     wp = (uint16 *)(ROM_BASE + base);
1721     *wp++ = htons(0x203c); // move.l #(MHz<<16)|MHz,d0
1722     *wp++ = htons(CPUClockSpeed / 1000000);
1723     *wp++ = htons(CPUClockSpeed / 1000000);
1724     *wp = htons(M68K_RTS);
1725     if ((base = find_rom_data(base, 0x9000, cpu_speed_dat, sizeof(cpu_speed_dat))) != 0) {
1726     D(bug("cpu_speed2 %08lx\n", base));
1727     wp = (uint16 *)(ROM_BASE + base);
1728     *wp++ = htons(0x203c); // move.l #(MHz<<16)|MHz,d0
1729     *wp++ = htons(CPUClockSpeed / 1000000);
1730     *wp++ = htons(CPUClockSpeed / 1000000);
1731     *wp = htons(M68K_RTS);
1732     }
1733    
1734     // Don't poke VIA in InitTimeMgr (via 0x298)
1735     static const uint8 time_via_dat[] = {0x40, 0xe7, 0x00, 0x7c, 0x07, 0x00, 0x28, 0x78, 0x01, 0xd4, 0x43, 0xec, 0x10, 0x00};
1736     if ((base = find_rom_data(0x30000, 0x40000, time_via_dat, sizeof(time_via_dat))) == 0) return false;
1737     D(bug("time_via %08lx\n", base));
1738     wp = (uint16 *)(ROM_BASE + base);
1739     *wp++ = htons(0x4cdf); // movem.l (sp)+,d0-d5/a0-a4
1740     *wp++ = htons(0x1f3f);
1741     *wp = htons(M68K_RTS);
1742    
1743     // Don't read from 0xff800000 (Name Registry, Open Firmware?) (via 0x2a2)
1744     // Remove this if FE03 works!!
1745     static const uint8 open_firmware_dat[] = {0x2f, 0x79, 0xff, 0x80, 0x00, 0x00, 0x00, 0xfc};
1746     if ((base = find_rom_data(0x48000, 0x58000, open_firmware_dat, sizeof(open_firmware_dat))) == 0) return false;
1747     D(bug("open_firmware %08lx\n", base));
1748     wp = (uint16 *)(ROM_BASE + base);
1749     *wp++ = htons(0x2f7c); // move.l #deadbeef,0xfc(a7)
1750     *wp++ = htons(0xdead);
1751     *wp++ = htons(0xbeef);
1752     *wp = htons(0x00fc);
1753     wp = (uint16 *)(ROM_BASE + base + 0x1a);
1754     *wp++ = htons(M68K_NOP); // (FE03 opcode, tries to jump to 0xdeadbeef)
1755     *wp = htons(M68K_NOP);
1756    
1757     // Don't EnableExtCache (via 0x2b2)
1758     static const uint8 ext_cache2_dat[] = {0x4f, 0xef, 0xff, 0xec, 0x20, 0x4f, 0x10, 0xbc, 0x00, 0x01, 0x11, 0x7c, 0x00, 0x1b};
1759     if ((base = find_rom_data(0x13000, 0x20000, ext_cache2_dat, sizeof(ext_cache2_dat))) == 0) return false;
1760     D(bug("ext_cache2 %08lx\n", base));
1761     wp = (uint16 *)(ROM_BASE + base);
1762     *wp = htons(M68K_RTS);
1763    
1764     // Don't install Time Manager task for 60Hz interrupt (Enable60HzInts, via 0x2b8)
1765     if (ROMType == ROMTYPE_NEWWORLD) {
1766     static const uint8 tm_task_dat[] = {0x30, 0x3c, 0x4e, 0x2b, 0xa9, 0xc9};
1767     if ((base = find_rom_data(0x2e0, 0x320, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1768     D(bug("tm_task %08lx\n", base));
1769     wp = (uint16 *)(ROM_BASE + base + 28);
1770     *wp++ = htons(M68K_NOP);
1771     *wp++ = htons(M68K_NOP);
1772     *wp++ = htons(M68K_NOP);
1773     *wp++ = htons(M68K_NOP);
1774     *wp++ = htons(M68K_NOP);
1775     *wp = htons(M68K_NOP);
1776     } else {
1777     static const uint8 tm_task_dat[] = {0x20, 0x3c, 0x73, 0x79, 0x73, 0x61};
1778     if ((base = find_rom_data(0x280, 0x300, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1779     D(bug("tm_task %08lx\n", base));
1780     wp = (uint16 *)(ROM_BASE + base - 6);
1781     *wp++ = htons(M68K_NOP);
1782     *wp++ = htons(M68K_NOP);
1783     *wp = htons(M68K_NOP);
1784     }
1785    
1786     // Don't read PVR from 0x5fffef80 in DriverServicesLib (via 0x316)
1787     if (ROMType != ROMTYPE_NEWWORLD) {
1788     uint32 dsl_offset = find_rom_resource(FOURCC('n','l','i','b'), -16401);
1789     if (ROMType == ROMTYPE_ZANZIBAR) {
1790     static const uint8 dsl_pvr_dat[] = {0x40, 0x82, 0x00, 0x40, 0x38, 0x60, 0xef, 0x80, 0x3c, 0x63, 0x60, 0x00, 0x80, 0x83, 0x00, 0x00, 0x54, 0x84, 0x84, 0x3e};
1791     if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_pvr_dat, sizeof(dsl_pvr_dat))) == 0) return false;
1792     } else {
1793     static const uint8 dsl_pvr_dat[] = {0x3b, 0xc3, 0x00, 0x00, 0x30, 0x84, 0xff, 0xa0, 0x40, 0x82, 0x00, 0x44, 0x80, 0x84, 0xef, 0xe0, 0x54, 0x84, 0x84, 0x3e};
1794     if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_pvr_dat, sizeof(dsl_pvr_dat))) == 0) return false;
1795     }
1796     D(bug("dsl_pvr %08lx\n", base));
1797     lp = (uint32 *)(ROM_BASE + base + 12);
1798     *lp = htonl(0x3c800000 | (PVR >> 16)); // lis r4,PVR
1799    
1800     // Don't read bus clock from 0x5fffef88 in DriverServicesLib (via 0x316)
1801     if (ROMType == ROMTYPE_ZANZIBAR) {
1802     static const uint8 dsl_bus_dat[] = {0x81, 0x07, 0x00, 0x00, 0x39, 0x20, 0x42, 0x40, 0x81, 0x62, 0xff, 0x20};
1803     if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_bus_dat, sizeof(dsl_bus_dat))) == 0) return false;
1804     D(bug("dsl_bus %08lx\n", base));
1805     lp = (uint32 *)(ROM_BASE + base);
1806     *lp = htonl(0x81000000 + XLM_BUS_CLOCK); // lwz r8,(bus clock speed)
1807     } else {
1808     static const uint8 dsl_bus_dat[] = {0x80, 0x83, 0xef, 0xe8, 0x80, 0x62, 0x00, 0x10, 0x7c, 0x04, 0x03, 0x96};
1809     if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_bus_dat, sizeof(dsl_bus_dat))) == 0) return false;
1810     D(bug("dsl_bus %08lx\n", base));
1811     lp = (uint32 *)(ROM_BASE + base);
1812     *lp = htonl(0x80800000 + XLM_BUS_CLOCK); // lwz r4,(bus clock speed)
1813     }
1814     }
1815    
1816     // Don't open InterruptTreeTNT in MotherBoardHAL init in DriverServicesLib init
1817     if (ROMType == ROMTYPE_ZANZIBAR) {
1818     lp = (uint32 *)(ROM_BASE + find_rom_resource(FOURCC('n','l','i','b'), -16408) + 0x16c);
1819     *lp = htonl(0x38600000); // li r3,0
1820     }
1821    
1822     // Patch Name Registry
1823     static const uint8 name_reg_dat[] = {0x70, 0xff, 0xab, 0xeb};
1824     if ((base = find_rom_data(0x300, 0x380, name_reg_dat, sizeof(name_reg_dat))) == 0) return false;
1825     D(bug("name_reg %08lx\n", base));
1826     wp = (uint16 *)(ROM_BASE + base);
1827     *wp = htons(M68K_EMUL_OP_NAME_REGISTRY);
1828    
1829     #if DISABLE_SCSI
1830     // Fake SCSI Manager
1831     // Remove this if SCSI Manager works!!
1832     static const uint8 scsi_mgr_a_dat[] = {0x4e, 0x56, 0x00, 0x00, 0x20, 0x3c, 0x00, 0x00, 0x04, 0x0c, 0xa7, 0x1e};
1833     static const uint8 scsi_mgr_b_dat[] = {0x4e, 0x56, 0x00, 0x00, 0x2f, 0x0c, 0x20, 0x3c, 0x00, 0x00, 0x04, 0x0c, 0xa7, 0x1e};
1834     if ((base = find_rom_data(0x1c000, 0x28000, scsi_mgr_a_dat, sizeof(scsi_mgr_a_dat))) == 0) {
1835     if ((base = find_rom_data(0x1c000, 0x28000, scsi_mgr_b_dat, sizeof(scsi_mgr_b_dat))) == 0) return false;
1836     }
1837     D(bug("scsi_mgr %08lx\n", base));
1838     wp = (uint16 *)(ROM_BASE + base);
1839     *wp++ = htons(0x21fc); // move.l #xxx,0x624 (SCSIAtomic)
1840     *wp++ = htons((ROM_BASE + base + 18) >> 16);
1841     *wp++ = htons((ROM_BASE + base + 18) & 0xffff);
1842     *wp++ = htons(0x0624);
1843     *wp++ = htons(0x21fc); // move.l #xxx,0xe54 (SCSIDispatch)
1844     *wp++ = htons((ROM_BASE + base + 22) >> 16);
1845     *wp++ = htons((ROM_BASE + base + 22) & 0xffff);
1846     *wp++ = htons(0x0e54);
1847     *wp++ = htons(M68K_RTS);
1848     *wp++ = htons(M68K_EMUL_OP_SCSI_ATOMIC);
1849     *wp++ = htons(M68K_RTS);
1850     *wp++ = htons(M68K_EMUL_OP_SCSI_DISPATCH);
1851     *wp = htons(0x4ed0); // jmp (a0)
1852     wp = (uint16 *)(ROM_BASE + base + 0x20);
1853     *wp++ = htons(0x7000); // moveq #0,d0
1854     *wp = htons(M68K_RTS);
1855     #endif
1856    
1857     #if DISABLE_SCSI
1858     // Don't access SCSI variables
1859     // Remove this if SCSI Manager works!!
1860     if (ROMType == ROMTYPE_NEWWORLD) {
1861     static const uint8 scsi_var_dat[] = {0x70, 0x01, 0xa0, 0x89, 0x4a, 0x6e, 0xfe, 0xac, 0x4f, 0xef, 0x00, 0x10, 0x66, 0x00};
1862     if ((base = find_rom_data(0x1f500, 0x1f600, scsi_var_dat, sizeof(scsi_var_dat))) != 0) {
1863     D(bug("scsi_var %08lx\n", base));
1864     wp = (uint16 *)(ROM_BASE + base + 12);
1865     *wp = htons(0x6000); // bra
1866     }
1867    
1868     static const uint8 scsi_var2_dat[] = {0x4e, 0x56, 0xfc, 0x58, 0x48, 0xe7, 0x1f, 0x38};
1869     if ((base = find_rom_data(0x1f700, 0x1f800, scsi_var2_dat, sizeof(scsi_var2_dat))) != 0) {
1870     D(bug("scsi_var2 %08lx\n", base));
1871     wp = (uint16 *)(ROM_BASE + base);
1872     *wp++ = htons(0x7000); // moveq #0,d0
1873     *wp = htons(M68K_RTS); // bra
1874     }
1875     }
1876     #endif
1877    
1878     // Don't wait in ADBInit (via 0x36c)
1879     static const uint8 adb_init_dat[] = {0x08, 0x2b, 0x00, 0x05, 0x01, 0x5d, 0x66, 0xf8};
1880     if ((base = find_rom_data(0x31000, 0x3d000, adb_init_dat, sizeof(adb_init_dat))) == 0) return false;
1881     D(bug("adb_init %08lx\n", base));
1882     wp = (uint16 *)(ROM_BASE + base + 6);
1883     *wp = htons(M68K_NOP);
1884    
1885     // Modify check in InitResources() so that addresses >0x80000000 work
1886     static const uint8 init_res_dat[] = {0x4a, 0xb8, 0x0a, 0x50, 0x6e, 0x20};
1887     if ((base = find_rom_data(0x78000, 0x8c000, init_res_dat, sizeof(init_res_dat))) == 0) return false;
1888     D(bug("init_res %08lx\n", base));
1889     bp = (uint8 *)(ROM_BASE + base + 4);
1890     *bp = 0x66;
1891    
1892     // Modify vCheckLoad() so that we can patch resources (68k Resource Manager)
1893     static const uint8 check_load_dat[] = {0x20, 0x78, 0x07, 0xf0, 0x4e, 0xd0};
1894     if ((base = find_rom_data(0x78000, 0x8c000, check_load_dat, sizeof(check_load_dat))) == 0) return false;
1895     D(bug("check_load %08lx\n", base));
1896     wp = (uint16 *)(ROM_BASE + base);
1897     *wp++ = htons(M68K_JMP);
1898     *wp++ = htons((ROM_BASE + CHECK_LOAD_PATCH_SPACE) >> 16);
1899     *wp = htons((ROM_BASE + CHECK_LOAD_PATCH_SPACE) & 0xffff);
1900     wp = (uint16 *)(ROM_BASE + CHECK_LOAD_PATCH_SPACE);
1901     *wp++ = htons(0x2f03); // move.l d3,-(a7)
1902     *wp++ = htons(0x2078); // move.l $07f0,a0
1903     *wp++ = htons(0x07f0);
1904     *wp++ = htons(M68K_JSR_A0);
1905     *wp++ = htons(M68K_EMUL_OP_CHECKLOAD);
1906     *wp = htons(M68K_RTS);
1907    
1908     // Replace .Sony driver
1909     sony_offset = find_rom_resource(FOURCC('D','R','V','R'), 4);
1910     if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_NEWWORLD)
1911     sony_offset = find_rom_resource(FOURCC('D','R','V','R'), 4, true); // First DRVR 4 is .MFMFloppy
1912     if (sony_offset == 0) {
1913     sony_offset = find_rom_resource(FOURCC('n','d','r','v'), -20196); // NewWorld 1.6 has "PCFloppy" ndrv
1914     if (sony_offset == 0)
1915     return false;
1916     lp = (uint32 *)(ROM_BASE + rsrc_ptr + 8);
1917     *lp = htonl(FOURCC('D','R','V','R'));
1918     wp = (uint16 *)(ROM_BASE + rsrc_ptr + 12);
1919     *wp = htons(4);
1920     }
1921     D(bug("sony_offset %08lx\n", sony_offset));
1922     memcpy((void *)(ROM_BASE + sony_offset), sony_driver, sizeof(sony_driver));
1923    
1924     // Install .Disk and .AppleCD drivers
1925     memcpy((void *)(ROM_BASE + sony_offset + 0x100), disk_driver, sizeof(disk_driver));
1926     memcpy((void *)(ROM_BASE + sony_offset + 0x200), cdrom_driver, sizeof(cdrom_driver));
1927    
1928     // Install serial drivers
1929     memcpy((void *)(ROM_BASE + sony_offset + 0x300), ain_driver, sizeof(ain_driver));
1930     memcpy((void *)(ROM_BASE + sony_offset + 0x400), aout_driver, sizeof(aout_driver));
1931     memcpy((void *)(ROM_BASE + sony_offset + 0x500), bin_driver, sizeof(bin_driver));
1932     memcpy((void *)(ROM_BASE + sony_offset + 0x600), bout_driver, sizeof(bout_driver));
1933    
1934     // Copy icons to ROM
1935     SonyDiskIconAddr = ROM_BASE + sony_offset + 0x800;
1936     memcpy((void *)(ROM_BASE + sony_offset + 0x800), SonyDiskIcon, sizeof(SonyDiskIcon));
1937     SonyDriveIconAddr = ROM_BASE + sony_offset + 0xa00;
1938     memcpy((void *)(ROM_BASE + sony_offset + 0xa00), SonyDriveIcon, sizeof(SonyDriveIcon));
1939     DiskIconAddr = ROM_BASE + sony_offset + 0xc00;
1940     memcpy((void *)(ROM_BASE + sony_offset + 0xc00), DiskIcon, sizeof(DiskIcon));
1941     CDROMIconAddr = ROM_BASE + sony_offset + 0xe00;
1942     memcpy((void *)(ROM_BASE + sony_offset + 0xe00), CDROMIcon, sizeof(CDROMIcon));
1943    
1944     // Patch driver install routine
1945     static const uint8 drvr_install_dat[] = {0xa7, 0x1e, 0x21, 0xc8, 0x01, 0x1c, 0x4e, 0x75};
1946     if ((base = find_rom_data(0xb00, 0xd00, drvr_install_dat, sizeof(drvr_install_dat))) == 0) return false;
1947     D(bug("drvr_install %08lx\n", base));
1948     wp = (uint16 *)(ROM_BASE + base + 8);
1949     *wp++ = htons(M68K_EMUL_OP_INSTALL_DRIVERS);
1950     *wp = htons(M68K_RTS);
1951    
1952     // Don't install serial drivers from ROM
1953     if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_NEWWORLD) {
1954     wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('S','E','R','D'), 0));
1955     *wp = htons(M68K_RTS);
1956     } else {
1957     wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('s','l','0','5'), 2) + 0xc4);
1958     *wp++ = htons(M68K_NOP);
1959     *wp++ = htons(M68K_NOP);
1960     *wp++ = htons(M68K_NOP);
1961     *wp++ = htons(M68K_NOP);
1962     *wp = htons(0x7000); // moveq #0,d0
1963     wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('s','l','0','5'), 2) + 0x8ee);
1964     *wp = htons(M68K_NOP);
1965     }
1966     uint32 nsrd_offset = find_rom_resource(FOURCC('n','s','r','d'), 1);
1967     if (nsrd_offset) {
1968     lp = (uint32 *)(ROM_BASE + rsrc_ptr + 8);
1969     *lp = htonl(FOURCC('x','s','r','d'));
1970     }
1971    
1972     // Replace ADBOp()
1973     memcpy((void *)(ROM_BASE + find_rom_trap(0xa07c)), adbop_patch, sizeof(adbop_patch));
1974    
1975     // Replace Time Manager
1976     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa058));
1977     *wp++ = htons(M68K_EMUL_OP_INSTIME);
1978     *wp = htons(M68K_RTS);
1979     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa059));
1980     *wp++ = htons(0x40e7); // move sr,-(sp)
1981     *wp++ = htons(0x007c); // ori #$0700,sr
1982     *wp++ = htons(0x0700);
1983     *wp++ = htons(M68K_EMUL_OP_RMVTIME);
1984     *wp++ = htons(0x46df); // move (sp)+,sr
1985     *wp = htons(M68K_RTS);
1986     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa05a));
1987     *wp++ = htons(0x40e7); // move sr,-(sp)
1988     *wp++ = htons(0x007c); // ori #$0700,sr
1989     *wp++ = htons(0x0700);
1990     *wp++ = htons(M68K_EMUL_OP_PRIMETIME);
1991     *wp++ = htons(0x46df); // move (sp)+,sr
1992     *wp = htons(M68K_RTS);
1993     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa093));
1994     *wp++ = htons(M68K_EMUL_OP_MICROSECONDS);
1995     *wp = htons(M68K_RTS);
1996    
1997     // Disable Egret Manager
1998     static const uint8 egret_dat[] = {0x2f, 0x30, 0x81, 0xe2, 0x20, 0x10, 0x00, 0x18};
1999     if ((base = find_rom_data(0xa000, 0x10000, egret_dat, sizeof(egret_dat))) == 0) return false;
2000     D(bug("egret %08lx\n", base));
2001     wp = (uint16 *)(ROM_BASE + base);
2002     *wp++ = htons(0x7000);
2003     *wp = htons(M68K_RTS);
2004    
2005     // Don't call FE0A opcode in Shutdown Manager
2006     static const uint8 shutdown_dat[] = {0x40, 0xe7, 0x00, 0x7c, 0x07, 0x00, 0x48, 0xe7, 0x3f, 0x00, 0x2c, 0x00, 0x2e, 0x01};
2007     if ((base = find_rom_data(0x30000, 0x40000, shutdown_dat, sizeof(shutdown_dat))) == 0) return false;
2008     D(bug("shutdown %08lx\n", base));
2009     wp = (uint16 *)(ROM_BASE + base);
2010     if (ROMType == ROMTYPE_ZANZIBAR)
2011     *wp = htons(M68K_RTS);
2012     else
2013     wp[-2] = htons(0x6000); // bra
2014    
2015     // Patch PowerOff()
2016     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa05b)); // PowerOff()
2017     *wp = htons(M68K_EMUL_RETURN);
2018    
2019     // Patch VIA interrupt handler
2020     static const uint8 via_int_dat[] = {0x70, 0x7f, 0xc0, 0x29, 0x1a, 0x00, 0xc0, 0x29, 0x1c, 0x00};
2021     if ((base = find_rom_data(0x13000, 0x1c000, via_int_dat, sizeof(via_int_dat))) == 0) return false;
2022     D(bug("via_int %08lx\n", base));
2023     uint32 level1_int = ROM_BASE + base;
2024     wp = (uint16 *)level1_int; // Level 1 handler
2025     *wp++ = htons(0x7002); // moveq #2,d0 (60Hz interrupt)
2026     *wp++ = htons(M68K_NOP);
2027     *wp++ = htons(M68K_NOP);
2028     *wp++ = htons(M68K_NOP);
2029     *wp = htons(M68K_NOP);
2030    
2031     static const uint8 via_int2_dat[] = {0x13, 0x7c, 0x00, 0x02, 0x1a, 0x00, 0x4e, 0x71, 0x52, 0xb8, 0x01, 0x6a};
2032     if ((base = find_rom_data(0x10000, 0x18000, via_int2_dat, sizeof(via_int2_dat))) == 0) return false;
2033     D(bug("via_int2 %08lx\n", base));
2034     wp = (uint16 *)(ROM_BASE + base); // 60Hz handler
2035     *wp++ = htons(M68K_EMUL_OP_IRQ);
2036     *wp++ = htons(0x4a80); // tst.l d0
2037     *wp++ = htons(0x6700); // beq xxx
2038     *wp = htons(0xffe8);
2039    
2040     if (ROMType == ROMTYPE_NEWWORLD) {
2041     static const uint8 via_int3_dat[] = {0x48, 0xe7, 0xf0, 0xf0, 0x76, 0x01, 0x60, 0x26};
2042     if ((base = find_rom_data(0x15000, 0x18000, via_int3_dat, sizeof(via_int3_dat))) == 0) return false;
2043     D(bug("via_int3 %08lx\n", base));
2044     wp = (uint16 *)(ROM_BASE + base); // CHRP level 1 handler
2045     *wp++ = htons(M68K_JMP);
2046     *wp++ = htons((level1_int - 12) >> 16);
2047     *wp = htons((level1_int - 12) & 0xffff);
2048     }
2049    
2050     // Patch PutScrap() for clipboard exchange with host OS
2051     uint32 put_scrap = find_rom_trap(0xa9fe); // PutScrap()
2052     wp = (uint16 *)(ROM_BASE + PUT_SCRAP_PATCH_SPACE);
2053     *wp++ = htons(M68K_EMUL_OP_PUT_SCRAP);
2054     *wp++ = htons(M68K_JMP);
2055     *wp++ = htons((ROM_BASE + put_scrap) >> 16);
2056     *wp++ = htons((ROM_BASE + put_scrap) & 0xffff);
2057     lp = (uint32 *)(ROM_BASE + 0x22);
2058     lp = (uint32 *)(ROM_BASE + ntohl(*lp));
2059     lp[0xa9fe & 0x3ff] = htonl(PUT_SCRAP_PATCH_SPACE);
2060    
2061     // Patch GetScrap() for clipboard exchange with host OS
2062     uint32 get_scrap = find_rom_trap(0xa9fd); // GetScrap()
2063     wp = (uint16 *)(ROM_BASE + GET_SCRAP_PATCH_SPACE);
2064     *wp++ = htons(M68K_EMUL_OP_GET_SCRAP);
2065     *wp++ = htons(M68K_JMP);
2066     *wp++ = htons((ROM_BASE + get_scrap) >> 16);
2067     *wp++ = htons((ROM_BASE + get_scrap) & 0xffff);
2068     lp = (uint32 *)(ROM_BASE + 0x22);
2069     lp = (uint32 *)(ROM_BASE + ntohl(*lp));
2070     lp[0xa9fd & 0x3ff] = htonl(GET_SCRAP_PATCH_SPACE);
2071    
2072     #if __BEOS__
2073     // Patch SynchIdleTime()
2074     if (PrefsFindBool("idlewait")) {
2075     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xabf7) + 4); // SynchIdleTime()
2076     D(bug("SynchIdleTime at %08lx\n", wp));
2077     if (ntohs(*wp) == 0x2078) {
2078     *wp++ = htons(M68K_EMUL_OP_IDLE_TIME);
2079     *wp = htons(M68K_NOP);
2080     } else {
2081     D(bug("SynchIdleTime patch not installed\n"));
2082     }
2083     }
2084     #endif
2085    
2086     // Construct list of all sifters used by sound components in ROM
2087     D(bug("Searching for sound components with type sdev in ROM\n"));
2088     uint32 thing = find_rom_resource(FOURCC('t','h','n','g'));
2089     while (thing) {
2090     thing += ROM_BASE;
2091     D(bug(" found %c%c%c%c %c%c%c%c\n", ReadMacInt8(thing), ReadMacInt8(thing + 1), ReadMacInt8(thing + 2), ReadMacInt8(thing + 3), ReadMacInt8(thing + 4), ReadMacInt8(thing + 5), ReadMacInt8(thing + 6), ReadMacInt8(thing + 7)));
2092     if (ReadMacInt32(thing) == FOURCC('s','d','e','v') && ReadMacInt32(thing + 4) == FOURCC('s','i','n','g')) {
2093     WriteMacInt32(thing + 4, FOURCC('a','w','g','c'));
2094     D(bug(" found sdev component at offset %08x in ROM\n", thing));
2095     AddSifter(ReadMacInt32(thing + componentResType), ReadMacInt16(thing + componentResID));
2096     if (ReadMacInt32(thing + componentPFCount))
2097     AddSifter(ReadMacInt32(thing + componentPFResType), ReadMacInt16(thing + componentPFResID));
2098     }
2099     thing = find_rom_resource(FOURCC('t','h','n','g'), 4711, true);
2100     }
2101    
2102     // Patch component code
2103     D(bug("Patching sifters in ROM\n"));
2104     for (int i=0; i<num_sifters; i++) {
2105     if ((thing = find_rom_resource(sifter_list[i].type, sifter_list[i].id)) != 0) {
2106     D(bug(" patching type %08x, id %d\n", sifter_list[i].type, sifter_list[i].id));
2107     // Install 68k glue code
2108     uint16 *wp = (uint16 *)(ROM_BASE + thing);
2109     *wp++ = htons(0x4e56); *wp++ = htons(0x0000); // link a6,#0
2110     *wp++ = htons(0x48e7); *wp++ = htons(0x8018); // movem.l d0/a3-a4,-(a7)
2111     *wp++ = htons(0x266e); *wp++ = htons(0x000c); // movea.l $c(a6),a3
2112     *wp++ = htons(0x286e); *wp++ = htons(0x0008); // movea.l $8(a6),a4
2113     *wp++ = htons(M68K_EMUL_OP_AUDIO_DISPATCH);
2114     *wp++ = htons(0x2d40); *wp++ = htons(0x0010); // move.l d0,$10(a6)
2115     *wp++ = htons(0x4cdf); *wp++ = htons(0x1801); // movem.l (a7)+,d0/a3-a4
2116     *wp++ = htons(0x4e5e); // unlk a6
2117     *wp++ = htons(0x4e74); *wp++ = htons(0x0008); // rtd #8
2118     }
2119     }
2120     return true;
2121     }
2122    
2123    
2124     /*
2125     * Install .Sony, disk and CD-ROM drivers
2126     */
2127    
2128     void InstallDrivers(void)
2129     {
2130     D(bug("Installing drivers...\n"));
2131     M68kRegisters r;
2132     uint8 pb[SIZEOF_IOParam];
2133    
2134     // Open .Sony driver
2135     WriteMacInt8((uint32)pb + ioPermssn, 0);
2136     WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Sony");
2137     r.a[0] = (uint32)pb;
2138     Execute68kTrap(0xa000, &r); // Open()
2139    
2140     // Install disk driver
2141     r.a[0] = ROM_BASE + sony_offset + 0x100;
2142     r.d[0] = (uint32)DiskRefNum;
2143     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2144     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~DiskRefNum * 4); // Get driver handle from Unit Table
2145     Execute68kTrap(0xa029, &r); // HLock()
2146     uint32 dce = ReadMacInt32(r.a[0]);
2147     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x100);
2148     WriteMacInt16(dce + dCtlFlags, DiskDriverFlags);
2149    
2150     // Open disk driver
2151     WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Disk");
2152     r.a[0] = (uint32)pb;
2153     Execute68kTrap(0xa000, &r); // Open()
2154    
2155     // Install CD-ROM driver unless nocdrom option given
2156     if (!PrefsFindBool("nocdrom")) {
2157    
2158     // Install CD-ROM driver
2159     r.a[0] = ROM_BASE + sony_offset + 0x200;
2160     r.d[0] = (uint32)CDROMRefNum;
2161     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2162     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~CDROMRefNum * 4); // Get driver handle from Unit Table
2163     Execute68kTrap(0xa029, &r); // HLock()
2164     dce = ReadMacInt32(r.a[0]);
2165     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x200);
2166     WriteMacInt16(dce + dCtlFlags, CDROMDriverFlags);
2167    
2168     // Open CD-ROM driver
2169     WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\010.AppleCD");
2170     r.a[0] = (uint32)pb;
2171     Execute68kTrap(0xa000, &r); // Open()
2172     }
2173    
2174     // Install serial drivers
2175     r.a[0] = ROM_BASE + sony_offset + 0x300;
2176     r.d[0] = (uint32)-6;
2177     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2178     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-6) * 4); // Get driver handle from Unit Table
2179     Execute68kTrap(0xa029, &r); // HLock()
2180     dce = ReadMacInt32(r.a[0]);
2181     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x300);
2182     WriteMacInt16(dce + dCtlFlags, 0x4d00);
2183    
2184     r.a[0] = ROM_BASE + sony_offset + 0x400;
2185     r.d[0] = (uint32)-7;
2186     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2187     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-7) * 4); // Get driver handle from Unit Table
2188     Execute68kTrap(0xa029, &r); // HLock()
2189     dce = ReadMacInt32(r.a[0]);
2190     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x400);
2191     WriteMacInt16(dce + dCtlFlags, 0x4e00);
2192    
2193     r.a[0] = ROM_BASE + sony_offset + 0x500;
2194     r.d[0] = (uint32)-8;
2195     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2196     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-8) * 4); // Get driver handle from Unit Table
2197     Execute68kTrap(0xa029, &r); // HLock()
2198     dce = ReadMacInt32(r.a[0]);
2199     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x500);
2200     WriteMacInt16(dce + dCtlFlags, 0x4d00);
2201    
2202     r.a[0] = ROM_BASE + sony_offset + 0x600;
2203     r.d[0] = (uint32)-9;
2204     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2205     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-9) * 4); // Get driver handle from Unit Table
2206     Execute68kTrap(0xa029, &r); // HLock()
2207     dce = ReadMacInt32(r.a[0]);
2208     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x600);
2209     WriteMacInt16(dce + dCtlFlags, 0x4e00);
2210     }