[Michael Schmitt]
Attached is a patch to SheepShaver to fix memory allocation problems when OS X 10.5 is the host. It also relaxes the 512 MB RAM limit on OS X hosts.


Problem
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Some users have been unable to run SheepShaver on OS X 10.5 (Leopard) hosts. The symptom is error "ERROR: Cannot map RAM: File already exists".

SheepShaver allocates RAM at fixed addresses. If it is running in "Real" addressing mode, and can't allocate at address 0, then it was hard-coded to allocate the RAM area at 0x20000000. The ROM area as allocated at 0x40800000.

The normal configuration is for SheepShaver to run under SDL, which is a Cocoa wrapper. By the time SheepShaver does its memory allocations, the Cocoa application has already started. The result is the SheepShaver memory address space already contains libraries, fonts, Input Managers, and IOKit areas.

On Leopard hosts these areas can land on the same addresses SheepShaver needs, so SheepShaver's memory allocation fails.


Solution
--------
The approach is to change SheepShaver (on Unix & OS X hosts) to allocate the RAM area anywhere it can find the space, rather than at a fixed address.

This could result in the RAM allocated higher than the ROM area, which causes a crash. To prevent this from occurring, the RAM and ROM areas are allocated contiguously.

Previously the ROM starting address was a constant ROM_BASE, which was used throughout the source files. The ROM start address is now a variable ROMBase. ROMBase is allocated and set by main_*.cpp just like RAMBase.

A side-effect of this change is that it lifts the 512 MB RAM limit for OS X hosts. The limit was because the fixed RAM and ROM addresses were such that the RAM could only be 512 MB before it overlapped the ROM area.


Impact
------
The change to make ROMBase a variable is throughout all hosts & addressing modes.

The RAM and ROM areas will only shift when run on Unix & OS X hosts, otherwise the same fixed allocation address is used as before.

This change is limited to "Real" addressing mode. Unlike Basilisk II, SheepShaver *pre-calculates* the offset for "Direct" addressing mode; the offset is compiled into the program. If the RAM address were allowed to shift, it could result in the RAM area wrapping around address 0.


Changes to main_unix.cpp
------------------------
1. Real addressing mode no longer defines a RAM_BASE constant.

2. The base address of the Mac ROM (ROMBase) is defined and exported by this program.

3. Memory management helper vm_mac_acquire is renamed to vm_mac_acquire_fixed. Added a new memory management helper vm_mac_acquire, which allocates memory at any address.

4. Changed and rearranged the allocation of RAM and ROM areas.

Before it worked like this:

  - Allocate ROM area
  - If can, attempt to allocate RAM at address zero
  - If RAM not allocated at 0, allocate at fixed address

We still want to try allocating the RAM at zero, and if using DIRECT addressing we're still going to use the fixed addresses. So we don't know where the ROM should be until after we do the RAM. The new logic is:

  - If can, attempt to allocate RAM at address zero
  - If RAM not allocated at 0
      if REAL addressing
         allocate RAM and ROM together. The ROM address is aligned to a 1 MB boundary
      else (direct addressing)
         allocate RAM at fixed address
  - If ROM hasn't been allocated yet, allocate at fixed address

5. Calculate ROMBase and ROMBaseHost based on where the ROM was loaded.

6. There is a crash if the RAM is allocated too high. To try and catch this, check if it was allocated higher than the kernel data address.

7. Change subsequent code from using constant ROM_BASE to variable ROMBase.


Changes to Other Programs
-------------------------
emul_op.cpp, main.cpp, name_registery.cpp, rom_patches.cpp, rsrc_patches.cpp, emul_ppc.cpp, sheepshaver_glue.cpp, ppc-translate-cpp:
Change from constant ROM_BASE to variable ROMBase.

ppc_asm.S: It was setting register to a hard-coded literal address: 0x40b0d000. Changed to set it to ROMBase + 0x30d000.

ppc_asm.tmpl: It defined a macro ASM_LO16 but it assumed that the macro would always be used with operands that included a register specification. This is not true. Moved the register specification from the macro to the macro invocations.

main_beos.cpp, main_windows.cpp: Since the subprograms are all expecting a variable ROMBase, all the main_*.cpp pgrams have to define and export it. The ROM_BASE constant is moved here for consistency. The mains for beos and windows just allocate the ROM at the same fixed address as before, set ROMBaseHost and ROMBase to that address, and then use ROMBase for the subsequent code.

cpu_emulation.h: removed ROM_BASE constant. This value is moved to the main_*.cpp modules, to be consistent with RAM_BASE.

user_strings_unix.cpp, user_strings_unix.h: Added new error messages related to errors that occur when the RAM and ROM are allocated anywhere.

Sync with new SIGSEGV API.

Remove specialised decoders. This will be done differently, if necessary.

Optimize generated code to NQD & CheckLoad functions. They don't call into
68k or MacOS code, so they don't need to be a termination point. i.e. don't
split into two basic blocks and thus avoid a full hash search.

Also add missing NQD_unknown_hook NativeOp from previous commit.

Add patches for native GetNamedResource() and Get1NamedResource(). This will
be useful to fix a bug in the AppleShare extension (see DRVR .AFPTranslator
in Basilisk II)

Unrelated improvement: call sheepshaver_cpu::get_resource() directly, don't
get it through another global function.

Align PowerPC registers struct manually, i.e. don't depend on non-portable
compiler extensions (e.g. GCC __attribute__((aligned(N)))).

Improve idle wait mechanism. Now, the emulator thread can be suspended
(idle_wait) until events arrived and notified through TriggerInterrupt().
i.e. we no longer sleep a fixed amount of time on platforms that support
a thread wait/signal mechanism.

Fix CR save/restore in EmulOp thunk. I don't know what it fixes for real
but that was definitely wrong to only preserve CR2 there.

it makes more sense to dump the crash dump header to stderr

Preserve all necessary registers on interrupt, thus also permitting nested
interrupts to occur. SheepShaver locks should now be reduced.

add FP regs & state to preserved context on interrupt

16-byte aligned memory allocator only for sheepshaver_cpu

Implement Direct Addressing mode similarly to Basilisk II. This is to get
SheepShaver working on OSes that don't support maipping of Low Memory globals
at 0x00000000, e.g. Windows.

Enable ethernet everywhere, several users got it to work. Hangs may be
unrelated to ethernet code anyway and ethernet driver should be endian
safe nowadays.

Performance of VOSF is heuristically determined at run-time, so have to
initialize SIGSEGV handlers early, as in Basilisk II. Besides, also add
missing call to vm_init() in case host system doesn't have MAP_ANON.

Don't handle XLM_IRQ_NEST atomically in emulated mode. That's useless since
this variable is modified only within a single thread and interrupts are
not handled asynchronously.

STATS: Account for all interrupts, but still count native interrupts. It
turns out that for a regular bootup sequence to the Finder, less than 30%
interrupts triggered were in native mode.

Default EMUL_TIME_STATS to 0, end user probably doesn't want garbage to
be printed to his console.

Fix NativeOp code generation, especially in PPC_REENTRANT_JIT mode

Don't allow "recursive" NanoKernel interrupts

Make NativeOp() handler a sheepshaver_cpu handler, thus getting rid of ugly
GPR macro definition.

Make the JIT engine somewhat reentrant. This brings a massive performance
boost for applications that cause many Execute68k(). e.g. audio in PlayerPRO.

Handle SAFE_INTERRUPT_PPC to check possible nested calls (and this happens)

NQD: use ReadMacInt*() and WriteMacInt*() accessors, i.e. code should now
be little-endian and 64-bit safe.

Start Native QuickDraw acceleration

Make SheepShaver work with OS 8.6 out-of-the-box with no extra patch for
the time being. i.e. ignore writes to the zero page when faking SCSIGlobals

GCC 3.4 does not allow the lazy_allocator instantiation, the other form is
not supported by any GCC but ICC accepts it.

Generate PowerPC code wrapping GetResource() replacements. That way, it's
a normal PPC function invocation that can be JIT compiled to native code
instead of nesting execute() calls which may lead to use the interpreter
(this took around 11% of total execution time on boot, downto 3%).

Also, optimize some SheepShaver EmulOps and actually report non-CTI.

Match Linux/ppc native version better: jump to ROM with EmulatorData in r4,
preserve CR & XER registers on EmulOp.

Use a unique ExecuteNative() interface in any case, i.e. native & emulated

Add "jit" prefs item. Fix PPC_DECODE_CACHE version to fill in new min_pc &
max_pc members of block info. Increase -finline-limit to 10000 for older gcc

Merge in-progress PowerPC "JIT1" engine for AMD64, IA-32, PPC.

The merge probably got wrong as there are some problems probably due to the
experiment begining with CR deferred evaluation. With nbench/ppc, performance
improvement was around 2x. With nbench on x86, performance improvement was
around 4x on average.

Incompatible change: instr_info_t has a new field in the middle. But since
insertion of PPC_I(XXX) identifiers is auto-generated, there is no problem.

- XLM_IRQ_NEST is always in native byte order format since any write to
  this variable go through {Enable,Disable}Interrupt().
- Add Ether thunks but only for WORDS_BIGENDIAN case since we do need more
complicated translation functions.

Implement partial block cache invalidation. Rewrite core cached blocks
execution loop with a Duff's device. Gather some predecode time statistics.
This shows that only around 2% of total emulation time is spent for
predecoding the instructions.

Integrate spcflags handling code to kpx_cpu core. We can also remove
oldish EXEC_RETURN handling with a throw/catch mechanism since we
do have a dependency on extra conditions (invalidated cache) that
prevents fast execution loops.

Rewrite interrupts handling code so that the emulator can work with a
predecode cache. This implies to run in interpreted mode only while
processing EmulOps or other native (nested) runs.

Note that the FLIGHT_RECORDER with a predecode cache gets slower than
without caching at all.

Preserve CR in execute_68k(). This enables MacOS 8.6 to work. ;-)

- Minor optimization to execute_ppc() as we apparently don't need to move
  target PC into CTR.
- Fix breakage introduced during little endian fixing. We now assume that
  MacOS doesn't rely on any PPC register that may have been saved on top
  of it stack. i.e. register state is saved onto native stack.

- Share EmulatorData & KernelData struct definitions
- Introduce new SheepShaver data area for alternate stacks, thunks, etc.
- Experimental asynchronous interrupts handling. This improves performance
  by 30% but some (rare) lockups may occur. To be debugged!

Try to handle XLM_IRQ_NEST atomically in emulated PPC views. Fix placement
of fake SCSIGlobals (disabled for now). Switch back to mono core emulation
until things are debugged enough. Implement get_resource() et al.