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root/cebix/SheepShaver/src/kpx_cpu/sheepshaver_glue.cpp

Comparing SheepShaver/src/kpx_cpu/sheepshaver_glue.cpp (file contents):
Revision 1.49 by gbeauche, 2004-07-11T06:42:28Z vs.
Revision 1.65 by gbeauche, 2005-07-03T22:02:01Z

#	Line 1 | Line 1
1		/*
2		*  sheepshaver_glue.cpp - Glue Kheperix CPU to SheepShaver CPU engine interface
3		*
4	<	*  SheepShaver (C) 1997-2004 Christian Bauer and Marc Hellwig
4	>	*  SheepShaver (C) 1997-2005 Christian Bauer and Marc Hellwig
5		*
6		*  This program is free software; you can redistribute it and/or modify
7		*  it under the terms of the GNU General Public License as published by
#	Line 42 | Line 42
42
43		#include <stdio.h>
44		#include <stdlib.h>
45	+	#ifdef HAVE_MALLOC_H
46	+	#include <malloc.h>
47	+	#endif
48
49		#ifdef USE_SDL_VIDEO
50		#include <SDL_events.h>
#	Line 90 | Line 93 | extern "C" void check_load_invoc(uint32
93		// PowerPC EmulOp to exit from emulation looop
94		const uint32 POWERPC_EXEC_RETURN = POWERPC_EMUL_OP | 1;
95
93	–	// Enable interrupt routine safety checks?
94	–	#define SAFE_INTERRUPT_PPC 1
95	–
96		// Enable Execute68k() safety checks?
97		#define SAFE_EXEC_68K 1
98
#	Line 106 | Line 106 | const uint32 POWERPC_EXEC_RETURN = POWER
106		#define INTERRUPTS_IN_NATIVE_MODE 1
107
108		// Pointer to Kernel Data
109	<	static KernelData * const kernel_data = (KernelData *)KERNEL_DATA_BASE;
109	>	static KernelData * kernel_data;
110
111		// SIGSEGV handler
112		sigsegv_return_t sigsegv_handler(sigsegv_address_t, sigsegv_address_t);
#	Line 139 | Line 139 | class sheepshaver_cpu
139		void init_decoder();
140		void execute_sheep(uint32 opcode);
141
142	–	// CPU context to preserve on interrupt
143	–	class interrupt_context {
144	–	uint32 gpr[32];
145	–	uint32 pc;
146	–	uint32 lr;
147	–	uint32 ctr;
148	–	uint32 cr;
149	–	uint32 xer;
150	–	sheepshaver_cpu *cpu;
151	–	const char *where;
152	–	public:
153	–	interrupt_context(sheepshaver_cpu *_cpu, const char *_where);
154	–	~interrupt_context();
155	–	};
156	–
142		public:
143
144		// Constructor
#	Line 180 | Line 165 | public:
165		// Execute MacOS/PPC code
166		uint32 execute_macos_code(uint32 tvect, int nargs, uint32 const *args);
167
168	+	#if PPC_ENABLE_JIT
169		// Compile one instruction
170		virtual int compile1(codegen_context_t & cg_context);
171	<
171	>	#endif
172		// Resource manager thunk
173		void get_resource(uint32 old_get_resource);
174
175		// Handle MacOS interrupt
176		void interrupt(uint32 entry);
191	–	void handle_interrupt();
177
178		// Make sure the SIGSEGV handler can access CPU registers
179		friend sigsegv_return_t sigsegv_handler(sigsegv_address_t, sigsegv_address_t);
195	–	};
180
181	<	// Memory allocator returning areas aligned on 16-byte boundaries
182	<	void *operator new(size_t size)
183	<	{
184	<	void *p;
181	>	// Memory allocator returning areas aligned on 16-byte boundaries
182	>	void *operator new(size_t size);
183	>	void operator delete(void *p);
184	>	};
185
186	<	#if defined(HAVE_POSIX_MEMALIGN)
187	<	if (posix_memalign(&p, 16, size) != 0)
186	>	// Memory allocator returning sheepshaver_cpu objects aligned on 16-byte boundaries
187	>	// FORMAT: [ alignment ] magic identifier, offset to malloc'ed data, sheepshaver_cpu data
188	>	void *sheepshaver_cpu::operator new(size_t size)
189	>	{
190	>	const int ALIGN = 16;
191	>
192	>	// Allocate enough space for sheepshaver_cpu data + signature + align pad
193	>	uint8 *ptr = (uint8 *)malloc(size + ALIGN * 2);
194	>	if (ptr == NULL)
195		throw std::bad_alloc();
205	–	#elif defined(HAVE_MEMALIGN)
206	–	p = memalign(16, size);
207	–	#elif defined(HAVE_VALLOC)
208	–	p = valloc(size); // page-aligned!
209	–	#else
210	–	/* XXX: handle padding ourselves */
211	–	p = malloc(size);
212	–	#endif
196
197	<	return p;
197	>	// Align memory
198	>	int ofs = 0;
199	>	while ((((uintptr)ptr) % ALIGN) != 0)
200	>	ofs++, ptr++;
201	>
202	>	// Insert signature and offset
203	>	struct aligned_block_t {
204	>	uint32 pad[(ALIGN - 8) / 4];
205	>	uint32 signature;
206	>	uint32 offset;
207	>	uint8  data[sizeof(sheepshaver_cpu)];
208	>	};
209	>	aligned_block_t *blk = (aligned_block_t *)ptr;
210	>	blk->signature = FOURCC('S','C','P','U');
211	>	blk->offset = ofs + (&blk->data[0] - (uint8 *)blk);
212	>	assert((((uintptr)&blk->data) % ALIGN) == 0);
213	>	return &blk->data[0];
214		}
215
216	<	void operator delete(void *p)
217	<	{
218	<	#if defined(HAVE_MEMALIGN) || defined(HAVE_VALLOC)
219	<	#if defined(__GLIBC__)
220	<	// this is known to work only with GNU libc
221	<	free(p);
223	<	#endif
224	<	#else
225	<	free(p);
226	<	#endif
216	>	void sheepshaver_cpu::operator delete(void *p)
217	>	{
218	>	uint32 *blk = (uint32 *)p;
219	>	assert(blk[-2] == FOURCC('S','C','P','U'));
220	>	void *ptr = (void *)(((uintptr)p) - blk[-1]);
221	>	free(ptr);
222		}
223
224		sheepshaver_cpu::sheepshaver_cpu()
#	Line 274 | Line 269 | void sheepshaver_cpu::execute_emul_op(ui
269		for (int i = 0; i < 7; i++)
270		r68.a[i] = gpr(16 + i);
271		r68.a[7] = gpr(1);
272	<	uint32 saved_cr = get_cr() & CR_field<2>::mask();
272	>	uint32 saved_cr = get_cr() & 0xff9fffff; // mask_operand::compute(11, 8)
273		uint32 saved_xer = get_xer();
274		EmulOp(&r68, gpr(24), emul_op);
275		set_cr(saved_cr);
#	Line 318 | Line 313 | void sheepshaver_cpu::execute_sheep(uint
313		}
314
315		// Compile one instruction
316	+	#if PPC_ENABLE_JIT
317		int sheepshaver_cpu::compile1(codegen_context_t & cg_context)
318		{
323	–	#if PPC_ENABLE_JIT
319		const instr_info_t *ii = cg_context.instr_info;
320		if (ii->mnemo != PPC_I(SHEEP))
321		return COMPILE_FAILURE;
#	Line 466 | Line 461 | int sheepshaver_cpu::compile1(codegen_co
461		}
462		}
463		return status;
469	–	#endif
470	–	return COMPILE_FAILURE;
471	–	}
472	–
473	–	// CPU context to preserve on interrupt
474	–	sheepshaver_cpu::interrupt_context::interrupt_context(sheepshaver_cpu *_cpu, const char *_where)
475	–	{
476	–	#if SAFE_INTERRUPT_PPC >= 2
477	–	cpu = _cpu;
478	–	where = _where;
479	–
480	–	// Save interrupt context
481	–	memcpy(&gpr[0], &cpu->gpr(0), sizeof(gpr));
482	–	pc = cpu->pc();
483	–	lr = cpu->lr();
484	–	ctr = cpu->ctr();
485	–	cr = cpu->get_cr();
486	–	xer = cpu->get_xer();
487	–	#endif
464		}
489	–
490	–	sheepshaver_cpu::interrupt_context::~interrupt_context()
491	–	{
492	–	#if SAFE_INTERRUPT_PPC >= 2
493	–	// Check whether CPU context was preserved by interrupt
494	–	if (memcmp(&gpr[0], &cpu->gpr(0), sizeof(gpr)) != 0) {
495	–	printf("FATAL: %s: interrupt clobbers registers\n", where);
496	–	for (int i = 0; i < 32; i++)
497	–	if (gpr[i] != cpu->gpr(i))
498	–	printf(" r%d: %08x -> %08x\n", i, gpr[i], cpu->gpr(i));
499	–	}
500	–	if (pc != cpu->pc())
501	–	printf("FATAL: %s: interrupt clobbers PC\n", where);
502	–	if (lr != cpu->lr())
503	–	printf("FATAL: %s: interrupt clobbers LR\n", where);
504	–	if (ctr != cpu->ctr())
505	–	printf("FATAL: %s: interrupt clobbers CTR\n", where);
506	–	if (cr != cpu->get_cr())
507	–	printf("FATAL: %s: interrupt clobbers CR\n", where);
508	–	if (xer != cpu->get_xer())
509	–	printf("FATAL: %s: interrupt clobbers XER\n", where);
465		#endif
511	–	}
466
467		// Handle MacOS interrupt
468		void sheepshaver_cpu::interrupt(uint32 entry)
#	Line 518 | Line 472 | void sheepshaver_cpu::interrupt(uint32 e
472		const clock_t interrupt_start = clock();
473		#endif
474
521	–	#if SAFE_INTERRUPT_PPC
522	–	static int depth = 0;
523	–	if (depth != 0)
524	–	printf("FATAL: sheepshaver_cpu::interrupt() called more than once: %d\n", depth);
525	–	depth++;
526	–	#endif
527	–
475		// Save program counters and branch registers
476		uint32 saved_pc = pc();
477		uint32 saved_lr = lr();
#	Line 578 | Line 525 | void sheepshaver_cpu::interrupt(uint32 e
525		#if EMUL_TIME_STATS
526		interrupt_time += (clock() - interrupt_start);
527		#endif
581	–
582	–	#if SAFE_INTERRUPT_PPC
583	–	depth--;
584	–	#endif
528		}
529
530		// Execute 68k routine
#	Line 812 | Line 755 | sigsegv_return_t sigsegv_handler(sigsegv
755		const uintptr addr = (uintptr)fault_address;
756		#if HAVE_SIGSEGV_SKIP_INSTRUCTION
757		// Ignore writes to ROM
758	<	if ((addr - ROM_BASE) < ROM_SIZE)
758	>	if ((addr - (uintptr)ROMBaseHost) < ROM_SIZE)
759		return SIGSEGV_RETURN_SKIP_INSTRUCTION;
760
761		// Get program counter of target CPU
#	Line 859 | Line 802 | sigsegv_return_t sigsegv_handler(sigsegv
802		#error "FIXME: You don't have the capability to skip instruction within signal handlers"
803		#endif
804
805	<	printf("SIGSEGV\n");
806	<	printf("  pc %p\n", fault_instruction);
807	<	printf("  ea %p\n", fault_address);
805	>	fprintf(stderr, "SIGSEGV\n");
806	>	fprintf(stderr, "  pc %p\n", fault_instruction);
807	>	fprintf(stderr, "  ea %p\n", fault_address);
808		dump_registers();
809		ppc_cpu->dump_log();
810		enter_mon();
#	Line 872 | Line 815 | sigsegv_return_t sigsegv_handler(sigsegv
815
816		void init_emul_ppc(void)
817		{
818	+	// Get pointer to KernelData in host address space
819	+	kernel_data = (KernelData *)Mac2HostAddr(KERNEL_DATA_BASE);
820	+
821		// Initialize main CPU emulator
822		ppc_cpu = new sheepshaver_cpu();
823		ppc_cpu->set_register(powerpc_registers::GPR(3), any_register((uint32)ROM_BASE + 0x30d000));
#	Line 969 | Line 915 | void emul_ppc(uint32 entry)
915
916		void TriggerInterrupt(void)
917		{
918	+	idle_resume();
919		#if 0
920		WriteMacInt32(0x16a, ReadMacInt32(0x16a) + 1);
921		#else
#	Line 978 | Line 925 | void TriggerInterrupt(void)
925		#endif
926		}
927
928	<	void sheepshaver_cpu::handle_interrupt(void)
928	>	void HandleInterrupt(powerpc_registers *r)
929		{
930		#ifdef USE_SDL_VIDEO
931		// We must fill in the events queue in the same thread that did call SDL_SetVideoMode()
#	Line 989 | Line 936 | void sheepshaver_cpu::handle_interrupt(v
936		if (int32(ReadMacInt32(XLM_IRQ_NEST)) > 0)
937		return;
938
939	<	// Current interrupt nest level
993	<	static int interrupt_depth = 0;
994	<	++interrupt_depth;
939	>	// Update interrupt count
940		#if EMUL_TIME_STATS
941		interrupt_count++;
942		#endif
943
999	–	// Disable MacOS stack sniffer
1000	–	WriteMacInt32(0x110, 0);
1001	–
944		// Interrupt action depends on current run mode
945		switch (ReadMacInt32(XLM_RUN_MODE)) {
946		case MODE_68K:
947		// 68k emulator active, trigger 68k interrupt level 1
948		WriteMacInt16(tswap32(kernel_data->v[0x67c >> 2]), 1);
949	<	set_cr(get_cr() | tswap32(kernel_data->v[0x674 >> 2]));
949	>	r->cr.set(r->cr.get() | tswap32(kernel_data->v[0x674 >> 2]));
950		break;
951
952		#if INTERRUPTS_IN_NATIVE_MODE
953		case MODE_NATIVE:
954		// 68k emulator inactive, in nanokernel?
955	<	if (gpr(1) != KernelDataAddr && interrupt_depth == 1) {
1014	<	interrupt_context ctx(this, "PowerPC mode");
955	>	if (r->gpr[1] != KernelDataAddr) {
956
957		// Prepare for 68k interrupt level 1
958		WriteMacInt16(tswap32(kernel_data->v[0x67c >> 2]), 1);
#	Line 1033 | Line 974 | void sheepshaver_cpu::handle_interrupt(v
974		case MODE_EMUL_OP:
975		// 68k emulator active, within EMUL_OP routine, execute 68k interrupt routine directly when interrupt level is 0
976		if ((ReadMacInt32(XLM_68K_R25) & 7) == 0) {
1036	–	interrupt_context ctx(this, "68k mode");
977		#if EMUL_TIME_STATS
978		const clock_t interrupt_start = clock();
979		#endif
#	Line 1042 | Line 982 | void sheepshaver_cpu::handle_interrupt(v
982		M68kRegisters r;
983		uint32 old_r25 = ReadMacInt32(XLM_68K_R25);     // Save interrupt level
984		WriteMacInt32(XLM_68K_R25, 0x21);                       // Execute with interrupt level 1
985	<	static const uint8 proc[] = {
985	>	static const uint8 proc_template[] = {
986		0x3f, 0x3c, 0x00, 0x00,                 // move.w       #$0000,-(sp)    (fake format word)
987		0x48, 0x7a, 0x00, 0x0a,                 // pea          @1(pc)                  (return address)
988		0x40, 0xe7,                                             // move         sr,-(sp)                (saved SR)
#	Line 1050 | Line 990 | void sheepshaver_cpu::handle_interrupt(v
990		0x4e, 0xd0,                                             // jmp          (a0)
991		M68K_RTS >> 8, M68K_RTS & 0xff  // @1
992		};
993	<	Execute68k((uint32)proc, &r);
993	>	BUILD_SHEEPSHAVER_PROCEDURE(proc);
994	>	Execute68k(proc, &r);
995		WriteMacInt32(XLM_68K_R25, old_r25);            // Restore interrupt level
996		#else
997		// Only update cursor
#	Line 1069 | Line 1010 | void sheepshaver_cpu::handle_interrupt(v
1010		break;
1011		#endif
1012		}
1072	–
1073	–	// We are done with this interrupt
1074	–	--interrupt_depth;
1013		}
1014
1015		static void get_resource(void);
#	Line 1099 | Line 1037 | void sheepshaver_cpu::execute_native_op(
1037		VideoVBL();
1038		break;
1039		case NATIVE_VIDEO_DO_DRIVER_IO:
1040	<	gpr(3) = (int32)(int16)VideoDoDriverIO((void *)gpr(3), (void *)gpr(4),
1041	<	(void *)gpr(5), gpr(6), gpr(7));
1040	>	gpr(3) = (int32)(int16)VideoDoDriverIO(gpr(3), gpr(4), gpr(5), gpr(6), gpr(7));
1041	>	break;
1042	>	case NATIVE_ETHER_AO_GET_HWADDR:
1043	>	AO_get_ethernet_address(gpr(3));
1044	>	break;
1045	>	case NATIVE_ETHER_AO_ADD_MULTI:
1046	>	AO_enable_multicast(gpr(3));
1047	>	break;
1048	>	case NATIVE_ETHER_AO_DEL_MULTI:
1049	>	AO_disable_multicast(gpr(3));
1050	>	break;
1051	>	case NATIVE_ETHER_AO_SEND_PACKET:
1052	>	AO_transmit_packet(gpr(3));
1053		break;
1105	–	#ifdef WORDS_BIGENDIAN
1054		case NATIVE_ETHER_IRQ:
1055		EtherIRQ();
1056		break;
#	Line 1124 | Line 1072 | void sheepshaver_cpu::execute_native_op(
1072		case NATIVE_ETHER_RSRV:
1073		gpr(3) = ether_rsrv((queue_t *)gpr(3));
1074		break;
1127	–	#else
1128	–	case NATIVE_ETHER_INIT:
1129	–	// FIXME: needs more complicated thunks
1130	–	gpr(3) = false;
1131	–	break;
1132	–	#endif
1075		case NATIVE_SYNC_HOOK:
1076		gpr(3) = NQD_sync_hook(gpr(3));
1077		break;
#	Line 1185 | Line 1127 | void sheepshaver_cpu::execute_native_op(
1127		break;
1128		}
1129		case NATIVE_MAKE_EXECUTABLE:
1130	<	MakeExecutable(0, (void *)gpr(4), gpr(5));
1130	>	MakeExecutable(0, gpr(4), gpr(5));
1131		break;
1132		case NATIVE_CHECK_LOAD_INVOC:
1133		check_load_invoc(gpr(3), gpr(4), gpr(5));

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