[ViewVC] Diff of: cebix/SheepShaver/src/kpx_cpu/sheepshaver

Comparing SheepShaver/src/kpx_cpu/sheepshaver_glue.cpp (file contents):
Revision 1.47 by gbeauche, 2004-06-24T15:37:26Z vs.
Revision 1.57 by gbeauche, 2005-01-30T21:48:21Z

#	Line 1 \| Line 1
1		/*
2		* sheepshaver_glue.cpp - Glue Kheperix CPU to SheepShaver CPU engine interface
3		*
4	<	* SheepShaver (C) 1997-2004 Christian Bauer and Marc Hellwig
4	>	* SheepShaver (C) 1997-2005 Christian Bauer and Marc Hellwig
5		*
6		* This program is free software; you can redistribute it and/or modify
7		* it under the terms of the GNU General Public License as published by
#	Line 42 \| Line 42
42
43		#include <stdio.h>
44		#include <stdlib.h>
45	+	#ifdef HAVE_MALLOC_H
46	+	#include <malloc.h>
47	+	#endif
48
49		#ifdef USE_SDL_VIDEO
50		#include <SDL_events.h>
#	Line 105 \| Line 108 \| const uint32 POWERPC_EXEC_RETURN = POWER
108		// Interrupts in native mode?
109		#define INTERRUPTS_IN_NATIVE_MODE 1
110
108	–	// Enable native EMUL_OPs to be run without a mode switch
109	–	#define ENABLE_NATIVE_EMUL_OP 1
110	–
111		// Pointer to Kernel Data
112	<	static KernelData * const kernel_data = (KernelData *)KERNEL_DATA_BASE;
112	>	static KernelData * kernel_data;
113
114		// SIGSEGV handler
115	<	static sigsegv_return_t sigsegv_handler(sigsegv_address_t, sigsegv_address_t);
115	>	sigsegv_return_t sigsegv_handler(sigsegv_address_t, sigsegv_address_t);
116
117		#if PPC_ENABLE_JIT && PPC_REENTRANT_JIT
118		// Special trampolines for EmulOp and NativeOp
#	Line 142 \| Line 142 \| class sheepshaver_cpu
142		void init_decoder();
143		void execute_sheep(uint32 opcode);
144
145	–	// Filter out EMUL_OP routines that only call native code
146	–	bool filter_execute_emul_op(uint32 emul_op);
147	–
148	–	// "Native" EMUL_OP routines
149	–	void execute_emul_op_microseconds();
150	–	void execute_emul_op_idle_time_1();
151	–	void execute_emul_op_idle_time_2();
152	–
145		// CPU context to preserve on interrupt
146		class interrupt_context {
147		uint32 gpr[32];
148	+	double fpr[32];
149		uint32 pc;
150		uint32 lr;
151		uint32 ctr;
152		uint32 cr;
153		uint32 xer;
154	+	uint32 fpscr;
155		sheepshaver_cpu *cpu;
156		const char *where;
157		public:
#	Line 191 \| Line 185 \| public:
185		// Execute MacOS/PPC code
186		uint32 execute_macos_code(uint32 tvect, int nargs, uint32 const *args);
187
188	+	#if PPC_ENABLE_JIT
189		// Compile one instruction
190		virtual int compile1(codegen_context_t & cg_context);
191	<
191	>	#endif
192		// Resource manager thunk
193		void get_resource(uint32 old_get_resource);
194
#	Line 203 \| Line 198 \| public:
198
199		// Make sure the SIGSEGV handler can access CPU registers
200		friend sigsegv_return_t sigsegv_handler(sigsegv_address_t, sigsegv_address_t);
201	+
202	+	// Memory allocator returning areas aligned on 16-byte boundaries
203	+	void *operator new(size_t size);
204	+	void operator delete(void *p);
205		};
206
207		// Memory allocator returning areas aligned on 16-byte boundaries
208	<	void *operator new(size_t size)
208	>	void *sheepshaver_cpu::operator new(size_t size)
209		{
210		void *p;
211
#	Line 225 \| Line 224 \| *void operator new(size_t size)**
224		return p;
225		}
226
227	<	void operator delete(void *p)
227	>	void sheepshaver_cpu::operator delete(void *p)
228		{
229		#if defined(HAVE_MEMALIGN) \|\| defined(HAVE_VALLOC)
230		#if defined(__GLIBC__)
#	Line 274 \| Line 273 \| typedef bit_field< 19, 19 > FN_field;
273		typedef bit_field< 20, 25 > NATIVE_OP_field;
274		typedef bit_field< 26, 31 > EMUL_OP_field;
275
277	–	// "Native" EMUL_OP routines
278	–	#define GPR_A(REG) gpr(16 + (REG))
279	–	#define GPR_D(REG) gpr( 8 + (REG))
280	–
281	–	void sheepshaver_cpu::execute_emul_op_microseconds()
282	–	{
283	–	Microseconds(GPR_A(0), GPR_D(0));
284	–	}
285	–
286	–	void sheepshaver_cpu::execute_emul_op_idle_time_1()
287	–	{
288	–	// Sleep if no events pending
289	–	if (ReadMacInt32(0x14c) == 0)
290	–	Delay_usec(16667);
291	–	GPR_A(0) = ReadMacInt32(0x2b6);
292	–	}
293	–
294	–	void sheepshaver_cpu::execute_emul_op_idle_time_2()
295	–	{
296	–	// Sleep if no events pending
297	–	if (ReadMacInt32(0x14c) == 0)
298	–	Delay_usec(16667);
299	–	GPR_D(0) = (uint32)-2;
300	–	}
301	–
302	–	// Filter out EMUL_OP routines that only call native code
303	–	bool sheepshaver_cpu::filter_execute_emul_op(uint32 emul_op)
304	–	{
305	–	switch (emul_op) {
306	–	case OP_MICROSECONDS:
307	–	execute_emul_op_microseconds();
308	–	return true;
309	–	case OP_IDLE_TIME:
310	–	execute_emul_op_idle_time_1();
311	–	return true;
312	–	case OP_IDLE_TIME_2:
313	–	execute_emul_op_idle_time_2();
314	–	return true;
315	–	}
316	–	return false;
317	–	}
318	–
276		// Execute EMUL_OP routine
277		void sheepshaver_cpu::execute_emul_op(uint32 emul_op)
278		{
322	–	#if ENABLE_NATIVE_EMUL_OP
323	–	// First, filter out EMUL_OPs that can be executed without a mode switch
324	–	if (filter_execute_emul_op(emul_op))
325	–	return;
326	–	#endif
327	–
279		M68kRegisters r68;
280		WriteMacInt32(XLM_68K_R25, gpr(25));
281		WriteMacInt32(XLM_RUN_MODE, MODE_EMUL_OP);
#	Line 377 \| Line 328 \| void sheepshaver_cpu::execute_sheep(uint
328		}
329
330		// Compile one instruction
331	+	#if PPC_ENABLE_JIT
332		int sheepshaver_cpu::compile1(codegen_context_t & cg_context)
333		{
382	–	#if PPC_ENABLE_JIT
334		const instr_info_t *ii = cg_context.instr_info;
335		if (ii->mnemo != PPC_I(SHEEP))
336		return COMPILE_FAILURE;
#	Line 506 \| Line 457 \| int sheepshaver_cpu::compile1(codegen_co
457
458		default: { // EMUL_OP
459		uint32 emul_op = EMUL_OP_field::extract(opcode) - 3;
509	–	#if ENABLE_NATIVE_EMUL_OP
510	–	typedef void (*emul_op_func_t)(dyngen_cpu_base);
511	–	emul_op_func_t emul_op_func = 0;
512	–	switch (emul_op) {
513	–	case OP_MICROSECONDS:
514	–	emul_op_func = (emul_op_func_t)nv_mem_fun(&sheepshaver_cpu::execute_emul_op_microseconds).ptr();
515	–	break;
516	–	case OP_IDLE_TIME:
517	–	emul_op_func = (emul_op_func_t)nv_mem_fun(&sheepshaver_cpu::execute_emul_op_idle_time_1).ptr();
518	–	break;
519	–	case OP_IDLE_TIME_2:
520	–	emul_op_func = (emul_op_func_t)nv_mem_fun(&sheepshaver_cpu::execute_emul_op_idle_time_2).ptr();
521	–	break;
522	–	}
523	–	if (emul_op_func) {
524	–	dg.gen_invoke_CPU(emul_op_func);
525	–	cg_context.done_compile = false;
526	–	status = COMPILE_CODE_OK;
527	–	break;
528	–	}
529	–	#endif
460		#if PPC_REENTRANT_JIT
461		// Try to execute EmulOp trampoline
462		dg.gen_set_PC_im(cg_context.pc + 4);
#	Line 546 \| Line 476 \| int sheepshaver_cpu::compile1(codegen_co
476		}
477		}
478		return status;
549	–	#endif
550	–	return COMPILE_FAILURE;
479		}
480	+	#endif
481
482		// CPU context to preserve on interrupt
483		sheepshaver_cpu::interrupt_context::interrupt_context(sheepshaver_cpu _cpu, const char _where)
#	Line 559 \| Line 488 \| sheepshaver_cpu::interrupt_context::inte
488
489		// Save interrupt context
490		memcpy(&gpr[0], &cpu->gpr(0), sizeof(gpr));
491	+	memcpy(&fpr[0], &cpu->fpr(0), sizeof(fpr));
492		pc = cpu->pc();
493		lr = cpu->lr();
494		ctr = cpu->ctr();
495		cr = cpu->get_cr();
496		xer = cpu->get_xer();
497	+	fpscr = cpu->fpscr();
498		#endif
499		}
500
#	Line 577 \| Line 508 \| sheepshaver_cpu::interrupt_context::~int
508		if (gpr[i] != cpu->gpr(i))
509		printf(" r%d: %08x -> %08x\n", i, gpr[i], cpu->gpr(i));
510		}
511	+	if (memcmp(&fpr[0], &cpu->fpr(0), sizeof(fpr)) != 0) {
512	+	printf("FATAL: %s: interrupt clobbers registers\n", where);
513	+	for (int i = 0; i < 32; i++)
514	+	if (fpr[i] != cpu->fpr(i))
515	+	printf(" r%d: %f -> %f\n", i, fpr[i], cpu->fpr(i));
516	+	}
517		if (pc != cpu->pc())
518		printf("FATAL: %s: interrupt clobbers PC\n", where);
519		if (lr != cpu->lr())
#	Line 587 \| Line 524 \| sheepshaver_cpu::interrupt_context::~int
524		printf("FATAL: %s: interrupt clobbers CR\n", where);
525		if (xer != cpu->get_xer())
526		printf("FATAL: %s: interrupt clobbers XER\n", where);
527	+	if (fpscr != cpu->fpscr())
528	+	printf("FATAL: %s: interrupt clobbers FPSCR\n", where);
529		#endif
530		}
531
#	Line 880 \| Line 819 \| static void dump_log(void)
819		* Initialize CPU emulation
820		*/
821
822	<	static sigsegv_return_t sigsegv_handler(sigsegv_address_t fault_address, sigsegv_address_t fault_instruction)
822	>	sigsegv_return_t sigsegv_handler(sigsegv_address_t fault_address, sigsegv_address_t fault_instruction)
823		{
824		#if ENABLE_VOSF
825		// Handle screen fault
#	Line 892 \| Line 831 \| static sigsegv_return_t sigsegv_handler(
831		const uintptr addr = (uintptr)fault_address;
832		#if HAVE_SIGSEGV_SKIP_INSTRUCTION
833		// Ignore writes to ROM
834	<	if ((addr - ROM_BASE) < ROM_SIZE)
834	>	if ((addr - (uintptr)ROMBaseHost) < ROM_SIZE)
835		return SIGSEGV_RETURN_SKIP_INSTRUCTION;
836
837		// Get program counter of target CPU
#	Line 952 \| Line 891 \| static sigsegv_return_t sigsegv_handler(
891
892		void init_emul_ppc(void)
893		{
894	+	// Get pointer to KernelData in host address space
895	+	kernel_data = (KernelData *)Mac2HostAddr(KERNEL_DATA_BASE);
896	+
897		// Initialize main CPU emulator
898		ppc_cpu = new sheepshaver_cpu();
899		ppc_cpu->set_register(powerpc_registers::GPR(3), any_register((uint32)ROM_BASE + 0x30d000));
900		ppc_cpu->set_register(powerpc_registers::GPR(4), any_register(KernelDataAddr + 0x1000));
901		WriteMacInt32(XLM_RUN_MODE, MODE_68K);
902
961	–	// Install the handler for SIGSEGV
962	–	sigsegv_install_handler(sigsegv_handler);
963	–
903		#if ENABLE_MON
904		// Install "regs" command in cxmon
905		mon_add_command("regs", dump_registers, "regs Dump PowerPC registers\n");
#	Line 1125 \| Line 1064 \| void sheepshaver_cpu::handle_interrupt(v
1064		M68kRegisters r;
1065		uint32 old_r25 = ReadMacInt32(XLM_68K_R25); // Save interrupt level
1066		WriteMacInt32(XLM_68K_R25, 0x21); // Execute with interrupt level 1
1067	<	static const uint8 proc[] = {
1067	>	static const uint8 proc_template[] = {
1068		0x3f, 0x3c, 0x00, 0x00, // move.w #$0000,-(sp) (fake format word)
1069		0x48, 0x7a, 0x00, 0x0a, // pea @1(pc) (return address)
1070		0x40, 0xe7, // move sr,-(sp) (saved SR)
#	Line 1133 \| Line 1072 \| void sheepshaver_cpu::handle_interrupt(v
1072		0x4e, 0xd0, // jmp (a0)
1073		M68K_RTS >> 8, M68K_RTS & 0xff // @1
1074		};
1075	<	Execute68k((uint32)proc, &r);
1075	>	BUILD_SHEEPSHAVER_PROCEDURE(proc);
1076	>	Execute68k(proc, &r);
1077		WriteMacInt32(XLM_68K_R25, old_r25); // Restore interrupt level
1078		#else
1079		// Only update cursor
#	Line 1182 \| Line 1122 \| void sheepshaver_cpu::execute_native_op(
1122		VideoVBL();
1123		break;
1124		case NATIVE_VIDEO_DO_DRIVER_IO:
1125	<	gpr(3) = (int32)(int16)VideoDoDriverIO((void )gpr(3), (void )gpr(4),
1186	<	(void *)gpr(5), gpr(6), gpr(7));
1125	>	gpr(3) = (int32)(int16)VideoDoDriverIO(gpr(3), gpr(4), gpr(5), gpr(6), gpr(7));
1126		break;
1188	–	#ifdef WORDS_BIGENDIAN
1127		case NATIVE_ETHER_IRQ:
1128		EtherIRQ();
1129		break;
#	Line 1207 \| Line 1145 \| void sheepshaver_cpu::execute_native_op(
1145		case NATIVE_ETHER_RSRV:
1146		gpr(3) = ether_rsrv((queue_t *)gpr(3));
1147		break;
1210	–	#else
1211	–	case NATIVE_ETHER_INIT:
1212	–	// FIXME: needs more complicated thunks
1213	–	gpr(3) = false;
1214	–	break;
1215	–	#endif
1148		case NATIVE_SYNC_HOOK:
1149		gpr(3) = NQD_sync_hook(gpr(3));
1150		break;
#	Line 1268 \| Line 1200 \| void sheepshaver_cpu::execute_native_op(
1200		break;
1201		}
1202		case NATIVE_MAKE_EXECUTABLE:
1203	<	MakeExecutable(0, (void *)gpr(4), gpr(5));
1203	>	MakeExecutable(0, gpr(4), gpr(5));
1204		break;
1205		case NATIVE_CHECK_LOAD_INVOC:
1206		check_load_invoc(gpr(3), gpr(4), gpr(5));

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Comparing SheepShaver/src/kpx_cpu/sheepshaver_glue.cpp (file contents): Revision 1.47 by gbeauche, 2004-06-24T15:37:26Z vs. Revision 1.57 by gbeauche, 2005-01-30T21:48:21Z

Diff Legend

Comparing SheepShaver/src/kpx_cpu/sheepshaver_glue.cpp (file contents):
Revision 1.47 by gbeauche, 2004-06-24T15:37:26Z vs.
Revision 1.57 by gbeauche, 2005-01-30T21:48:21Z