105 |
|
// Interrupts in native mode? |
106 |
|
#define INTERRUPTS_IN_NATIVE_MODE 1 |
107 |
|
|
108 |
– |
// Enable native EMUL_OPs to be run without a mode switch |
109 |
– |
#define ENABLE_NATIVE_EMUL_OP 1 |
110 |
– |
|
108 |
|
// Pointer to Kernel Data |
109 |
|
static KernelData * const kernel_data = (KernelData *)KERNEL_DATA_BASE; |
110 |
|
|
139 |
|
void init_decoder(); |
140 |
|
void execute_sheep(uint32 opcode); |
141 |
|
|
145 |
– |
// Filter out EMUL_OP routines that only call native code |
146 |
– |
bool filter_execute_emul_op(uint32 emul_op); |
147 |
– |
|
148 |
– |
// "Native" EMUL_OP routines |
149 |
– |
void execute_emul_op_microseconds(); |
150 |
– |
void execute_emul_op_idle_time_1(); |
151 |
– |
void execute_emul_op_idle_time_2(); |
152 |
– |
|
142 |
|
// CPU context to preserve on interrupt |
143 |
|
class interrupt_context { |
144 |
|
uint32 gpr[32]; |
263 |
|
typedef bit_field< 20, 25 > NATIVE_OP_field; |
264 |
|
typedef bit_field< 26, 31 > EMUL_OP_field; |
265 |
|
|
277 |
– |
// "Native" EMUL_OP routines |
278 |
– |
#define GPR_A(REG) gpr(16 + (REG)) |
279 |
– |
#define GPR_D(REG) gpr( 8 + (REG)) |
280 |
– |
|
281 |
– |
void sheepshaver_cpu::execute_emul_op_microseconds() |
282 |
– |
{ |
283 |
– |
Microseconds(GPR_A(0), GPR_D(0)); |
284 |
– |
} |
285 |
– |
|
286 |
– |
void sheepshaver_cpu::execute_emul_op_idle_time_1() |
287 |
– |
{ |
288 |
– |
// Sleep if no events pending |
289 |
– |
if (ReadMacInt32(0x14c) == 0) |
290 |
– |
Delay_usec(16667); |
291 |
– |
GPR_A(0) = ReadMacInt32(0x2b6); |
292 |
– |
} |
293 |
– |
|
294 |
– |
void sheepshaver_cpu::execute_emul_op_idle_time_2() |
295 |
– |
{ |
296 |
– |
// Sleep if no events pending |
297 |
– |
if (ReadMacInt32(0x14c) == 0) |
298 |
– |
Delay_usec(16667); |
299 |
– |
GPR_D(0) = (uint32)-2; |
300 |
– |
} |
301 |
– |
|
302 |
– |
// Filter out EMUL_OP routines that only call native code |
303 |
– |
bool sheepshaver_cpu::filter_execute_emul_op(uint32 emul_op) |
304 |
– |
{ |
305 |
– |
switch (emul_op) { |
306 |
– |
case OP_MICROSECONDS: |
307 |
– |
execute_emul_op_microseconds(); |
308 |
– |
return true; |
309 |
– |
case OP_IDLE_TIME: |
310 |
– |
execute_emul_op_idle_time_1(); |
311 |
– |
return true; |
312 |
– |
case OP_IDLE_TIME_2: |
313 |
– |
execute_emul_op_idle_time_2(); |
314 |
– |
return true; |
315 |
– |
} |
316 |
– |
return false; |
317 |
– |
} |
318 |
– |
|
266 |
|
// Execute EMUL_OP routine |
267 |
|
void sheepshaver_cpu::execute_emul_op(uint32 emul_op) |
268 |
|
{ |
322 |
– |
#if ENABLE_NATIVE_EMUL_OP |
323 |
– |
// First, filter out EMUL_OPs that can be executed without a mode switch |
324 |
– |
if (filter_execute_emul_op(emul_op)) |
325 |
– |
return; |
326 |
– |
#endif |
327 |
– |
|
269 |
|
M68kRegisters r68; |
270 |
|
WriteMacInt32(XLM_68K_R25, gpr(25)); |
271 |
|
WriteMacInt32(XLM_RUN_MODE, MODE_EMUL_OP); |
447 |
|
|
448 |
|
default: { // EMUL_OP |
449 |
|
uint32 emul_op = EMUL_OP_field::extract(opcode) - 3; |
509 |
– |
#if ENABLE_NATIVE_EMUL_OP |
510 |
– |
typedef void (*emul_op_func_t)(dyngen_cpu_base); |
511 |
– |
emul_op_func_t emul_op_func = 0; |
512 |
– |
switch (emul_op) { |
513 |
– |
case OP_MICROSECONDS: |
514 |
– |
emul_op_func = (emul_op_func_t)nv_mem_fun(&sheepshaver_cpu::execute_emul_op_microseconds).ptr(); |
515 |
– |
break; |
516 |
– |
case OP_IDLE_TIME: |
517 |
– |
emul_op_func = (emul_op_func_t)nv_mem_fun(&sheepshaver_cpu::execute_emul_op_idle_time_1).ptr(); |
518 |
– |
break; |
519 |
– |
case OP_IDLE_TIME_2: |
520 |
– |
emul_op_func = (emul_op_func_t)nv_mem_fun(&sheepshaver_cpu::execute_emul_op_idle_time_2).ptr(); |
521 |
– |
break; |
522 |
– |
} |
523 |
– |
if (emul_op_func) { |
524 |
– |
dg.gen_invoke_CPU(emul_op_func); |
525 |
– |
cg_context.done_compile = false; |
526 |
– |
status = COMPILE_CODE_OK; |
527 |
– |
break; |
528 |
– |
} |
529 |
– |
#endif |
450 |
|
#if PPC_REENTRANT_JIT |
451 |
|
// Try to execute EmulOp trampoline |
452 |
|
dg.gen_set_PC_im(cg_context.pc + 4); |