| 1 |
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/* |
| 2 |
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* sheepshaver_glue.cpp - Glue Kheperix CPU to SheepShaver CPU engine interface |
| 3 |
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* |
| 4 |
< |
* SheepShaver (C) 1997-2004 Christian Bauer and Marc Hellwig |
| 4 |
> |
* SheepShaver (C) 1997-2005 Christian Bauer and Marc Hellwig |
| 5 |
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* |
| 6 |
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* This program is free software; you can redistribute it and/or modify |
| 7 |
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* it under the terms of the GNU General Public License as published by |
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|
| 43 |
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#include <stdio.h> |
| 44 |
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#include <stdlib.h> |
| 45 |
+ |
#ifdef HAVE_MALLOC_H |
| 46 |
+ |
#include <malloc.h> |
| 47 |
+ |
#endif |
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+ |
|
| 49 |
+ |
#ifdef USE_SDL_VIDEO |
| 50 |
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#include <SDL_events.h> |
| 51 |
+ |
#endif |
| 52 |
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|
| 53 |
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#if ENABLE_MON |
| 54 |
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#include "mon.h" |
| 93 |
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// PowerPC EmulOp to exit from emulation looop |
| 94 |
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const uint32 POWERPC_EXEC_RETURN = POWERPC_EMUL_OP | 1; |
| 95 |
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|
| 89 |
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// Enable interrupt routine safety checks? |
| 90 |
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#define SAFE_INTERRUPT_PPC 1 |
| 91 |
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|
| 96 |
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// Enable Execute68k() safety checks? |
| 97 |
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#define SAFE_EXEC_68K 1 |
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|
| 105 |
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// Interrupts in native mode? |
| 106 |
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#define INTERRUPTS_IN_NATIVE_MODE 1 |
| 107 |
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|
| 104 |
– |
// Enable native EMUL_OPs to be run without a mode switch |
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#define ENABLE_NATIVE_EMUL_OP 1 |
| 106 |
– |
|
| 108 |
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// Pointer to Kernel Data |
| 109 |
< |
static KernelData * const kernel_data = (KernelData *)KERNEL_DATA_BASE; |
| 109 |
> |
static KernelData * kernel_data; |
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|
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// SIGSEGV handler |
| 112 |
< |
static sigsegv_return_t sigsegv_handler(sigsegv_address_t, sigsegv_address_t); |
| 112 |
> |
sigsegv_return_t sigsegv_handler(sigsegv_address_t, sigsegv_address_t); |
| 113 |
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|
| 114 |
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#if PPC_ENABLE_JIT && PPC_REENTRANT_JIT |
| 115 |
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// Special trampolines for EmulOp and NativeOp |
| 139 |
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void init_decoder(); |
| 140 |
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void execute_sheep(uint32 opcode); |
| 141 |
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|
| 141 |
– |
// Filter out EMUL_OP routines that only call native code |
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bool filter_execute_emul_op(uint32 emul_op); |
| 143 |
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|
| 144 |
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// "Native" EMUL_OP routines |
| 145 |
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void execute_emul_op_microseconds(); |
| 146 |
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void execute_emul_op_idle_time_1(); |
| 147 |
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void execute_emul_op_idle_time_2(); |
| 148 |
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|
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// CPU context to preserve on interrupt |
| 150 |
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class interrupt_context { |
| 151 |
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uint32 gpr[32]; |
| 152 |
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uint32 pc; |
| 153 |
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uint32 lr; |
| 154 |
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uint32 ctr; |
| 155 |
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uint32 cr; |
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uint32 xer; |
| 157 |
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sheepshaver_cpu *cpu; |
| 158 |
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const char *where; |
| 159 |
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public: |
| 160 |
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interrupt_context(sheepshaver_cpu *_cpu, const char *_where); |
| 161 |
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~interrupt_context(); |
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}; |
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|
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public: |
| 143 |
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|
| 144 |
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// Constructor |
| 165 |
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// Execute MacOS/PPC code |
| 166 |
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uint32 execute_macos_code(uint32 tvect, int nargs, uint32 const *args); |
| 167 |
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|
| 168 |
+ |
#if PPC_ENABLE_JIT |
| 169 |
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// Compile one instruction |
| 170 |
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virtual int compile1(codegen_context_t & cg_context); |
| 171 |
< |
|
| 171 |
> |
#endif |
| 172 |
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// Resource manager thunk |
| 173 |
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void get_resource(uint32 old_get_resource); |
| 174 |
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|
| 175 |
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// Handle MacOS interrupt |
| 176 |
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void interrupt(uint32 entry); |
| 198 |
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void handle_interrupt(); |
| 177 |
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|
| 178 |
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// Make sure the SIGSEGV handler can access CPU registers |
| 179 |
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friend sigsegv_return_t sigsegv_handler(sigsegv_address_t, sigsegv_address_t); |
| 202 |
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}; |
| 180 |
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|
| 181 |
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// Memory allocator returning areas aligned on 16-byte boundaries |
| 182 |
< |
void *operator new(size_t size) |
| 183 |
< |
{ |
| 184 |
< |
void *p; |
| 181 |
> |
// Memory allocator returning areas aligned on 16-byte boundaries |
| 182 |
> |
void *operator new(size_t size); |
| 183 |
> |
void operator delete(void *p); |
| 184 |
> |
}; |
| 185 |
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|
| 186 |
< |
#if defined(HAVE_POSIX_MEMALIGN) |
| 187 |
< |
if (posix_memalign(&p, 16, size) != 0) |
| 186 |
> |
// Memory allocator returning sheepshaver_cpu objects aligned on 16-byte boundaries |
| 187 |
> |
// FORMAT: [ alignment ] magic identifier, offset to malloc'ed data, sheepshaver_cpu data |
| 188 |
> |
void *sheepshaver_cpu::operator new(size_t size) |
| 189 |
> |
{ |
| 190 |
> |
const int ALIGN = 16; |
| 191 |
> |
|
| 192 |
> |
// Allocate enough space for sheepshaver_cpu data + signature + align pad |
| 193 |
> |
uint8 *ptr = (uint8 *)malloc(size + ALIGN * 2); |
| 194 |
> |
if (ptr == NULL) |
| 195 |
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throw std::bad_alloc(); |
| 212 |
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#elif defined(HAVE_MEMALIGN) |
| 213 |
– |
p = memalign(16, size); |
| 214 |
– |
#elif defined(HAVE_VALLOC) |
| 215 |
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p = valloc(size); // page-aligned! |
| 216 |
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#else |
| 217 |
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/* XXX: handle padding ourselves */ |
| 218 |
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p = malloc(size); |
| 219 |
– |
#endif |
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|
| 197 |
< |
return p; |
| 197 |
> |
// Align memory |
| 198 |
> |
int ofs = 0; |
| 199 |
> |
while ((((uintptr)ptr) % ALIGN) != 0) |
| 200 |
> |
ofs++, ptr++; |
| 201 |
> |
|
| 202 |
> |
// Insert signature and offset |
| 203 |
> |
struct aligned_block_t { |
| 204 |
> |
uint32 pad[(ALIGN - 8) / 4]; |
| 205 |
> |
uint32 signature; |
| 206 |
> |
uint32 offset; |
| 207 |
> |
uint8 data[sizeof(sheepshaver_cpu)]; |
| 208 |
> |
}; |
| 209 |
> |
aligned_block_t *blk = (aligned_block_t *)ptr; |
| 210 |
> |
blk->signature = FOURCC('S','C','P','U'); |
| 211 |
> |
blk->offset = ofs + (&blk->data[0] - (uint8 *)blk); |
| 212 |
> |
assert((((uintptr)&blk->data) % ALIGN) == 0); |
| 213 |
> |
return &blk->data[0]; |
| 214 |
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} |
| 215 |
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|
| 216 |
< |
void operator delete(void *p) |
| 217 |
< |
{ |
| 218 |
< |
#if defined(HAVE_MEMALIGN) || defined(HAVE_VALLOC) |
| 219 |
< |
#if defined(__GLIBC__) |
| 220 |
< |
// this is known to work only with GNU libc |
| 221 |
< |
free(p); |
| 230 |
< |
#endif |
| 231 |
< |
#else |
| 232 |
< |
free(p); |
| 233 |
< |
#endif |
| 216 |
> |
void sheepshaver_cpu::operator delete(void *p) |
| 217 |
> |
{ |
| 218 |
> |
uint32 *blk = (uint32 *)p; |
| 219 |
> |
assert(blk[-2] == FOURCC('S','C','P','U')); |
| 220 |
> |
void *ptr = (void *)(((uintptr)p) - blk[-1]); |
| 221 |
> |
free(ptr); |
| 222 |
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} |
| 223 |
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|
| 224 |
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sheepshaver_cpu::sheepshaver_cpu() |
| 258 |
|
typedef bit_field< 20, 25 > NATIVE_OP_field; |
| 259 |
|
typedef bit_field< 26, 31 > EMUL_OP_field; |
| 260 |
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|
| 273 |
– |
// "Native" EMUL_OP routines |
| 274 |
– |
#define GPR_A(REG) gpr(16 + (REG)) |
| 275 |
– |
#define GPR_D(REG) gpr( 8 + (REG)) |
| 276 |
– |
|
| 277 |
– |
void sheepshaver_cpu::execute_emul_op_microseconds() |
| 278 |
– |
{ |
| 279 |
– |
Microseconds(GPR_A(0), GPR_D(0)); |
| 280 |
– |
} |
| 281 |
– |
|
| 282 |
– |
void sheepshaver_cpu::execute_emul_op_idle_time_1() |
| 283 |
– |
{ |
| 284 |
– |
// Sleep if no events pending |
| 285 |
– |
if (ReadMacInt32(0x14c) == 0) |
| 286 |
– |
Delay_usec(16667); |
| 287 |
– |
GPR_A(0) = ReadMacInt32(0x2b6); |
| 288 |
– |
} |
| 289 |
– |
|
| 290 |
– |
void sheepshaver_cpu::execute_emul_op_idle_time_2() |
| 291 |
– |
{ |
| 292 |
– |
// Sleep if no events pending |
| 293 |
– |
if (ReadMacInt32(0x14c) == 0) |
| 294 |
– |
Delay_usec(16667); |
| 295 |
– |
GPR_D(0) = (uint32)-2; |
| 296 |
– |
} |
| 297 |
– |
|
| 298 |
– |
// Filter out EMUL_OP routines that only call native code |
| 299 |
– |
bool sheepshaver_cpu::filter_execute_emul_op(uint32 emul_op) |
| 300 |
– |
{ |
| 301 |
– |
switch (emul_op) { |
| 302 |
– |
case OP_MICROSECONDS: |
| 303 |
– |
execute_emul_op_microseconds(); |
| 304 |
– |
return true; |
| 305 |
– |
case OP_IDLE_TIME: |
| 306 |
– |
execute_emul_op_idle_time_1(); |
| 307 |
– |
return true; |
| 308 |
– |
case OP_IDLE_TIME_2: |
| 309 |
– |
execute_emul_op_idle_time_2(); |
| 310 |
– |
return true; |
| 311 |
– |
} |
| 312 |
– |
return false; |
| 313 |
– |
} |
| 314 |
– |
|
| 261 |
|
// Execute EMUL_OP routine |
| 262 |
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void sheepshaver_cpu::execute_emul_op(uint32 emul_op) |
| 263 |
|
{ |
| 318 |
– |
#if ENABLE_NATIVE_EMUL_OP |
| 319 |
– |
// First, filter out EMUL_OPs that can be executed without a mode switch |
| 320 |
– |
if (filter_execute_emul_op(emul_op)) |
| 321 |
– |
return; |
| 322 |
– |
#endif |
| 323 |
– |
|
| 264 |
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M68kRegisters r68; |
| 265 |
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WriteMacInt32(XLM_68K_R25, gpr(25)); |
| 266 |
|
WriteMacInt32(XLM_RUN_MODE, MODE_EMUL_OP); |
| 269 |
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for (int i = 0; i < 7; i++) |
| 270 |
|
r68.a[i] = gpr(16 + i); |
| 271 |
|
r68.a[7] = gpr(1); |
| 272 |
< |
uint32 saved_cr = get_cr() & CR_field<2>::mask(); |
| 272 |
> |
uint32 saved_cr = get_cr() & 0xff9fffff; // mask_operand::compute(11, 8) |
| 273 |
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uint32 saved_xer = get_xer(); |
| 274 |
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EmulOp(&r68, gpr(24), emul_op); |
| 275 |
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set_cr(saved_cr); |
| 313 |
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} |
| 314 |
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|
| 315 |
|
// Compile one instruction |
| 316 |
+ |
#if PPC_ENABLE_JIT |
| 317 |
|
int sheepshaver_cpu::compile1(codegen_context_t & cg_context) |
| 318 |
|
{ |
| 378 |
– |
#if PPC_ENABLE_JIT |
| 319 |
|
const instr_info_t *ii = cg_context.instr_info; |
| 320 |
|
if (ii->mnemo != PPC_I(SHEEP)) |
| 321 |
|
return COMPILE_FAILURE; |
| 386 |
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status = COMPILE_CODE_OK; |
| 387 |
|
break; |
| 388 |
|
#endif |
| 449 |
– |
case NATIVE_DISABLE_INTERRUPT: |
| 450 |
– |
dg.gen_invoke(DisableInterrupt); |
| 451 |
– |
status = COMPILE_CODE_OK; |
| 452 |
– |
break; |
| 453 |
– |
case NATIVE_ENABLE_INTERRUPT: |
| 454 |
– |
dg.gen_invoke(EnableInterrupt); |
| 455 |
– |
status = COMPILE_CODE_OK; |
| 456 |
– |
break; |
| 389 |
|
case NATIVE_BITBLT: |
| 390 |
|
dg.gen_load_T0_GPR(3); |
| 391 |
|
dg.gen_invoke_T0((void (*)(uint32))NQD_bitblt); |
| 442 |
|
|
| 443 |
|
default: { // EMUL_OP |
| 444 |
|
uint32 emul_op = EMUL_OP_field::extract(opcode) - 3; |
| 513 |
– |
#if ENABLE_NATIVE_EMUL_OP |
| 514 |
– |
typedef void (*emul_op_func_t)(dyngen_cpu_base); |
| 515 |
– |
emul_op_func_t emul_op_func = 0; |
| 516 |
– |
switch (emul_op) { |
| 517 |
– |
case OP_MICROSECONDS: |
| 518 |
– |
emul_op_func = (emul_op_func_t)nv_mem_fun(&sheepshaver_cpu::execute_emul_op_microseconds).ptr(); |
| 519 |
– |
break; |
| 520 |
– |
case OP_IDLE_TIME: |
| 521 |
– |
emul_op_func = (emul_op_func_t)nv_mem_fun(&sheepshaver_cpu::execute_emul_op_idle_time_1).ptr(); |
| 522 |
– |
break; |
| 523 |
– |
case OP_IDLE_TIME_2: |
| 524 |
– |
emul_op_func = (emul_op_func_t)nv_mem_fun(&sheepshaver_cpu::execute_emul_op_idle_time_2).ptr(); |
| 525 |
– |
break; |
| 526 |
– |
} |
| 527 |
– |
if (emul_op_func) { |
| 528 |
– |
dg.gen_invoke_CPU(emul_op_func); |
| 529 |
– |
cg_context.done_compile = false; |
| 530 |
– |
status = COMPILE_CODE_OK; |
| 531 |
– |
break; |
| 532 |
– |
} |
| 533 |
– |
#endif |
| 445 |
|
#if PPC_REENTRANT_JIT |
| 446 |
|
// Try to execute EmulOp trampoline |
| 447 |
|
dg.gen_set_PC_im(cg_context.pc + 4); |
| 461 |
|
} |
| 462 |
|
} |
| 463 |
|
return status; |
| 553 |
– |
#endif |
| 554 |
– |
return COMPILE_FAILURE; |
| 464 |
|
} |
| 556 |
– |
|
| 557 |
– |
// CPU context to preserve on interrupt |
| 558 |
– |
sheepshaver_cpu::interrupt_context::interrupt_context(sheepshaver_cpu *_cpu, const char *_where) |
| 559 |
– |
{ |
| 560 |
– |
#if SAFE_INTERRUPT_PPC >= 2 |
| 561 |
– |
cpu = _cpu; |
| 562 |
– |
where = _where; |
| 563 |
– |
|
| 564 |
– |
// Save interrupt context |
| 565 |
– |
memcpy(&gpr[0], &cpu->gpr(0), sizeof(gpr)); |
| 566 |
– |
pc = cpu->pc(); |
| 567 |
– |
lr = cpu->lr(); |
| 568 |
– |
ctr = cpu->ctr(); |
| 569 |
– |
cr = cpu->get_cr(); |
| 570 |
– |
xer = cpu->get_xer(); |
| 465 |
|
#endif |
| 572 |
– |
} |
| 573 |
– |
|
| 574 |
– |
sheepshaver_cpu::interrupt_context::~interrupt_context() |
| 575 |
– |
{ |
| 576 |
– |
#if SAFE_INTERRUPT_PPC >= 2 |
| 577 |
– |
// Check whether CPU context was preserved by interrupt |
| 578 |
– |
if (memcmp(&gpr[0], &cpu->gpr(0), sizeof(gpr)) != 0) { |
| 579 |
– |
printf("FATAL: %s: interrupt clobbers registers\n", where); |
| 580 |
– |
for (int i = 0; i < 32; i++) |
| 581 |
– |
if (gpr[i] != cpu->gpr(i)) |
| 582 |
– |
printf(" r%d: %08x -> %08x\n", i, gpr[i], cpu->gpr(i)); |
| 583 |
– |
} |
| 584 |
– |
if (pc != cpu->pc()) |
| 585 |
– |
printf("FATAL: %s: interrupt clobbers PC\n", where); |
| 586 |
– |
if (lr != cpu->lr()) |
| 587 |
– |
printf("FATAL: %s: interrupt clobbers LR\n", where); |
| 588 |
– |
if (ctr != cpu->ctr()) |
| 589 |
– |
printf("FATAL: %s: interrupt clobbers CTR\n", where); |
| 590 |
– |
if (cr != cpu->get_cr()) |
| 591 |
– |
printf("FATAL: %s: interrupt clobbers CR\n", where); |
| 592 |
– |
if (xer != cpu->get_xer()) |
| 593 |
– |
printf("FATAL: %s: interrupt clobbers XER\n", where); |
| 594 |
– |
#endif |
| 595 |
– |
} |
| 466 |
|
|
| 467 |
|
// Handle MacOS interrupt |
| 468 |
|
void sheepshaver_cpu::interrupt(uint32 entry) |
| 472 |
|
const clock_t interrupt_start = clock(); |
| 473 |
|
#endif |
| 474 |
|
|
| 605 |
– |
#if SAFE_INTERRUPT_PPC |
| 606 |
– |
static int depth = 0; |
| 607 |
– |
if (depth != 0) |
| 608 |
– |
printf("FATAL: sheepshaver_cpu::interrupt() called more than once: %d\n", depth); |
| 609 |
– |
depth++; |
| 610 |
– |
#endif |
| 611 |
– |
|
| 475 |
|
// Save program counters and branch registers |
| 476 |
|
uint32 saved_pc = pc(); |
| 477 |
|
uint32 saved_lr = lr(); |
| 525 |
|
#if EMUL_TIME_STATS |
| 526 |
|
interrupt_time += (clock() - interrupt_start); |
| 527 |
|
#endif |
| 665 |
– |
|
| 666 |
– |
#if SAFE_INTERRUPT_PPC |
| 667 |
– |
depth--; |
| 668 |
– |
#endif |
| 528 |
|
} |
| 529 |
|
|
| 530 |
|
// Execute 68k routine |
| 743 |
|
* Initialize CPU emulation |
| 744 |
|
*/ |
| 745 |
|
|
| 746 |
< |
static sigsegv_return_t sigsegv_handler(sigsegv_address_t fault_address, sigsegv_address_t fault_instruction) |
| 746 |
> |
sigsegv_return_t sigsegv_handler(sigsegv_address_t fault_address, sigsegv_address_t fault_instruction) |
| 747 |
|
{ |
| 748 |
|
#if ENABLE_VOSF |
| 749 |
|
// Handle screen fault |
| 755 |
|
const uintptr addr = (uintptr)fault_address; |
| 756 |
|
#if HAVE_SIGSEGV_SKIP_INSTRUCTION |
| 757 |
|
// Ignore writes to ROM |
| 758 |
< |
if ((addr - ROM_BASE) < ROM_SIZE) |
| 758 |
> |
if ((addr - (uintptr)ROMBaseHost) < ROM_SIZE) |
| 759 |
|
return SIGSEGV_RETURN_SKIP_INSTRUCTION; |
| 760 |
|
|
| 761 |
|
// Get program counter of target CPU |
| 802 |
|
#error "FIXME: You don't have the capability to skip instruction within signal handlers" |
| 803 |
|
#endif |
| 804 |
|
|
| 805 |
< |
printf("SIGSEGV\n"); |
| 806 |
< |
printf(" pc %p\n", fault_instruction); |
| 807 |
< |
printf(" ea %p\n", fault_address); |
| 805 |
> |
fprintf(stderr, "SIGSEGV\n"); |
| 806 |
> |
fprintf(stderr, " pc %p\n", fault_instruction); |
| 807 |
> |
fprintf(stderr, " ea %p\n", fault_address); |
| 808 |
|
dump_registers(); |
| 809 |
|
ppc_cpu->dump_log(); |
| 810 |
|
enter_mon(); |
| 815 |
|
|
| 816 |
|
void init_emul_ppc(void) |
| 817 |
|
{ |
| 818 |
+ |
// Get pointer to KernelData in host address space |
| 819 |
+ |
kernel_data = (KernelData *)Mac2HostAddr(KERNEL_DATA_BASE); |
| 820 |
+ |
|
| 821 |
|
// Initialize main CPU emulator |
| 822 |
|
ppc_cpu = new sheepshaver_cpu(); |
| 823 |
|
ppc_cpu->set_register(powerpc_registers::GPR(3), any_register((uint32)ROM_BASE + 0x30d000)); |
| 824 |
|
ppc_cpu->set_register(powerpc_registers::GPR(4), any_register(KernelDataAddr + 0x1000)); |
| 825 |
|
WriteMacInt32(XLM_RUN_MODE, MODE_68K); |
| 826 |
|
|
| 965 |
– |
// Install the handler for SIGSEGV |
| 966 |
– |
sigsegv_install_handler(sigsegv_handler); |
| 967 |
– |
|
| 827 |
|
#if ENABLE_MON |
| 828 |
|
// Install "regs" command in cxmon |
| 829 |
|
mon_add_command("regs", dump_registers, "regs Dump PowerPC registers\n"); |
| 915 |
|
|
| 916 |
|
void TriggerInterrupt(void) |
| 917 |
|
{ |
| 918 |
+ |
idle_resume(); |
| 919 |
|
#if 0 |
| 920 |
|
WriteMacInt32(0x16a, ReadMacInt32(0x16a) + 1); |
| 921 |
|
#else |
| 925 |
|
#endif |
| 926 |
|
} |
| 927 |
|
|
| 928 |
< |
void sheepshaver_cpu::handle_interrupt(void) |
| 928 |
> |
void HandleInterrupt(powerpc_registers *r) |
| 929 |
|
{ |
| 930 |
+ |
#ifdef USE_SDL_VIDEO |
| 931 |
+ |
// We must fill in the events queue in the same thread that did call SDL_SetVideoMode() |
| 932 |
+ |
SDL_PumpEvents(); |
| 933 |
+ |
#endif |
| 934 |
+ |
|
| 935 |
|
// Do nothing if interrupts are disabled |
| 936 |
< |
if (*(int32 *)XLM_IRQ_NEST > 0) |
| 936 |
> |
if (int32(ReadMacInt32(XLM_IRQ_NEST)) > 0) |
| 937 |
|
return; |
| 938 |
|
|
| 939 |
< |
// Current interrupt nest level |
| 1075 |
< |
static int interrupt_depth = 0; |
| 1076 |
< |
++interrupt_depth; |
| 939 |
> |
// Update interrupt count |
| 940 |
|
#if EMUL_TIME_STATS |
| 941 |
|
interrupt_count++; |
| 942 |
|
#endif |
| 943 |
|
|
| 1081 |
– |
// Disable MacOS stack sniffer |
| 1082 |
– |
WriteMacInt32(0x110, 0); |
| 1083 |
– |
|
| 944 |
|
// Interrupt action depends on current run mode |
| 945 |
|
switch (ReadMacInt32(XLM_RUN_MODE)) { |
| 946 |
|
case MODE_68K: |
| 947 |
|
// 68k emulator active, trigger 68k interrupt level 1 |
| 948 |
|
WriteMacInt16(tswap32(kernel_data->v[0x67c >> 2]), 1); |
| 949 |
< |
set_cr(get_cr() | tswap32(kernel_data->v[0x674 >> 2])); |
| 949 |
> |
r->cr.set(r->cr.get() | tswap32(kernel_data->v[0x674 >> 2])); |
| 950 |
|
break; |
| 951 |
|
|
| 952 |
|
#if INTERRUPTS_IN_NATIVE_MODE |
| 953 |
|
case MODE_NATIVE: |
| 954 |
|
// 68k emulator inactive, in nanokernel? |
| 955 |
< |
if (gpr(1) != KernelDataAddr && interrupt_depth == 1) { |
| 1096 |
< |
interrupt_context ctx(this, "PowerPC mode"); |
| 955 |
> |
if (r->gpr[1] != KernelDataAddr) { |
| 956 |
|
|
| 957 |
|
// Prepare for 68k interrupt level 1 |
| 958 |
|
WriteMacInt16(tswap32(kernel_data->v[0x67c >> 2]), 1); |
| 974 |
|
case MODE_EMUL_OP: |
| 975 |
|
// 68k emulator active, within EMUL_OP routine, execute 68k interrupt routine directly when interrupt level is 0 |
| 976 |
|
if ((ReadMacInt32(XLM_68K_R25) & 7) == 0) { |
| 1118 |
– |
interrupt_context ctx(this, "68k mode"); |
| 977 |
|
#if EMUL_TIME_STATS |
| 978 |
|
const clock_t interrupt_start = clock(); |
| 979 |
|
#endif |
| 982 |
|
M68kRegisters r; |
| 983 |
|
uint32 old_r25 = ReadMacInt32(XLM_68K_R25); // Save interrupt level |
| 984 |
|
WriteMacInt32(XLM_68K_R25, 0x21); // Execute with interrupt level 1 |
| 985 |
< |
static const uint8 proc[] = { |
| 985 |
> |
static const uint8 proc_template[] = { |
| 986 |
|
0x3f, 0x3c, 0x00, 0x00, // move.w #$0000,-(sp) (fake format word) |
| 987 |
|
0x48, 0x7a, 0x00, 0x0a, // pea @1(pc) (return address) |
| 988 |
|
0x40, 0xe7, // move sr,-(sp) (saved SR) |
| 990 |
|
0x4e, 0xd0, // jmp (a0) |
| 991 |
|
M68K_RTS >> 8, M68K_RTS & 0xff // @1 |
| 992 |
|
}; |
| 993 |
< |
Execute68k((uint32)proc, &r); |
| 993 |
> |
BUILD_SHEEPSHAVER_PROCEDURE(proc); |
| 994 |
> |
Execute68k(proc, &r); |
| 995 |
|
WriteMacInt32(XLM_68K_R25, old_r25); // Restore interrupt level |
| 996 |
|
#else |
| 997 |
|
// Only update cursor |
| 1010 |
|
break; |
| 1011 |
|
#endif |
| 1012 |
|
} |
| 1154 |
– |
|
| 1155 |
– |
// We are done with this interrupt |
| 1156 |
– |
--interrupt_depth; |
| 1013 |
|
} |
| 1014 |
|
|
| 1015 |
|
static void get_resource(void); |
| 1037 |
|
VideoVBL(); |
| 1038 |
|
break; |
| 1039 |
|
case NATIVE_VIDEO_DO_DRIVER_IO: |
| 1040 |
< |
gpr(3) = (int32)(int16)VideoDoDriverIO((void *)gpr(3), (void *)gpr(4), |
| 1185 |
< |
(void *)gpr(5), gpr(6), gpr(7)); |
| 1040 |
> |
gpr(3) = (int32)(int16)VideoDoDriverIO(gpr(3), gpr(4), gpr(5), gpr(6), gpr(7)); |
| 1041 |
|
break; |
| 1187 |
– |
#ifdef WORDS_BIGENDIAN |
| 1042 |
|
case NATIVE_ETHER_IRQ: |
| 1043 |
|
EtherIRQ(); |
| 1044 |
|
break; |
| 1060 |
|
case NATIVE_ETHER_RSRV: |
| 1061 |
|
gpr(3) = ether_rsrv((queue_t *)gpr(3)); |
| 1062 |
|
break; |
| 1209 |
– |
#else |
| 1210 |
– |
case NATIVE_ETHER_INIT: |
| 1211 |
– |
// FIXME: needs more complicated thunks |
| 1212 |
– |
gpr(3) = false; |
| 1213 |
– |
break; |
| 1214 |
– |
#endif |
| 1063 |
|
case NATIVE_SYNC_HOOK: |
| 1064 |
|
gpr(3) = NQD_sync_hook(gpr(3)); |
| 1065 |
|
break; |
| 1114 |
|
get_resource_callbacks[selector - NATIVE_GET_RESOURCE](); |
| 1115 |
|
break; |
| 1116 |
|
} |
| 1269 |
– |
case NATIVE_DISABLE_INTERRUPT: |
| 1270 |
– |
DisableInterrupt(); |
| 1271 |
– |
break; |
| 1272 |
– |
case NATIVE_ENABLE_INTERRUPT: |
| 1273 |
– |
EnableInterrupt(); |
| 1274 |
– |
break; |
| 1117 |
|
case NATIVE_MAKE_EXECUTABLE: |
| 1118 |
< |
MakeExecutable(0, (void *)gpr(4), gpr(5)); |
| 1118 |
> |
MakeExecutable(0, gpr(4), gpr(5)); |
| 1119 |
|
break; |
| 1120 |
|
case NATIVE_CHECK_LOAD_INVOC: |
| 1121 |
|
check_load_invoc(gpr(3), gpr(4), gpr(5)); |
