43 |
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#include <stdio.h> |
44 |
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#include <stdlib.h> |
45 |
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|
46 |
+ |
#ifdef USE_SDL_VIDEO |
47 |
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#include <SDL_events.h> |
48 |
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#endif |
49 |
+ |
|
50 |
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#if ENABLE_MON |
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#include "mon.h" |
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#include "mon_disass.h" |
105 |
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// Interrupts in native mode? |
106 |
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#define INTERRUPTS_IN_NATIVE_MODE 1 |
107 |
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|
104 |
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// Enable native EMUL_OPs to be run without a mode switch |
105 |
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#define ENABLE_NATIVE_EMUL_OP 1 |
106 |
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|
108 |
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// Pointer to Kernel Data |
109 |
< |
static KernelData * const kernel_data = (KernelData *)KERNEL_DATA_BASE; |
109 |
> |
static KernelData * kernel_data; |
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|
111 |
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// SIGSEGV handler |
112 |
< |
static sigsegv_return_t sigsegv_handler(sigsegv_address_t, sigsegv_address_t); |
112 |
> |
sigsegv_return_t sigsegv_handler(sigsegv_address_t, sigsegv_address_t); |
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|
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#if PPC_ENABLE_JIT && PPC_REENTRANT_JIT |
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// Special trampolines for EmulOp and NativeOp |
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void init_decoder(); |
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void execute_sheep(uint32 opcode); |
141 |
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|
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// Filter out EMUL_OP routines that only call native code |
142 |
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bool filter_execute_emul_op(uint32 emul_op); |
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|
144 |
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// "Native" EMUL_OP routines |
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void execute_emul_op_microseconds(); |
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void execute_emul_op_idle_time_1(); |
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void execute_emul_op_idle_time_2(); |
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|
142 |
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// CPU context to preserve on interrupt |
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class interrupt_context { |
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uint32 gpr[32]; |
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typedef bit_field< 20, 25 > NATIVE_OP_field; |
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typedef bit_field< 26, 31 > EMUL_OP_field; |
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|
273 |
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// "Native" EMUL_OP routines |
274 |
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#define GPR_A(REG) gpr(16 + (REG)) |
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#define GPR_D(REG) gpr( 8 + (REG)) |
276 |
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|
277 |
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void sheepshaver_cpu::execute_emul_op_microseconds() |
278 |
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{ |
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Microseconds(GPR_A(0), GPR_D(0)); |
280 |
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} |
281 |
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|
282 |
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void sheepshaver_cpu::execute_emul_op_idle_time_1() |
283 |
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{ |
284 |
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// Sleep if no events pending |
285 |
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if (ReadMacInt32(0x14c) == 0) |
286 |
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Delay_usec(16667); |
287 |
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GPR_A(0) = ReadMacInt32(0x2b6); |
288 |
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} |
289 |
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|
290 |
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void sheepshaver_cpu::execute_emul_op_idle_time_2() |
291 |
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{ |
292 |
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// Sleep if no events pending |
293 |
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if (ReadMacInt32(0x14c) == 0) |
294 |
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Delay_usec(16667); |
295 |
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GPR_D(0) = (uint32)-2; |
296 |
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} |
297 |
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|
298 |
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// Filter out EMUL_OP routines that only call native code |
299 |
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bool sheepshaver_cpu::filter_execute_emul_op(uint32 emul_op) |
300 |
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{ |
301 |
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switch (emul_op) { |
302 |
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case OP_MICROSECONDS: |
303 |
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execute_emul_op_microseconds(); |
304 |
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return true; |
305 |
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case OP_IDLE_TIME: |
306 |
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execute_emul_op_idle_time_1(); |
307 |
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return true; |
308 |
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case OP_IDLE_TIME_2: |
309 |
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execute_emul_op_idle_time_2(); |
310 |
– |
return true; |
311 |
– |
} |
312 |
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return false; |
313 |
– |
} |
314 |
– |
|
266 |
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// Execute EMUL_OP routine |
267 |
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void sheepshaver_cpu::execute_emul_op(uint32 emul_op) |
268 |
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{ |
318 |
– |
#if ENABLE_NATIVE_EMUL_OP |
319 |
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// First, filter out EMUL_OPs that can be executed without a mode switch |
320 |
– |
if (filter_execute_emul_op(emul_op)) |
321 |
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return; |
322 |
– |
#endif |
323 |
– |
|
269 |
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M68kRegisters r68; |
270 |
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WriteMacInt32(XLM_68K_R25, gpr(25)); |
271 |
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WriteMacInt32(XLM_RUN_MODE, MODE_EMUL_OP); |
391 |
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status = COMPILE_CODE_OK; |
392 |
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break; |
393 |
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#endif |
449 |
– |
case NATIVE_DISABLE_INTERRUPT: |
450 |
– |
dg.gen_invoke(DisableInterrupt); |
451 |
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status = COMPILE_CODE_OK; |
452 |
– |
break; |
453 |
– |
case NATIVE_ENABLE_INTERRUPT: |
454 |
– |
dg.gen_invoke(EnableInterrupt); |
455 |
– |
status = COMPILE_CODE_OK; |
456 |
– |
break; |
394 |
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case NATIVE_BITBLT: |
395 |
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dg.gen_load_T0_GPR(3); |
396 |
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dg.gen_invoke_T0((void (*)(uint32))NQD_bitblt); |
447 |
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|
448 |
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default: { // EMUL_OP |
449 |
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uint32 emul_op = EMUL_OP_field::extract(opcode) - 3; |
513 |
– |
#if ENABLE_NATIVE_EMUL_OP |
514 |
– |
typedef void (*emul_op_func_t)(dyngen_cpu_base); |
515 |
– |
emul_op_func_t emul_op_func = 0; |
516 |
– |
switch (emul_op) { |
517 |
– |
case OP_MICROSECONDS: |
518 |
– |
emul_op_func = (emul_op_func_t)nv_mem_fun(&sheepshaver_cpu::execute_emul_op_microseconds).ptr(); |
519 |
– |
break; |
520 |
– |
case OP_IDLE_TIME: |
521 |
– |
emul_op_func = (emul_op_func_t)nv_mem_fun(&sheepshaver_cpu::execute_emul_op_idle_time_1).ptr(); |
522 |
– |
break; |
523 |
– |
case OP_IDLE_TIME_2: |
524 |
– |
emul_op_func = (emul_op_func_t)nv_mem_fun(&sheepshaver_cpu::execute_emul_op_idle_time_2).ptr(); |
525 |
– |
break; |
526 |
– |
} |
527 |
– |
if (emul_op_func) { |
528 |
– |
dg.gen_invoke_CPU(emul_op_func); |
529 |
– |
cg_context.done_compile = false; |
530 |
– |
status = COMPILE_CODE_OK; |
531 |
– |
break; |
532 |
– |
} |
533 |
– |
#endif |
450 |
|
#if PPC_REENTRANT_JIT |
451 |
|
// Try to execute EmulOp trampoline |
452 |
|
dg.gen_set_PC_im(cg_context.pc + 4); |
800 |
|
* Initialize CPU emulation |
801 |
|
*/ |
802 |
|
|
803 |
< |
static sigsegv_return_t sigsegv_handler(sigsegv_address_t fault_address, sigsegv_address_t fault_instruction) |
803 |
> |
sigsegv_return_t sigsegv_handler(sigsegv_address_t fault_address, sigsegv_address_t fault_instruction) |
804 |
|
{ |
805 |
|
#if ENABLE_VOSF |
806 |
|
// Handle screen fault |
812 |
|
const uintptr addr = (uintptr)fault_address; |
813 |
|
#if HAVE_SIGSEGV_SKIP_INSTRUCTION |
814 |
|
// Ignore writes to ROM |
815 |
< |
if ((addr - ROM_BASE) < ROM_SIZE) |
815 |
> |
if ((addr - (uintptr)ROMBaseHost) < ROM_SIZE) |
816 |
|
return SIGSEGV_RETURN_SKIP_INSTRUCTION; |
817 |
|
|
818 |
|
// Get program counter of target CPU |
872 |
|
|
873 |
|
void init_emul_ppc(void) |
874 |
|
{ |
875 |
+ |
// Get pointer to KernelData in host address space |
876 |
+ |
kernel_data = (KernelData *)Mac2HostAddr(KERNEL_DATA_BASE); |
877 |
+ |
|
878 |
|
// Initialize main CPU emulator |
879 |
|
ppc_cpu = new sheepshaver_cpu(); |
880 |
|
ppc_cpu->set_register(powerpc_registers::GPR(3), any_register((uint32)ROM_BASE + 0x30d000)); |
881 |
|
ppc_cpu->set_register(powerpc_registers::GPR(4), any_register(KernelDataAddr + 0x1000)); |
882 |
|
WriteMacInt32(XLM_RUN_MODE, MODE_68K); |
883 |
|
|
965 |
– |
// Install the handler for SIGSEGV |
966 |
– |
sigsegv_install_handler(sigsegv_handler); |
967 |
– |
|
884 |
|
#if ENABLE_MON |
885 |
|
// Install "regs" command in cxmon |
886 |
|
mon_add_command("regs", dump_registers, "regs Dump PowerPC registers\n"); |
983 |
|
|
984 |
|
void sheepshaver_cpu::handle_interrupt(void) |
985 |
|
{ |
986 |
+ |
#ifdef USE_SDL_VIDEO |
987 |
+ |
// We must fill in the events queue in the same thread that did call SDL_SetVideoMode() |
988 |
+ |
SDL_PumpEvents(); |
989 |
+ |
#endif |
990 |
+ |
|
991 |
|
// Do nothing if interrupts are disabled |
992 |
< |
if (*(int32 *)XLM_IRQ_NEST > 0) |
992 |
> |
if (int32(ReadMacInt32(XLM_IRQ_NEST)) > 0) |
993 |
|
return; |
994 |
|
|
995 |
|
// Current interrupt nest level |
1053 |
|
0x4e, 0xd0, // jmp (a0) |
1054 |
|
M68K_RTS >> 8, M68K_RTS & 0xff // @1 |
1055 |
|
}; |
1056 |
< |
Execute68k((uint32)proc, &r); |
1056 |
> |
Execute68k(Host2MacAddr((uint8 *)proc), &r); |
1057 |
|
WriteMacInt32(XLM_68K_R25, old_r25); // Restore interrupt level |
1058 |
|
#else |
1059 |
|
// Only update cursor |
1102 |
|
VideoVBL(); |
1103 |
|
break; |
1104 |
|
case NATIVE_VIDEO_DO_DRIVER_IO: |
1105 |
< |
gpr(3) = (int32)(int16)VideoDoDriverIO((void *)gpr(3), (void *)gpr(4), |
1185 |
< |
(void *)gpr(5), gpr(6), gpr(7)); |
1105 |
> |
gpr(3) = (int32)(int16)VideoDoDriverIO(gpr(3), gpr(4), gpr(5), gpr(6), gpr(7)); |
1106 |
|
break; |
1107 |
|
#ifdef WORDS_BIGENDIAN |
1108 |
|
case NATIVE_ETHER_IRQ: |
1186 |
|
get_resource_callbacks[selector - NATIVE_GET_RESOURCE](); |
1187 |
|
break; |
1188 |
|
} |
1269 |
– |
case NATIVE_DISABLE_INTERRUPT: |
1270 |
– |
DisableInterrupt(); |
1271 |
– |
break; |
1272 |
– |
case NATIVE_ENABLE_INTERRUPT: |
1273 |
– |
EnableInterrupt(); |
1274 |
– |
break; |
1189 |
|
case NATIVE_MAKE_EXECUTABLE: |
1190 |
< |
MakeExecutable(0, (void *)gpr(4), gpr(5)); |
1190 |
> |
MakeExecutable(0, gpr(4), gpr(5)); |
1191 |
|
break; |
1192 |
|
case NATIVE_CHECK_LOAD_INVOC: |
1193 |
|
check_load_invoc(gpr(3), gpr(4), gpr(5)); |