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/* |
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* sheepshaver_glue.cpp - Glue Kheperix CPU to SheepShaver CPU engine interface |
3 |
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* |
4 |
< |
* SheepShaver (C) 1997-2002 Christian Bauer and Marc Hellwig |
4 |
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* SheepShaver (C) 1997-2004 Christian Bauer and Marc Hellwig |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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#include "sysdeps.h" |
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#include "cpu_emulation.h" |
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#include "main.h" |
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#include "prefs.h" |
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#include "xlowmem.h" |
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#include "emul_op.h" |
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#include "rom_patches.h" |
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#include "macos_util.h" |
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#include "block-alloc.hpp" |
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#include "sigsegv.h" |
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#include "spcflags.h" |
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#include "cpu/ppc/ppc-cpu.hpp" |
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#include "cpu/ppc/ppc-operations.hpp" |
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#include "cpu/ppc/ppc-instructions.hpp" |
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#include "thunks.h" |
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|
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// Used for NativeOp trampolines |
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#include "video.h" |
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#include "name_registry.h" |
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#include "serial.h" |
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#include "ether.h" |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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|
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#if ENABLE_MON |
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#include "mon.h" |
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#include "mon_disass.h" |
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#endif |
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|
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#define DEBUG 1 |
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#define DEBUG 0 |
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#include "debug.h" |
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|
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// Emulation time statistics |
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#define EMUL_TIME_STATS 1 |
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|
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#if EMUL_TIME_STATS |
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static clock_t emul_start_time; |
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static uint32 interrupt_count = 0; |
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static clock_t interrupt_time = 0; |
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static uint32 exec68k_count = 0; |
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static clock_t exec68k_time = 0; |
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static uint32 native_exec_count = 0; |
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static clock_t native_exec_time = 0; |
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static uint32 macos_exec_count = 0; |
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static clock_t macos_exec_time = 0; |
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#endif |
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|
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static void enter_mon(void) |
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{ |
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// Start up mon in real-mode |
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#endif |
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} |
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|
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// From main_*.cpp |
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extern uintptr SignalStackBase(); |
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|
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// From rsrc_patches.cpp |
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extern "C" void check_load_invoc(uint32 type, int16 id, uint32 h); |
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|
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// PowerPC EmulOp to exit from emulation looop |
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const uint32 POWERPC_EXEC_RETURN = POWERPC_EMUL_OP | 1; |
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|
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// Enable multicore (main/interrupts) cpu emulation? |
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#define MULTICORE_CPU 0 |
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#define MULTICORE_CPU (ASYNC_IRQ ? 1 : 0) |
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|
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// Enable Execute68k() safety checks? |
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#define SAFE_EXEC_68K 1 |
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// Interrupts in native mode? |
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#define INTERRUPTS_IN_NATIVE_MODE 1 |
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|
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// 68k Emulator Data |
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struct EmulatorData { |
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uint32 v[0x400]; |
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}; |
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// Pointer to Kernel Data |
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static KernelData * const kernel_data = (KernelData *)KERNEL_DATA_BASE; |
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|
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// Kernel Data |
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struct KernelData { |
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uint32 v[0x400]; |
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EmulatorData ed; |
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}; |
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// SIGSEGV handler |
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static sigsegv_return_t sigsegv_handler(sigsegv_address_t, sigsegv_address_t); |
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|
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// Pointer to Kernel Data |
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static KernelData * const kernel_data = (KernelData *)0x68ffe000; |
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// JIT Compiler enabled? |
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static inline bool enable_jit_p() |
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{ |
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return PrefsFindBool("jit"); |
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} |
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/** |
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* PowerPC emulator glue with special 'sheep' opcodes |
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**/ |
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|
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struct sheepshaver_exec_return { }; |
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enum { |
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PPC_I(SHEEP) = PPC_I(MAX), |
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PPC_I(SHEEP_MAX) |
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}; |
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class sheepshaver_cpu |
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: public powerpc_cpu |
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|
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public: |
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|
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sheepshaver_cpu() |
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: powerpc_cpu() |
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{ init_decoder(); } |
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// Constructor |
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sheepshaver_cpu(); |
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|
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// Condition Register accessors |
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// CR & XER accessors |
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uint32 get_cr() const { return cr().get(); } |
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void set_cr(uint32 v) { cr().set(v); } |
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uint32 get_xer() const { return xer().get(); } |
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void set_xer(uint32 v) { xer().set(v); } |
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|
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// Execution loop |
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void execute(uint32 pc); |
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// Execute EMUL_OP routine |
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void execute_emul_op(uint32 emul_op); |
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|
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// Execute 68k routine |
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void execute_68k(uint32 entry, M68kRegisters *r); |
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// Execute MacOS/PPC code |
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uint32 execute_macos_code(uint32 tvect, int nargs, uint32 const *args); |
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|
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// Compile one instruction |
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virtual bool compile1(codegen_context_t & cg_context); |
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|
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// Resource manager thunk |
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void get_resource(uint32 old_get_resource); |
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|
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// Handle MacOS interrupt |
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void interrupt(uint32 entry, sheepshaver_cpu *cpu); |
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void interrupt(uint32 entry); |
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void handle_interrupt(); |
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|
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// spcflags for interrupts handling |
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static uint32 spcflags; |
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|
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// Lazy memory allocator (one item at a time) |
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void *operator new(size_t size) |
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{ return allocator_helper< sheepshaver_cpu, lazy_allocator >::allocate(); } |
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void operator delete(void *p) |
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{ allocator_helper< sheepshaver_cpu, lazy_allocator >::deallocate(p); } |
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// FIXME: really make surre array allocation fail at link time? |
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void *operator new[](size_t); |
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void operator delete[](void *p); |
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// Make sure the SIGSEGV handler can access CPU registers |
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friend sigsegv_return_t sigsegv_handler(sigsegv_address_t, sigsegv_address_t); |
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}; |
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|
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uint32 sheepshaver_cpu::spcflags = 0; |
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lazy_allocator< sheepshaver_cpu > allocator_helper< sheepshaver_cpu, lazy_allocator >::allocator; |
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> |
// Memory allocator returning areas aligned on 16-byte boundaries |
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void *operator new(size_t size) |
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{ |
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void *p; |
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|
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< |
void sheepshaver_cpu::init_decoder() |
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> |
#if defined(HAVE_POSIX_MEMALIGN) |
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if (posix_memalign(&p, 16, size) != 0) |
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throw std::bad_alloc(); |
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> |
#elif defined(HAVE_MEMALIGN) |
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> |
p = memalign(16, size); |
176 |
> |
#elif defined(HAVE_VALLOC) |
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p = valloc(size); // page-aligned! |
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> |
#else |
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> |
/* XXX: handle padding ourselves */ |
180 |
> |
p = malloc(size); |
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#endif |
182 |
> |
|
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return p; |
184 |
> |
} |
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> |
|
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> |
void operator delete(void *p) |
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{ |
188 |
< |
#ifndef PPC_NO_STATIC_II_INDEX_TABLE |
189 |
< |
static bool initialized = false; |
190 |
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if (initialized) |
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return; |
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initialized = true; |
188 |
> |
#if defined(HAVE_MEMALIGN) || defined(HAVE_VALLOC) |
189 |
> |
#if defined(__GLIBC__) |
190 |
> |
// this is known to work only with GNU libc |
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free(p); |
192 |
> |
#endif |
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#else |
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free(p); |
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#endif |
196 |
+ |
} |
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|
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sheepshaver_cpu::sheepshaver_cpu() |
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: powerpc_cpu(enable_jit_p()) |
200 |
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{ |
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init_decoder(); |
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} |
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|
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void sheepshaver_cpu::init_decoder() |
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{ |
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static const instr_info_t sheep_ii_table[] = { |
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{ "sheep", |
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(execute_fn)&sheepshaver_cpu::execute_sheep, |
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(execute_pmf)&sheepshaver_cpu::execute_sheep, |
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NULL, |
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< |
D_form, 6, 0, CFLOW_TRAP |
210 |
> |
PPC_I(SHEEP), |
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> |
D_form, 6, 0, CFLOW_JUMP | CFLOW_TRAP |
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} |
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}; |
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|
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typedef bit_field< 21, 25 > NATIVE_OP_field; |
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typedef bit_field< 26, 31 > EMUL_OP_field; |
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|
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// Execute EMUL_OP routine |
239 |
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void sheepshaver_cpu::execute_emul_op(uint32 emul_op) |
240 |
+ |
{ |
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M68kRegisters r68; |
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WriteMacInt32(XLM_68K_R25, gpr(25)); |
243 |
+ |
WriteMacInt32(XLM_RUN_MODE, MODE_EMUL_OP); |
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+ |
for (int i = 0; i < 8; i++) |
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r68.d[i] = gpr(8 + i); |
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for (int i = 0; i < 7; i++) |
247 |
+ |
r68.a[i] = gpr(16 + i); |
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+ |
r68.a[7] = gpr(1); |
249 |
+ |
uint32 saved_cr = get_cr() & CR_field<2>::mask(); |
250 |
+ |
uint32 saved_xer = get_xer(); |
251 |
+ |
EmulOp(&r68, gpr(24), emul_op); |
252 |
+ |
set_cr(saved_cr); |
253 |
+ |
set_xer(saved_xer); |
254 |
+ |
for (int i = 0; i < 8; i++) |
255 |
+ |
gpr(8 + i) = r68.d[i]; |
256 |
+ |
for (int i = 0; i < 7; i++) |
257 |
+ |
gpr(16 + i) = r68.a[i]; |
258 |
+ |
gpr(1) = r68.a[7]; |
259 |
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WriteMacInt32(XLM_RUN_MODE, MODE_68K); |
260 |
+ |
} |
261 |
+ |
|
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// Execute SheepShaver instruction |
263 |
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void sheepshaver_cpu::execute_sheep(uint32 opcode) |
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{ |
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case 0: // EMUL_RETURN |
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QuitEmulator(); |
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break; |
272 |
< |
|
272 |
> |
|
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case 1: // EXEC_RETURN |
274 |
< |
throw sheepshaver_exec_return(); |
274 |
> |
spcflags().set(SPCFLAG_CPU_EXEC_RETURN); |
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break; |
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|
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case 2: // EXEC_NATIVE |
282 |
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pc() += 4; |
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break; |
284 |
|
|
285 |
< |
default: { // EMUL_OP |
286 |
< |
M68kRegisters r68; |
209 |
< |
WriteMacInt32(XLM_68K_R25, gpr(25)); |
210 |
< |
WriteMacInt32(XLM_RUN_MODE, MODE_EMUL_OP); |
211 |
< |
for (int i = 0; i < 8; i++) |
212 |
< |
r68.d[i] = gpr(8 + i); |
213 |
< |
for (int i = 0; i < 7; i++) |
214 |
< |
r68.a[i] = gpr(16 + i); |
215 |
< |
r68.a[7] = gpr(1); |
216 |
< |
EmulOp(&r68, gpr(24), EMUL_OP_field::extract(opcode) - 3); |
217 |
< |
for (int i = 0; i < 8; i++) |
218 |
< |
gpr(8 + i) = r68.d[i]; |
219 |
< |
for (int i = 0; i < 7; i++) |
220 |
< |
gpr(16 + i) = r68.a[i]; |
221 |
< |
gpr(1) = r68.a[7]; |
222 |
< |
WriteMacInt32(XLM_RUN_MODE, MODE_68K); |
285 |
> |
default: // EMUL_OP |
286 |
> |
execute_emul_op(EMUL_OP_field::extract(opcode) - 3); |
287 |
|
pc() += 4; |
288 |
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break; |
289 |
|
} |
226 |
– |
} |
290 |
|
} |
291 |
|
|
292 |
< |
// Checks for pending interrupts |
293 |
< |
struct execute_nothing { |
294 |
< |
static inline void execute(powerpc_cpu *) { } |
295 |
< |
}; |
292 |
> |
// Compile one instruction |
293 |
> |
bool sheepshaver_cpu::compile1(codegen_context_t & cg_context) |
294 |
> |
{ |
295 |
> |
#if PPC_ENABLE_JIT |
296 |
> |
const instr_info_t *ii = cg_context.instr_info; |
297 |
> |
if (ii->mnemo != PPC_I(SHEEP)) |
298 |
> |
return false; |
299 |
> |
|
300 |
> |
bool compiled = false; |
301 |
> |
powerpc_dyngen & dg = cg_context.codegen; |
302 |
> |
uint32 opcode = cg_context.opcode; |
303 |
|
|
304 |
< |
static void HandleInterrupt(void); |
304 |
> |
switch (opcode & 0x3f) { |
305 |
> |
case 0: // EMUL_RETURN |
306 |
> |
dg.gen_invoke(QuitEmulator); |
307 |
> |
compiled = true; |
308 |
> |
break; |
309 |
|
|
310 |
< |
struct execute_spcflags_check { |
311 |
< |
static inline void execute(powerpc_cpu *cpu) { |
312 |
< |
if (SPCFLAGS_TEST(SPCFLAG_ALL_BUT_EXEC_RETURN)) { |
313 |
< |
if (SPCFLAGS_TEST( SPCFLAG_ENTER_MON )) { |
314 |
< |
SPCFLAGS_CLEAR( SPCFLAG_ENTER_MON ); |
315 |
< |
enter_mon(); |
316 |
< |
} |
317 |
< |
if (SPCFLAGS_TEST( SPCFLAG_DOINT )) { |
318 |
< |
SPCFLAGS_CLEAR( SPCFLAG_DOINT ); |
319 |
< |
HandleInterrupt(); |
320 |
< |
} |
321 |
< |
if (SPCFLAGS_TEST( SPCFLAG_INT )) { |
322 |
< |
SPCFLAGS_CLEAR( SPCFLAG_INT ); |
323 |
< |
SPCFLAGS_SET( SPCFLAG_DOINT ); |
310 |
> |
case 1: // EXEC_RETURN |
311 |
> |
dg.gen_spcflags_set(SPCFLAG_CPU_EXEC_RETURN); |
312 |
> |
compiled = true; |
313 |
> |
break; |
314 |
> |
|
315 |
> |
case 2: { // EXEC_NATIVE |
316 |
> |
uint32 selector = NATIVE_OP_field::extract(opcode); |
317 |
> |
switch (selector) { |
318 |
> |
case NATIVE_PATCH_NAME_REGISTRY: |
319 |
> |
dg.gen_invoke(DoPatchNameRegistry); |
320 |
> |
compiled = true; |
321 |
> |
break; |
322 |
> |
case NATIVE_VIDEO_INSTALL_ACCEL: |
323 |
> |
dg.gen_invoke(VideoInstallAccel); |
324 |
> |
compiled = true; |
325 |
> |
break; |
326 |
> |
case NATIVE_VIDEO_VBL: |
327 |
> |
dg.gen_invoke(VideoVBL); |
328 |
> |
compiled = true; |
329 |
> |
break; |
330 |
> |
case NATIVE_GET_RESOURCE: |
331 |
> |
case NATIVE_GET_1_RESOURCE: |
332 |
> |
case NATIVE_GET_IND_RESOURCE: |
333 |
> |
case NATIVE_GET_1_IND_RESOURCE: |
334 |
> |
case NATIVE_R_GET_RESOURCE: { |
335 |
> |
static const uint32 get_resource_ptr[] = { |
336 |
> |
XLM_GET_RESOURCE, |
337 |
> |
XLM_GET_1_RESOURCE, |
338 |
> |
XLM_GET_IND_RESOURCE, |
339 |
> |
XLM_GET_1_IND_RESOURCE, |
340 |
> |
XLM_R_GET_RESOURCE |
341 |
> |
}; |
342 |
> |
uint32 old_get_resource = ReadMacInt32(get_resource_ptr[selector - NATIVE_GET_RESOURCE]); |
343 |
> |
typedef void (*func_t)(dyngen_cpu_base, uint32); |
344 |
> |
func_t func = (func_t)nv_mem_fun(&sheepshaver_cpu::get_resource).ptr(); |
345 |
> |
dg.gen_invoke_CPU_im(func, old_get_resource); |
346 |
> |
compiled = true; |
347 |
> |
break; |
348 |
> |
} |
349 |
> |
case NATIVE_DISABLE_INTERRUPT: |
350 |
> |
dg.gen_invoke(DisableInterrupt); |
351 |
> |
compiled = true; |
352 |
> |
break; |
353 |
> |
case NATIVE_ENABLE_INTERRUPT: |
354 |
> |
dg.gen_invoke(EnableInterrupt); |
355 |
> |
compiled = true; |
356 |
> |
break; |
357 |
> |
case NATIVE_CHECK_LOAD_INVOC: |
358 |
> |
dg.gen_load_T0_GPR(3); |
359 |
> |
dg.gen_load_T1_GPR(4); |
360 |
> |
dg.gen_se_16_32_T1(); |
361 |
> |
dg.gen_load_T2_GPR(5); |
362 |
> |
dg.gen_invoke_T0_T1_T2((void (*)(uint32, uint32, uint32))check_load_invoc); |
363 |
> |
compiled = true; |
364 |
> |
break; |
365 |
> |
} |
366 |
> |
if (FN_field::test(opcode)) { |
367 |
> |
if (compiled) { |
368 |
> |
dg.gen_load_A0_LR(); |
369 |
> |
dg.gen_set_PC_A0(); |
370 |
|
} |
371 |
+ |
cg_context.done_compile = true; |
372 |
|
} |
373 |
+ |
else |
374 |
+ |
cg_context.done_compile = false; |
375 |
+ |
break; |
376 |
|
} |
253 |
– |
}; |
377 |
|
|
378 |
< |
// Execution loop |
379 |
< |
void sheepshaver_cpu::execute(uint32 entry) |
380 |
< |
{ |
381 |
< |
try { |
382 |
< |
pc() = entry; |
383 |
< |
powerpc_cpu::do_execute<execute_nothing, execute_spcflags_check>(); |
384 |
< |
} |
262 |
< |
catch (sheepshaver_exec_return const &) { |
263 |
< |
// Nothing, simply return |
378 |
> |
default: { // EMUL_OP |
379 |
> |
typedef void (*func_t)(dyngen_cpu_base, uint32); |
380 |
> |
func_t func = (func_t)nv_mem_fun(&sheepshaver_cpu::execute_emul_op).ptr(); |
381 |
> |
dg.gen_invoke_CPU_im(func, EMUL_OP_field::extract(opcode) - 3); |
382 |
> |
cg_context.done_compile = false; |
383 |
> |
compiled = true; |
384 |
> |
break; |
385 |
|
} |
265 |
– |
catch (...) { |
266 |
– |
printf("ERROR: execute() received an unknown exception!\n"); |
267 |
– |
QuitEmulator(); |
386 |
|
} |
387 |
+ |
return compiled; |
388 |
+ |
#endif |
389 |
+ |
return false; |
390 |
|
} |
391 |
|
|
392 |
|
// Handle MacOS interrupt |
393 |
< |
void sheepshaver_cpu::interrupt(uint32 entry, sheepshaver_cpu *cpu) |
393 |
> |
void sheepshaver_cpu::interrupt(uint32 entry) |
394 |
|
{ |
395 |
< |
#if MULTICORE_CPU |
396 |
< |
// Initialize stack pointer from previous CPU running |
397 |
< |
gpr(1) = cpu->gpr(1); |
398 |
< |
#else |
395 |
> |
#if EMUL_TIME_STATS |
396 |
> |
interrupt_count++; |
397 |
> |
const clock_t interrupt_start = clock(); |
398 |
> |
#endif |
399 |
> |
|
400 |
> |
#if !MULTICORE_CPU |
401 |
|
// Save program counters and branch registers |
402 |
|
uint32 saved_pc = pc(); |
403 |
|
uint32 saved_lr = lr(); |
404 |
|
uint32 saved_ctr= ctr(); |
405 |
+ |
uint32 saved_sp = gpr(1); |
406 |
|
#endif |
407 |
|
|
408 |
< |
// Create stack frame |
409 |
< |
gpr(1) -= 64; |
408 |
> |
// Initialize stack pointer to SheepShaver alternate stack base |
409 |
> |
gpr(1) = SignalStackBase() - 64; |
410 |
|
|
411 |
|
// Build trampoline to return from interrupt |
412 |
< |
uint32 trampoline[] = { POWERPC_EMUL_OP | 1 }; |
412 |
> |
SheepVar32 trampoline = POWERPC_EXEC_RETURN; |
413 |
|
|
414 |
|
// Prepare registers for nanokernel interrupt routine |
415 |
< |
kernel_data->v[0x004 >> 2] = gpr(1); |
416 |
< |
kernel_data->v[0x018 >> 2] = gpr(6); |
415 |
> |
kernel_data->v[0x004 >> 2] = htonl(gpr(1)); |
416 |
> |
kernel_data->v[0x018 >> 2] = htonl(gpr(6)); |
417 |
|
|
418 |
< |
gpr(6) = kernel_data->v[0x65c >> 2]; |
418 |
> |
gpr(6) = ntohl(kernel_data->v[0x65c >> 2]); |
419 |
|
assert(gpr(6) != 0); |
420 |
|
WriteMacInt32(gpr(6) + 0x13c, gpr(7)); |
421 |
|
WriteMacInt32(gpr(6) + 0x144, gpr(8)); |
426 |
|
WriteMacInt32(gpr(6) + 0x16c, gpr(13)); |
427 |
|
|
428 |
|
gpr(1) = KernelDataAddr; |
429 |
< |
gpr(7) = kernel_data->v[0x660 >> 2]; |
429 |
> |
gpr(7) = ntohl(kernel_data->v[0x660 >> 2]); |
430 |
|
gpr(8) = 0; |
431 |
< |
gpr(10) = (uint32)trampoline; |
432 |
< |
gpr(12) = (uint32)trampoline; |
433 |
< |
gpr(13) = cr().get(); |
431 |
> |
gpr(10) = trampoline.addr(); |
432 |
> |
gpr(12) = trampoline.addr(); |
433 |
> |
gpr(13) = get_cr(); |
434 |
|
|
435 |
|
// rlwimi. r7,r7,8,0,0 |
436 |
|
uint32 result = op_ppc_rlwimi::apply(gpr(7), 8, 0x80000000, gpr(7)); |
438 |
|
gpr(7) = result; |
439 |
|
|
440 |
|
gpr(11) = 0xf072; // MSR (SRR1) |
441 |
< |
cr().set((gpr(11) & 0x0fff0000) | (cr().get() & ~0x0fff0000)); |
441 |
> |
cr().set((gpr(11) & 0x0fff0000) | (get_cr() & ~0x0fff0000)); |
442 |
|
|
443 |
|
// Enter nanokernel |
444 |
|
execute(entry); |
445 |
|
|
322 |
– |
// Cleanup stack |
323 |
– |
gpr(1) += 64; |
324 |
– |
|
446 |
|
#if !MULTICORE_CPU |
447 |
|
// Restore program counters and branch registers |
448 |
|
pc() = saved_pc; |
449 |
|
lr() = saved_lr; |
450 |
|
ctr()= saved_ctr; |
451 |
+ |
gpr(1) = saved_sp; |
452 |
+ |
#endif |
453 |
+ |
|
454 |
+ |
#if EMUL_TIME_STATS |
455 |
+ |
interrupt_time += (clock() - interrupt_start); |
456 |
|
#endif |
457 |
|
} |
458 |
|
|
459 |
|
// Execute 68k routine |
460 |
|
void sheepshaver_cpu::execute_68k(uint32 entry, M68kRegisters *r) |
461 |
|
{ |
462 |
+ |
#if EMUL_TIME_STATS |
463 |
+ |
exec68k_count++; |
464 |
+ |
const clock_t exec68k_start = clock(); |
465 |
+ |
#endif |
466 |
+ |
|
467 |
|
#if SAFE_EXEC_68K |
468 |
|
if (ReadMacInt32(XLM_RUN_MODE) != MODE_EMUL_OP) |
469 |
|
printf("FATAL: Execute68k() not called from EMUL_OP mode\n"); |
473 |
|
uint32 saved_pc = pc(); |
474 |
|
uint32 saved_lr = lr(); |
475 |
|
uint32 saved_ctr= ctr(); |
476 |
+ |
uint32 saved_cr = get_cr(); |
477 |
|
|
478 |
|
// Create MacOS stack frame |
479 |
+ |
// FIXME: make sure MacOS doesn't expect PPC registers to live on top |
480 |
|
uint32 sp = gpr(1); |
481 |
< |
gpr(1) -= 56 + 19*4 + 18*8; |
481 |
> |
gpr(1) -= 56; |
482 |
|
WriteMacInt32(gpr(1), sp); |
483 |
|
|
484 |
|
// Save PowerPC registers |
485 |
< |
memcpy(Mac2HostAddr(gpr(1)+56), &gpr(13), sizeof(uint32)*(32-13)); |
485 |
> |
uint32 saved_GPRs[19]; |
486 |
> |
memcpy(&saved_GPRs[0], &gpr(13), sizeof(uint32)*(32-13)); |
487 |
|
#if SAVE_FP_EXEC_68K |
488 |
< |
memcpy(Mac2HostAddr(gpr(1)+56+19*4), &fpr(14), sizeof(double)*(32-14)); |
488 |
> |
double saved_FPRs[18]; |
489 |
> |
memcpy(&saved_FPRs[0], &fpr(14), sizeof(double)*(32-14)); |
490 |
|
#endif |
491 |
|
|
492 |
|
// Setup registers for 68k emulator |
500 |
|
gpr(25) = ReadMacInt32(XLM_68K_R25); // MSB of SR |
501 |
|
gpr(26) = 0; |
502 |
|
gpr(28) = 0; // VBR |
503 |
< |
gpr(29) = kernel_data->ed.v[0x74 >> 2]; // Pointer to opcode table |
504 |
< |
gpr(30) = kernel_data->ed.v[0x78 >> 2]; // Address of emulator |
503 |
> |
gpr(29) = ntohl(kernel_data->ed.v[0x74 >> 2]); // Pointer to opcode table |
504 |
> |
gpr(30) = ntohl(kernel_data->ed.v[0x78 >> 2]); // Address of emulator |
505 |
|
gpr(31) = KernelDataAddr + 0x1000; |
506 |
|
|
507 |
|
// Push return address (points to EXEC_RETURN opcode) on stack |
533 |
|
r->a[i] = gpr(16 + i); |
534 |
|
|
535 |
|
// Restore PowerPC registers |
536 |
< |
memcpy(&gpr(13), Mac2HostAddr(gpr(1)+56), sizeof(uint32)*(32-13)); |
536 |
> |
memcpy(&gpr(13), &saved_GPRs[0], sizeof(uint32)*(32-13)); |
537 |
|
#if SAVE_FP_EXEC_68K |
538 |
< |
memcpy(&fpr(14), Mac2HostAddr(gpr(1)+56+19*4), sizeof(double)*(32-14)); |
538 |
> |
memcpy(&fpr(14), &saved_FPRs[0], sizeof(double)*(32-14)); |
539 |
|
#endif |
540 |
|
|
541 |
|
// Cleanup stack |
542 |
< |
gpr(1) += 56 + 19*4 + 18*8; |
542 |
> |
gpr(1) += 56; |
543 |
|
|
544 |
|
// Restore program counters and branch registers |
545 |
|
pc() = saved_pc; |
546 |
|
lr() = saved_lr; |
547 |
|
ctr()= saved_ctr; |
548 |
+ |
set_cr(saved_cr); |
549 |
+ |
|
550 |
+ |
#if EMUL_TIME_STATS |
551 |
+ |
exec68k_time += (clock() - exec68k_start); |
552 |
+ |
#endif |
553 |
|
} |
554 |
|
|
555 |
|
// Call MacOS PPC code |
556 |
|
uint32 sheepshaver_cpu::execute_macos_code(uint32 tvect, int nargs, uint32 const *args) |
557 |
|
{ |
558 |
+ |
#if EMUL_TIME_STATS |
559 |
+ |
macos_exec_count++; |
560 |
+ |
const clock_t macos_exec_start = clock(); |
561 |
+ |
#endif |
562 |
+ |
|
563 |
|
// Save program counters and branch registers |
564 |
|
uint32 saved_pc = pc(); |
565 |
|
uint32 saved_lr = lr(); |
566 |
|
uint32 saved_ctr= ctr(); |
567 |
|
|
568 |
|
// Build trampoline with EXEC_RETURN |
569 |
< |
uint32 trampoline[] = { POWERPC_EMUL_OP | 1 }; |
570 |
< |
lr() = (uint32)trampoline; |
569 |
> |
SheepVar32 trampoline = POWERPC_EXEC_RETURN; |
570 |
> |
lr() = trampoline.addr(); |
571 |
|
|
572 |
|
gpr(1) -= 64; // Create stack frame |
573 |
|
uint32 proc = ReadMacInt32(tvect); // Get routine address |
598 |
|
lr() = saved_lr; |
599 |
|
ctr()= saved_ctr; |
600 |
|
|
601 |
+ |
#if EMUL_TIME_STATS |
602 |
+ |
macos_exec_time += (clock() - macos_exec_start); |
603 |
+ |
#endif |
604 |
+ |
|
605 |
|
return retval; |
606 |
|
} |
607 |
|
|
610 |
|
{ |
611 |
|
// Save branch registers |
612 |
|
uint32 saved_lr = lr(); |
464 |
– |
uint32 saved_ctr= ctr(); |
613 |
|
|
614 |
< |
const uint32 trampoline[] = { POWERPC_EMUL_OP | 1 }; |
614 |
> |
SheepVar32 trampoline = POWERPC_EXEC_RETURN; |
615 |
> |
WriteMacInt32(trampoline.addr(), POWERPC_EXEC_RETURN); |
616 |
> |
lr() = trampoline.addr(); |
617 |
|
|
468 |
– |
lr() = (uint32)trampoline; |
469 |
– |
ctr()= entry; |
618 |
|
execute(entry); |
619 |
|
|
620 |
|
// Restore branch registers |
621 |
|
lr() = saved_lr; |
474 |
– |
ctr()= saved_ctr; |
622 |
|
} |
623 |
|
|
624 |
|
// Resource Manager thunk |
478 |
– |
extern "C" void check_load_invoc(uint32 type, int16 id, uint16 **h); |
479 |
– |
|
625 |
|
inline void sheepshaver_cpu::get_resource(uint32 old_get_resource) |
626 |
|
{ |
627 |
|
uint32 type = gpr(3); |
632 |
|
|
633 |
|
// Call old routine |
634 |
|
execute_ppc(old_get_resource); |
490 |
– |
uint16 **handle = (uint16 **)gpr(3); |
635 |
|
|
636 |
|
// Call CheckLoad() |
637 |
+ |
uint32 handle = gpr(3); |
638 |
|
check_load_invoc(type, id, handle); |
639 |
< |
gpr(3) = (uint32)handle; |
639 |
> |
gpr(3) = handle; |
640 |
|
|
641 |
|
// Cleanup stack |
642 |
|
gpr(1) += 56; |
651 |
|
static sheepshaver_cpu *interrupt_cpu = NULL; // CPU emulator to handle interrupts |
652 |
|
static sheepshaver_cpu *current_cpu = NULL; // Current CPU emulator context |
653 |
|
|
654 |
+ |
void FlushCodeCache(uintptr start, uintptr end) |
655 |
+ |
{ |
656 |
+ |
D(bug("FlushCodeCache(%08x, %08x)\n", start, end)); |
657 |
+ |
main_cpu->invalidate_cache_range(start, end); |
658 |
+ |
#if MULTICORE_CPU |
659 |
+ |
interrupt_cpu->invalidate_cache_range(start, end); |
660 |
+ |
#endif |
661 |
+ |
} |
662 |
+ |
|
663 |
|
static inline void cpu_push(sheepshaver_cpu *new_cpu) |
664 |
|
{ |
665 |
|
#if MULTICORE_CPU |
690 |
|
* Initialize CPU emulation |
691 |
|
*/ |
692 |
|
|
693 |
< |
static struct sigaction sigsegv_action; |
540 |
< |
|
541 |
< |
#if defined(__powerpc__) |
542 |
< |
#include <sys/ucontext.h> |
543 |
< |
#endif |
544 |
< |
|
545 |
< |
static void sigsegv_handler(int sig, siginfo_t *sip, void *scp) |
693 |
> |
static sigsegv_return_t sigsegv_handler(sigsegv_address_t fault_address, sigsegv_address_t fault_instruction) |
694 |
|
{ |
547 |
– |
const uintptr addr = (uintptr)sip->si_addr; |
695 |
|
#if ENABLE_VOSF |
696 |
< |
// Handle screen fault. |
697 |
< |
extern bool Screen_fault_handler(sigsegv_address_t fault_address, sigsegv_address_t fault_instruction); |
698 |
< |
if (Screen_fault_handler((sigsegv_address_t)addr, SIGSEGV_INVALID_PC)) |
699 |
< |
return; |
696 |
> |
// Handle screen fault |
697 |
> |
extern bool Screen_fault_handler(sigsegv_address_t, sigsegv_address_t); |
698 |
> |
if (Screen_fault_handler(fault_address, fault_instruction)) |
699 |
> |
return SIGSEGV_RETURN_SUCCESS; |
700 |
|
#endif |
701 |
< |
#if defined(__powerpc__) |
702 |
< |
if (addr >= ROM_BASE && addr < ROM_BASE + ROM_SIZE) { |
703 |
< |
printf("IGNORE write access to ROM at %08x\n", addr); |
704 |
< |
(((ucontext_t *)scp)->uc_mcontext.regs)->nip += 4; |
705 |
< |
return; |
706 |
< |
} |
707 |
< |
if (addr >= 0xf3012000 && addr < 0xf3014000 && 0) { |
708 |
< |
printf("IGNORE write access to ROM at %08x\n", addr); |
709 |
< |
(((ucontext_t *)scp)->uc_mcontext.regs)->nip += 4; |
710 |
< |
return; |
701 |
> |
|
702 |
> |
const uintptr addr = (uintptr)fault_address; |
703 |
> |
#if HAVE_SIGSEGV_SKIP_INSTRUCTION |
704 |
> |
// Ignore writes to ROM |
705 |
> |
if ((addr - ROM_BASE) < ROM_SIZE) |
706 |
> |
return SIGSEGV_RETURN_SKIP_INSTRUCTION; |
707 |
> |
|
708 |
> |
// Get program counter of target CPU |
709 |
> |
sheepshaver_cpu * const cpu = current_cpu; |
710 |
> |
const uint32 pc = cpu->pc(); |
711 |
> |
|
712 |
> |
// Fault in Mac ROM or RAM? |
713 |
> |
bool mac_fault = (pc >= ROM_BASE) && (pc < (ROM_BASE + ROM_AREA_SIZE)) || (pc >= RAMBase) && (pc < (RAMBase + RAMSize)); |
714 |
> |
if (mac_fault) { |
715 |
> |
|
716 |
> |
// "VM settings" during MacOS 8 installation |
717 |
> |
if (pc == ROM_BASE + 0x488160 && cpu->gpr(20) == 0xf8000000) |
718 |
> |
return SIGSEGV_RETURN_SKIP_INSTRUCTION; |
719 |
> |
|
720 |
> |
// MacOS 8.5 installation |
721 |
> |
else if (pc == ROM_BASE + 0x488140 && cpu->gpr(16) == 0xf8000000) |
722 |
> |
return SIGSEGV_RETURN_SKIP_INSTRUCTION; |
723 |
> |
|
724 |
> |
// MacOS 8 serial drivers on startup |
725 |
> |
else if (pc == ROM_BASE + 0x48e080 && (cpu->gpr(8) == 0xf3012002 || cpu->gpr(8) == 0xf3012000)) |
726 |
> |
return SIGSEGV_RETURN_SKIP_INSTRUCTION; |
727 |
> |
|
728 |
> |
// MacOS 8.1 serial drivers on startup |
729 |
> |
else if (pc == ROM_BASE + 0x48c5e0 && (cpu->gpr(20) == 0xf3012002 || cpu->gpr(20) == 0xf3012000)) |
730 |
> |
return SIGSEGV_RETURN_SKIP_INSTRUCTION; |
731 |
> |
else if (pc == ROM_BASE + 0x4a10a0 && (cpu->gpr(20) == 0xf3012002 || cpu->gpr(20) == 0xf3012000)) |
732 |
> |
return SIGSEGV_RETURN_SKIP_INSTRUCTION; |
733 |
> |
|
734 |
> |
// Ignore writes to the zero page |
735 |
> |
else if ((uint32)(addr - SheepMem::ZeroPage()) < (uint32)SheepMem::PageSize()) |
736 |
> |
return SIGSEGV_RETURN_SKIP_INSTRUCTION; |
737 |
> |
|
738 |
> |
// Ignore all other faults, if requested |
739 |
> |
if (PrefsFindBool("ignoresegv")) |
740 |
> |
return SIGSEGV_RETURN_SKIP_INSTRUCTION; |
741 |
|
} |
565 |
– |
#endif |
566 |
– |
printf("Caught SIGSEGV at address %p\n", sip->si_addr); |
567 |
– |
printf("Native PC: %08x\n", (((ucontext_t *)scp)->uc_mcontext.regs)->nip); |
568 |
– |
printf("Current CPU: %s\n", current_cpu == main_cpu ? "main" : "interrupts"); |
569 |
– |
#if 1 |
570 |
– |
dump_registers(); |
742 |
|
#else |
743 |
< |
printf("Main CPU context\n"); |
573 |
< |
main_cpu->dump_registers(); |
574 |
< |
printf("Interrupts CPU context\n"); |
575 |
< |
interrupt_cpu->dump_registers(); |
743 |
> |
#error "FIXME: You don't have the capability to skip instruction within signal handlers" |
744 |
|
#endif |
745 |
+ |
|
746 |
+ |
printf("SIGSEGV\n"); |
747 |
+ |
printf(" pc %p\n", fault_instruction); |
748 |
+ |
printf(" ea %p\n", fault_address); |
749 |
+ |
printf(" cpu %s\n", current_cpu == main_cpu ? "main" : "interrupts"); |
750 |
+ |
dump_registers(); |
751 |
|
current_cpu->dump_log(); |
752 |
|
enter_mon(); |
753 |
|
QuitEmulator(); |
754 |
+ |
|
755 |
+ |
return SIGSEGV_RETURN_FAILURE; |
756 |
|
} |
757 |
|
|
758 |
|
void init_emul_ppc(void) |
760 |
|
// Initialize main CPU emulator |
761 |
|
main_cpu = new sheepshaver_cpu(); |
762 |
|
main_cpu->set_register(powerpc_registers::GPR(3), any_register((uint32)ROM_BASE + 0x30d000)); |
763 |
+ |
main_cpu->set_register(powerpc_registers::GPR(4), any_register(KernelDataAddr + 0x1000)); |
764 |
|
WriteMacInt32(XLM_RUN_MODE, MODE_68K); |
765 |
|
|
766 |
|
#if MULTICORE_CPU |
768 |
|
interrupt_cpu = new sheepshaver_cpu(); |
769 |
|
#endif |
770 |
|
|
771 |
< |
// Install SIGSEGV handler |
772 |
< |
sigemptyset(&sigsegv_action.sa_mask); |
596 |
< |
sigsegv_action.sa_sigaction = sigsegv_handler; |
597 |
< |
sigsegv_action.sa_flags = SA_SIGINFO; |
598 |
< |
sigsegv_action.sa_restorer = NULL; |
599 |
< |
sigaction(SIGSEGV, &sigsegv_action, NULL); |
771 |
> |
// Install the handler for SIGSEGV |
772 |
> |
sigsegv_install_handler(sigsegv_handler); |
773 |
|
|
774 |
|
#if ENABLE_MON |
775 |
|
// Install "regs" command in cxmon |
776 |
|
mon_add_command("regs", dump_registers, "regs Dump PowerPC registers\n"); |
777 |
|
mon_add_command("log", dump_log, "log Dump PowerPC emulation log\n"); |
778 |
|
#endif |
779 |
+ |
|
780 |
+ |
#if EMUL_TIME_STATS |
781 |
+ |
emul_start_time = clock(); |
782 |
+ |
#endif |
783 |
+ |
} |
784 |
+ |
|
785 |
+ |
/* |
786 |
+ |
* Deinitialize emulation |
787 |
+ |
*/ |
788 |
+ |
|
789 |
+ |
void exit_emul_ppc(void) |
790 |
+ |
{ |
791 |
+ |
#if EMUL_TIME_STATS |
792 |
+ |
clock_t emul_end_time = clock(); |
793 |
+ |
|
794 |
+ |
printf("### Statistics for SheepShaver emulation parts\n"); |
795 |
+ |
const clock_t emul_time = emul_end_time - emul_start_time; |
796 |
+ |
printf("Total emulation time : %.1f sec\n", double(emul_time) / double(CLOCKS_PER_SEC)); |
797 |
+ |
printf("Total interrupt count: %d (%2.1f Hz)\n", interrupt_count, |
798 |
+ |
(double(interrupt_count) * CLOCKS_PER_SEC) / double(emul_time)); |
799 |
+ |
|
800 |
+ |
#define PRINT_STATS(LABEL, VAR_PREFIX) do { \ |
801 |
+ |
printf("Total " LABEL " count : %d\n", VAR_PREFIX##_count); \ |
802 |
+ |
printf("Total " LABEL " time : %.1f sec (%.1f%%)\n", \ |
803 |
+ |
double(VAR_PREFIX##_time) / double(CLOCKS_PER_SEC), \ |
804 |
+ |
100.0 * double(VAR_PREFIX##_time) / double(emul_time)); \ |
805 |
+ |
} while (0) |
806 |
+ |
|
807 |
+ |
PRINT_STATS("Execute68k[Trap] execution", exec68k); |
808 |
+ |
PRINT_STATS("NativeOp execution", native_exec); |
809 |
+ |
PRINT_STATS("MacOS routine execution", macos_exec); |
810 |
+ |
|
811 |
+ |
#undef PRINT_STATS |
812 |
+ |
printf("\n"); |
813 |
+ |
#endif |
814 |
+ |
|
815 |
+ |
delete main_cpu; |
816 |
+ |
#if MULTICORE_CPU |
817 |
+ |
delete interrupt_cpu; |
818 |
+ |
#endif |
819 |
|
} |
820 |
|
|
821 |
|
/* |
825 |
|
void emul_ppc(uint32 entry) |
826 |
|
{ |
827 |
|
current_cpu = main_cpu; |
828 |
+ |
#if 0 |
829 |
|
current_cpu->start_log(); |
830 |
+ |
#endif |
831 |
+ |
// start emulation loop and enable code translation or caching |
832 |
|
current_cpu->execute(entry); |
833 |
|
} |
834 |
|
|
836 |
|
* Handle PowerPC interrupt |
837 |
|
*/ |
838 |
|
|
839 |
< |
// Atomic operations |
840 |
< |
extern int atomic_add(int *var, int v); |
841 |
< |
extern int atomic_and(int *var, int v); |
842 |
< |
extern int atomic_or(int *var, int v); |
843 |
< |
|
839 |
> |
#if ASYNC_IRQ |
840 |
> |
void HandleInterrupt(void) |
841 |
> |
{ |
842 |
> |
main_cpu->handle_interrupt(); |
843 |
> |
} |
844 |
> |
#else |
845 |
|
void TriggerInterrupt(void) |
846 |
|
{ |
847 |
|
#if 0 |
848 |
|
WriteMacInt32(0x16a, ReadMacInt32(0x16a) + 1); |
849 |
|
#else |
850 |
< |
SPCFLAGS_SET( SPCFLAG_INT ); |
850 |
> |
// Trigger interrupt to main cpu only |
851 |
> |
if (main_cpu) |
852 |
> |
main_cpu->trigger_interrupt(); |
853 |
|
#endif |
854 |
|
} |
855 |
+ |
#endif |
856 |
|
|
857 |
< |
static void HandleInterrupt(void) |
857 |
> |
void sheepshaver_cpu::handle_interrupt(void) |
858 |
|
{ |
859 |
|
// Do nothing if interrupts are disabled |
860 |
< |
if (int32(ReadMacInt32(XLM_IRQ_NEST)) > 0) |
860 |
> |
if (*(int32 *)XLM_IRQ_NEST > 0) |
861 |
|
return; |
862 |
|
|
863 |
|
// Do nothing if there is no interrupt pending |
873 |
|
// 68k emulator active, trigger 68k interrupt level 1 |
874 |
|
assert(current_cpu == main_cpu); |
875 |
|
WriteMacInt16(tswap32(kernel_data->v[0x67c >> 2]), 1); |
876 |
< |
main_cpu->set_cr(main_cpu->get_cr() | tswap32(kernel_data->v[0x674 >> 2])); |
876 |
> |
set_cr(get_cr() | tswap32(kernel_data->v[0x674 >> 2])); |
877 |
|
break; |
878 |
|
|
879 |
|
#if INTERRUPTS_IN_NATIVE_MODE |
880 |
|
case MODE_NATIVE: |
881 |
|
// 68k emulator inactive, in nanokernel? |
882 |
|
assert(current_cpu == main_cpu); |
883 |
< |
if (main_cpu->gpr(1) != KernelDataAddr) { |
883 |
> |
if (gpr(1) != KernelDataAddr) { |
884 |
|
// Prepare for 68k interrupt level 1 |
885 |
|
WriteMacInt16(tswap32(kernel_data->v[0x67c >> 2]), 1); |
886 |
|
WriteMacInt32(tswap32(kernel_data->v[0x658 >> 2]) + 0xdc, |
891 |
|
DisableInterrupt(); |
892 |
|
cpu_push(interrupt_cpu); |
893 |
|
if (ROMType == ROMTYPE_NEWWORLD) |
894 |
< |
current_cpu->interrupt(ROM_BASE + 0x312b1c, main_cpu); |
894 |
> |
current_cpu->interrupt(ROM_BASE + 0x312b1c); |
895 |
|
else |
896 |
< |
current_cpu->interrupt(ROM_BASE + 0x312a3c, main_cpu); |
896 |
> |
current_cpu->interrupt(ROM_BASE + 0x312a3c); |
897 |
|
cpu_pop(); |
898 |
|
} |
899 |
|
break; |
924 |
|
if (InterruptFlags & INTFLAG_VIA) { |
925 |
|
ClearInterruptFlag(INTFLAG_VIA); |
926 |
|
ADBInterrupt(); |
927 |
< |
ExecutePPC(VideoVBL); |
927 |
> |
ExecuteNative(NATIVE_VIDEO_VBL); |
928 |
|
} |
929 |
|
} |
930 |
|
#endif |
934 |
|
} |
935 |
|
} |
936 |
|
|
717 |
– |
/* |
718 |
– |
* Execute NATIVE_OP opcode (called by PowerPC emulator) |
719 |
– |
*/ |
720 |
– |
|
721 |
– |
#define POWERPC_NATIVE_OP_INIT(LR, OP) \ |
722 |
– |
tswap32(POWERPC_EMUL_OP | ((LR) << 11) | (((uint32)OP) << 6) | 2) |
723 |
– |
|
724 |
– |
// FIXME: Make sure 32-bit relocations are used |
725 |
– |
const uint32 NativeOpTable[NATIVE_OP_MAX] = { |
726 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_PATCH_NAME_REGISTRY), |
727 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_VIDEO_INSTALL_ACCEL), |
728 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_VIDEO_VBL), |
729 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_VIDEO_DO_DRIVER_IO), |
730 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_ETHER_IRQ), |
731 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_ETHER_INIT), |
732 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_ETHER_TERM), |
733 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_ETHER_OPEN), |
734 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_ETHER_CLOSE), |
735 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_ETHER_WPUT), |
736 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_ETHER_RSRV), |
737 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_SERIAL_NOTHING), |
738 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_SERIAL_OPEN), |
739 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_SERIAL_PRIME_IN), |
740 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_SERIAL_PRIME_OUT), |
741 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_SERIAL_CONTROL), |
742 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_SERIAL_STATUS), |
743 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_SERIAL_CLOSE), |
744 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_GET_RESOURCE), |
745 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_GET_1_RESOURCE), |
746 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_GET_IND_RESOURCE), |
747 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_GET_1_IND_RESOURCE), |
748 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_R_GET_RESOURCE), |
749 |
– |
POWERPC_NATIVE_OP_INIT(0, NATIVE_DISABLE_INTERRUPT), |
750 |
– |
POWERPC_NATIVE_OP_INIT(0, NATIVE_ENABLE_INTERRUPT), |
751 |
– |
}; |
752 |
– |
|
937 |
|
static void get_resource(void); |
938 |
|
static void get_1_resource(void); |
939 |
|
static void get_ind_resource(void); |
944 |
|
|
945 |
|
static void NativeOp(int selector) |
946 |
|
{ |
947 |
+ |
#if EMUL_TIME_STATS |
948 |
+ |
native_exec_count++; |
949 |
+ |
const clock_t native_exec_start = clock(); |
950 |
+ |
#endif |
951 |
+ |
|
952 |
|
switch (selector) { |
953 |
|
case NATIVE_PATCH_NAME_REGISTRY: |
954 |
|
DoPatchNameRegistry(); |
963 |
|
GPR(3) = (int32)(int16)VideoDoDriverIO((void *)GPR(3), (void *)GPR(4), |
964 |
|
(void *)GPR(5), GPR(6), GPR(7)); |
965 |
|
break; |
966 |
< |
case NATIVE_GET_RESOURCE: |
967 |
< |
get_resource(); |
966 |
> |
#ifdef WORDS_BIGENDIAN |
967 |
> |
case NATIVE_ETHER_IRQ: |
968 |
> |
EtherIRQ(); |
969 |
|
break; |
970 |
< |
case NATIVE_GET_1_RESOURCE: |
971 |
< |
get_1_resource(); |
970 |
> |
case NATIVE_ETHER_INIT: |
971 |
> |
GPR(3) = InitStreamModule((void *)GPR(3)); |
972 |
|
break; |
973 |
< |
case NATIVE_GET_IND_RESOURCE: |
974 |
< |
get_ind_resource(); |
973 |
> |
case NATIVE_ETHER_TERM: |
974 |
> |
TerminateStreamModule(); |
975 |
|
break; |
976 |
< |
case NATIVE_GET_1_IND_RESOURCE: |
977 |
< |
get_1_ind_resource(); |
976 |
> |
case NATIVE_ETHER_OPEN: |
977 |
> |
GPR(3) = ether_open((queue_t *)GPR(3), (void *)GPR(4), GPR(5), GPR(6), (void*)GPR(7)); |
978 |
|
break; |
979 |
< |
case NATIVE_R_GET_RESOURCE: |
980 |
< |
r_get_resource(); |
979 |
> |
case NATIVE_ETHER_CLOSE: |
980 |
> |
GPR(3) = ether_close((queue_t *)GPR(3), GPR(4), (void *)GPR(5)); |
981 |
|
break; |
982 |
+ |
case NATIVE_ETHER_WPUT: |
983 |
+ |
GPR(3) = ether_wput((queue_t *)GPR(3), (mblk_t *)GPR(4)); |
984 |
+ |
break; |
985 |
+ |
case NATIVE_ETHER_RSRV: |
986 |
+ |
GPR(3) = ether_rsrv((queue_t *)GPR(3)); |
987 |
+ |
break; |
988 |
+ |
#else |
989 |
+ |
case NATIVE_ETHER_INIT: |
990 |
+ |
// FIXME: needs more complicated thunks |
991 |
+ |
GPR(3) = false; |
992 |
+ |
break; |
993 |
+ |
#endif |
994 |
|
case NATIVE_SERIAL_NOTHING: |
995 |
|
case NATIVE_SERIAL_OPEN: |
996 |
|
case NATIVE_SERIAL_PRIME_IN: |
1011 |
|
GPR(3) = serial_callbacks[selector - NATIVE_SERIAL_NOTHING](GPR(3), GPR(4)); |
1012 |
|
break; |
1013 |
|
} |
1014 |
+ |
case NATIVE_GET_RESOURCE: |
1015 |
+ |
case NATIVE_GET_1_RESOURCE: |
1016 |
+ |
case NATIVE_GET_IND_RESOURCE: |
1017 |
+ |
case NATIVE_GET_1_IND_RESOURCE: |
1018 |
+ |
case NATIVE_R_GET_RESOURCE: { |
1019 |
+ |
typedef void (*GetResourceCallback)(void); |
1020 |
+ |
static const GetResourceCallback get_resource_callbacks[] = { |
1021 |
+ |
get_resource, |
1022 |
+ |
get_1_resource, |
1023 |
+ |
get_ind_resource, |
1024 |
+ |
get_1_ind_resource, |
1025 |
+ |
r_get_resource |
1026 |
+ |
}; |
1027 |
+ |
get_resource_callbacks[selector - NATIVE_GET_RESOURCE](); |
1028 |
+ |
break; |
1029 |
+ |
} |
1030 |
|
case NATIVE_DISABLE_INTERRUPT: |
1031 |
|
DisableInterrupt(); |
1032 |
|
break; |
1033 |
|
case NATIVE_ENABLE_INTERRUPT: |
1034 |
|
EnableInterrupt(); |
1035 |
|
break; |
1036 |
+ |
case NATIVE_MAKE_EXECUTABLE: |
1037 |
+ |
MakeExecutable(0, (void *)GPR(4), GPR(5)); |
1038 |
+ |
break; |
1039 |
+ |
case NATIVE_CHECK_LOAD_INVOC: |
1040 |
+ |
check_load_invoc(GPR(3), GPR(4), GPR(5)); |
1041 |
+ |
break; |
1042 |
|
default: |
1043 |
|
printf("FATAL: NATIVE_OP called with bogus selector %d\n", selector); |
1044 |
|
QuitEmulator(); |
1045 |
|
break; |
1046 |
|
} |
823 |
– |
} |
1047 |
|
|
1048 |
< |
/* |
1049 |
< |
* Execute native subroutine (LR must contain return address) |
1050 |
< |
*/ |
828 |
< |
|
829 |
< |
void ExecuteNative(int selector) |
830 |
< |
{ |
831 |
< |
uint32 tvect[2]; |
832 |
< |
tvect[0] = tswap32(POWERPC_NATIVE_OP_FUNC(selector)); |
833 |
< |
tvect[1] = 0; // Fake TVECT |
834 |
< |
RoutineDescriptor desc = BUILD_PPC_ROUTINE_DESCRIPTOR(0, tvect); |
835 |
< |
M68kRegisters r; |
836 |
< |
Execute68k((uint32)&desc, &r); |
1048 |
> |
#if EMUL_TIME_STATS |
1049 |
> |
native_exec_time += (clock() - native_exec_start); |
1050 |
> |
#endif |
1051 |
|
} |
1052 |
|
|
1053 |
|
/* |
1068 |
|
|
1069 |
|
void Execute68kTrap(uint16 trap, M68kRegisters *r) |
1070 |
|
{ |
1071 |
< |
uint16 proc[2] = {trap, M68K_RTS}; |
1072 |
< |
Execute68k((uint32)proc, r); |
1071 |
> |
SheepVar proc_var(4); |
1072 |
> |
uint32 proc = proc_var.addr(); |
1073 |
> |
WriteMacInt16(proc, trap); |
1074 |
> |
WriteMacInt16(proc + 2, M68K_RTS); |
1075 |
> |
Execute68k(proc, r); |
1076 |
|
} |
1077 |
|
|
1078 |
|
/* |
1127 |
|
} |
1128 |
|
|
1129 |
|
/* |
913 |
– |
* Atomic operations |
914 |
– |
*/ |
915 |
– |
|
916 |
– |
int atomic_add(int *var, int v) |
917 |
– |
{ |
918 |
– |
int ret = *var; |
919 |
– |
*var += v; |
920 |
– |
return ret; |
921 |
– |
} |
922 |
– |
|
923 |
– |
int atomic_and(int *var, int v) |
924 |
– |
{ |
925 |
– |
int ret = *var; |
926 |
– |
*var &= v; |
927 |
– |
return ret; |
928 |
– |
} |
929 |
– |
|
930 |
– |
int atomic_or(int *var, int v) |
931 |
– |
{ |
932 |
– |
int ret = *var; |
933 |
– |
*var |= v; |
934 |
– |
return ret; |
935 |
– |
} |
936 |
– |
|
937 |
– |
/* |
1130 |
|
* Resource Manager thunks |
1131 |
|
*/ |
1132 |
|
|