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/* |
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* sheepshaver_glue.cpp - Glue Kheperix CPU to SheepShaver CPU engine interface |
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* |
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* SheepShaver (C) 1997-2002 Christian Bauer and Marc Hellwig |
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* SheepShaver (C) 1997-2004 Christian Bauer and Marc Hellwig |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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#include "sysdeps.h" |
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#include "cpu_emulation.h" |
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#include "main.h" |
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#include "prefs.h" |
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#include "xlowmem.h" |
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#include "emul_op.h" |
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#include "rom_patches.h" |
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#include "macos_util.h" |
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#include "block-alloc.hpp" |
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#include "sigsegv.h" |
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#include "spcflags.h" |
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#include "cpu/ppc/ppc-cpu.hpp" |
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#include "cpu/ppc/ppc-operations.hpp" |
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#include "cpu/ppc/ppc-instructions.hpp" |
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#include "thunks.h" |
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|
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// Used for NativeOp trampolines |
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#include "video.h" |
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#include "name_registry.h" |
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#include "serial.h" |
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#include "ether.h" |
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|
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#include <stdio.h> |
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|
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#include "mon_disass.h" |
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#endif |
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|
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#define DEBUG 1 |
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#define DEBUG 0 |
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#include "debug.h" |
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|
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// Emulation time statistics |
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#define EMUL_TIME_STATS 1 |
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|
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#if EMUL_TIME_STATS |
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static clock_t emul_start_time; |
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static uint32 interrupt_count = 0; |
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static clock_t interrupt_time = 0; |
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static uint32 exec68k_count = 0; |
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static clock_t exec68k_time = 0; |
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static uint32 native_exec_count = 0; |
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static clock_t native_exec_time = 0; |
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static uint32 macos_exec_count = 0; |
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static clock_t macos_exec_time = 0; |
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#endif |
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|
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static void enter_mon(void) |
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{ |
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// Start up mon in real-mode |
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#endif |
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} |
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|
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// From main_*.cpp |
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extern uintptr SignalStackBase(); |
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|
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// From rsrc_patches.cpp |
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extern "C" void check_load_invoc(uint32 type, int16 id, uint32 h); |
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|
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// PowerPC EmulOp to exit from emulation looop |
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const uint32 POWERPC_EXEC_RETURN = POWERPC_EMUL_OP | 1; |
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|
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// Enable multicore (main/interrupts) cpu emulation? |
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#define MULTICORE_CPU 0 |
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#define MULTICORE_CPU (ASYNC_IRQ ? 1 : 0) |
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|
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// Enable Execute68k() safety checks? |
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#define SAFE_EXEC_68K 1 |
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// Interrupts in native mode? |
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#define INTERRUPTS_IN_NATIVE_MODE 1 |
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|
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// 68k Emulator Data |
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struct EmulatorData { |
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uint32 v[0x400]; |
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}; |
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// Pointer to Kernel Data |
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static KernelData * const kernel_data = (KernelData *)KERNEL_DATA_BASE; |
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|
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// Kernel Data |
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struct KernelData { |
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uint32 v[0x400]; |
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EmulatorData ed; |
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}; |
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// SIGSEGV handler |
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static sigsegv_return_t sigsegv_handler(sigsegv_address_t, sigsegv_address_t); |
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|
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// Pointer to Kernel Data |
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static KernelData * const kernel_data = (KernelData *)0x68ffe000; |
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// JIT Compiler enabled? |
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static inline bool enable_jit_p() |
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{ |
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return PrefsFindBool("jit"); |
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} |
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/** |
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* PowerPC emulator glue with special 'sheep' opcodes |
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**/ |
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|
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struct sheepshaver_exec_return { }; |
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enum { |
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PPC_I(SHEEP) = PPC_I(MAX), |
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PPC_I(SHEEP_MAX) |
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}; |
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|
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class sheepshaver_cpu |
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: public powerpc_cpu |
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public: |
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|
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sheepshaver_cpu() |
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: powerpc_cpu() |
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{ init_decoder(); } |
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// Constructor |
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sheepshaver_cpu(); |
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|
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// Condition Register accessors |
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// CR & XER accessors |
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uint32 get_cr() const { return cr().get(); } |
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void set_cr(uint32 v) { cr().set(v); } |
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uint32 get_xer() const { return xer().get(); } |
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void set_xer(uint32 v) { xer().set(v); } |
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|
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// Execution loop |
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void execute(uint32 pc); |
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// Execute EMUL_OP routine |
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void execute_emul_op(uint32 emul_op); |
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|
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// Execute 68k routine |
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void execute_68k(uint32 entry, M68kRegisters *r); |
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// Execute MacOS/PPC code |
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uint32 execute_macos_code(uint32 tvect, int nargs, uint32 const *args); |
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|
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// Compile one instruction |
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virtual bool compile1(codegen_context_t & cg_context); |
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|
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// Resource manager thunk |
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void get_resource(uint32 old_get_resource); |
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|
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// Handle MacOS interrupt |
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void interrupt(uint32 entry, sheepshaver_cpu *cpu); |
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|
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// spcflags for interrupts handling |
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static uint32 spcflags; |
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void interrupt(uint32 entry); |
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void handle_interrupt(); |
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|
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// Lazy memory allocator (one item at a time) |
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void *operator new(size_t size) |
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// FIXME: really make surre array allocation fail at link time? |
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void *operator new[](size_t); |
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void operator delete[](void *p); |
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|
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// Make sure the SIGSEGV handler can access CPU registers |
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friend sigsegv_return_t sigsegv_handler(sigsegv_address_t, sigsegv_address_t); |
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}; |
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|
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uint32 sheepshaver_cpu::spcflags = 0; |
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lazy_allocator< sheepshaver_cpu > allocator_helper< sheepshaver_cpu, lazy_allocator >::allocator; |
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// FIXME: this specialization doesn't work with GCC |
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// template<> lazy_allocator< sheepshaver_cpu > allocator_helper< sheepshaver_cpu, lazy_allocator >::allocator; |
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template< class data_type, template< class > class allocator_type > |
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allocator_type< data_type > allocator_helper< data_type, allocator_type >::allocator; |
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|
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< |
void sheepshaver_cpu::init_decoder() |
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sheepshaver_cpu::sheepshaver_cpu() |
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> |
: powerpc_cpu(enable_jit_p()) |
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{ |
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< |
#ifndef PPC_NO_STATIC_II_INDEX_TABLE |
183 |
< |
static bool initialized = false; |
148 |
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if (initialized) |
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return; |
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initialized = true; |
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#endif |
182 |
> |
init_decoder(); |
183 |
> |
} |
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|
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void sheepshaver_cpu::init_decoder() |
186 |
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{ |
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static const instr_info_t sheep_ii_table[] = { |
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{ "sheep", |
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(execute_fn)&sheepshaver_cpu::execute_sheep, |
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(execute_pmf)&sheepshaver_cpu::execute_sheep, |
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NULL, |
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D_form, 6, 0, CFLOW_TRAP |
191 |
> |
PPC_I(SHEEP), |
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D_form, 6, 0, CFLOW_JUMP | CFLOW_TRAP |
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} |
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}; |
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|
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typedef bit_field< 21, 25 > NATIVE_OP_field; |
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typedef bit_field< 26, 31 > EMUL_OP_field; |
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|
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// Execute EMUL_OP routine |
220 |
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void sheepshaver_cpu::execute_emul_op(uint32 emul_op) |
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{ |
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M68kRegisters r68; |
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WriteMacInt32(XLM_68K_R25, gpr(25)); |
224 |
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WriteMacInt32(XLM_RUN_MODE, MODE_EMUL_OP); |
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for (int i = 0; i < 8; i++) |
226 |
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r68.d[i] = gpr(8 + i); |
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for (int i = 0; i < 7; i++) |
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r68.a[i] = gpr(16 + i); |
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r68.a[7] = gpr(1); |
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uint32 saved_cr = get_cr() & CR_field<2>::mask(); |
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uint32 saved_xer = get_xer(); |
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EmulOp(&r68, gpr(24), emul_op); |
233 |
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set_cr(saved_cr); |
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set_xer(saved_xer); |
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for (int i = 0; i < 8; i++) |
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gpr(8 + i) = r68.d[i]; |
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for (int i = 0; i < 7; i++) |
238 |
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gpr(16 + i) = r68.a[i]; |
239 |
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gpr(1) = r68.a[7]; |
240 |
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WriteMacInt32(XLM_RUN_MODE, MODE_68K); |
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} |
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|
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// Execute SheepShaver instruction |
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void sheepshaver_cpu::execute_sheep(uint32 opcode) |
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{ |
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case 0: // EMUL_RETURN |
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QuitEmulator(); |
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break; |
253 |
< |
|
253 |
> |
|
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case 1: // EXEC_RETURN |
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< |
throw sheepshaver_exec_return(); |
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> |
spcflags().set(SPCFLAG_CPU_EXEC_RETURN); |
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break; |
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|
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case 2: // EXEC_NATIVE |
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pc() += 4; |
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break; |
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|
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< |
default: { // EMUL_OP |
267 |
< |
M68kRegisters r68; |
209 |
< |
WriteMacInt32(XLM_68K_R25, gpr(25)); |
210 |
< |
WriteMacInt32(XLM_RUN_MODE, MODE_EMUL_OP); |
211 |
< |
for (int i = 0; i < 8; i++) |
212 |
< |
r68.d[i] = gpr(8 + i); |
213 |
< |
for (int i = 0; i < 7; i++) |
214 |
< |
r68.a[i] = gpr(16 + i); |
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< |
r68.a[7] = gpr(1); |
216 |
< |
EmulOp(&r68, gpr(24), EMUL_OP_field::extract(opcode) - 3); |
217 |
< |
for (int i = 0; i < 8; i++) |
218 |
< |
gpr(8 + i) = r68.d[i]; |
219 |
< |
for (int i = 0; i < 7; i++) |
220 |
< |
gpr(16 + i) = r68.a[i]; |
221 |
< |
gpr(1) = r68.a[7]; |
222 |
< |
WriteMacInt32(XLM_RUN_MODE, MODE_68K); |
266 |
> |
default: // EMUL_OP |
267 |
> |
execute_emul_op(EMUL_OP_field::extract(opcode) - 3); |
268 |
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pc() += 4; |
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break; |
270 |
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} |
226 |
– |
} |
271 |
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} |
272 |
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|
273 |
< |
// Checks for pending interrupts |
274 |
< |
struct execute_nothing { |
275 |
< |
static inline void execute(powerpc_cpu *) { } |
276 |
< |
}; |
273 |
> |
// Compile one instruction |
274 |
> |
bool sheepshaver_cpu::compile1(codegen_context_t & cg_context) |
275 |
> |
{ |
276 |
> |
#if PPC_ENABLE_JIT |
277 |
> |
const instr_info_t *ii = cg_context.instr_info; |
278 |
> |
if (ii->mnemo != PPC_I(SHEEP)) |
279 |
> |
return false; |
280 |
> |
|
281 |
> |
bool compiled = false; |
282 |
> |
powerpc_dyngen & dg = cg_context.codegen; |
283 |
> |
uint32 opcode = cg_context.opcode; |
284 |
|
|
285 |
< |
static void HandleInterrupt(void); |
285 |
> |
switch (opcode & 0x3f) { |
286 |
> |
case 0: // EMUL_RETURN |
287 |
> |
dg.gen_invoke(QuitEmulator); |
288 |
> |
compiled = true; |
289 |
> |
break; |
290 |
|
|
291 |
< |
struct execute_spcflags_check { |
292 |
< |
static inline void execute(powerpc_cpu *cpu) { |
293 |
< |
if (SPCFLAGS_TEST(SPCFLAG_ALL_BUT_EXEC_RETURN)) { |
294 |
< |
if (SPCFLAGS_TEST( SPCFLAG_ENTER_MON )) { |
295 |
< |
SPCFLAGS_CLEAR( SPCFLAG_ENTER_MON ); |
296 |
< |
enter_mon(); |
297 |
< |
} |
298 |
< |
if (SPCFLAGS_TEST( SPCFLAG_DOINT )) { |
299 |
< |
SPCFLAGS_CLEAR( SPCFLAG_DOINT ); |
300 |
< |
HandleInterrupt(); |
301 |
< |
} |
302 |
< |
if (SPCFLAGS_TEST( SPCFLAG_INT )) { |
303 |
< |
SPCFLAGS_CLEAR( SPCFLAG_INT ); |
304 |
< |
SPCFLAGS_SET( SPCFLAG_DOINT ); |
291 |
> |
case 1: // EXEC_RETURN |
292 |
> |
dg.gen_spcflags_set(SPCFLAG_CPU_EXEC_RETURN); |
293 |
> |
compiled = true; |
294 |
> |
break; |
295 |
> |
|
296 |
> |
case 2: { // EXEC_NATIVE |
297 |
> |
uint32 selector = NATIVE_OP_field::extract(opcode); |
298 |
> |
switch (selector) { |
299 |
> |
case NATIVE_PATCH_NAME_REGISTRY: |
300 |
> |
dg.gen_invoke(DoPatchNameRegistry); |
301 |
> |
compiled = true; |
302 |
> |
break; |
303 |
> |
case NATIVE_VIDEO_INSTALL_ACCEL: |
304 |
> |
dg.gen_invoke(VideoInstallAccel); |
305 |
> |
compiled = true; |
306 |
> |
break; |
307 |
> |
case NATIVE_VIDEO_VBL: |
308 |
> |
dg.gen_invoke(VideoVBL); |
309 |
> |
compiled = true; |
310 |
> |
break; |
311 |
> |
case NATIVE_GET_RESOURCE: |
312 |
> |
case NATIVE_GET_1_RESOURCE: |
313 |
> |
case NATIVE_GET_IND_RESOURCE: |
314 |
> |
case NATIVE_GET_1_IND_RESOURCE: |
315 |
> |
case NATIVE_R_GET_RESOURCE: { |
316 |
> |
static const uint32 get_resource_ptr[] = { |
317 |
> |
XLM_GET_RESOURCE, |
318 |
> |
XLM_GET_1_RESOURCE, |
319 |
> |
XLM_GET_IND_RESOURCE, |
320 |
> |
XLM_GET_1_IND_RESOURCE, |
321 |
> |
XLM_R_GET_RESOURCE |
322 |
> |
}; |
323 |
> |
uint32 old_get_resource = ReadMacInt32(get_resource_ptr[selector - NATIVE_GET_RESOURCE]); |
324 |
> |
typedef void (*func_t)(dyngen_cpu_base, uint32); |
325 |
> |
func_t func = (func_t)nv_mem_fun(&sheepshaver_cpu::get_resource).ptr(); |
326 |
> |
dg.gen_invoke_CPU_im(func, old_get_resource); |
327 |
> |
compiled = true; |
328 |
> |
break; |
329 |
> |
} |
330 |
> |
case NATIVE_DISABLE_INTERRUPT: |
331 |
> |
dg.gen_invoke(DisableInterrupt); |
332 |
> |
compiled = true; |
333 |
> |
break; |
334 |
> |
case NATIVE_ENABLE_INTERRUPT: |
335 |
> |
dg.gen_invoke(EnableInterrupt); |
336 |
> |
compiled = true; |
337 |
> |
break; |
338 |
> |
case NATIVE_CHECK_LOAD_INVOC: |
339 |
> |
dg.gen_load_T0_GPR(3); |
340 |
> |
dg.gen_load_T1_GPR(4); |
341 |
> |
dg.gen_se_16_32_T1(); |
342 |
> |
dg.gen_load_T2_GPR(5); |
343 |
> |
dg.gen_invoke_T0_T1_T2((void (*)(uint32, uint32, uint32))check_load_invoc); |
344 |
> |
compiled = true; |
345 |
> |
break; |
346 |
> |
} |
347 |
> |
if (FN_field::test(opcode)) { |
348 |
> |
if (compiled) { |
349 |
> |
dg.gen_load_A0_LR(); |
350 |
> |
dg.gen_set_PC_A0(); |
351 |
|
} |
352 |
+ |
cg_context.done_compile = true; |
353 |
|
} |
354 |
+ |
else |
355 |
+ |
cg_context.done_compile = false; |
356 |
+ |
break; |
357 |
|
} |
253 |
– |
}; |
358 |
|
|
359 |
< |
// Execution loop |
360 |
< |
void sheepshaver_cpu::execute(uint32 entry) |
361 |
< |
{ |
362 |
< |
try { |
363 |
< |
pc() = entry; |
364 |
< |
powerpc_cpu::do_execute<execute_nothing, execute_spcflags_check>(); |
359 |
> |
default: { // EMUL_OP |
360 |
> |
typedef void (*func_t)(dyngen_cpu_base, uint32); |
361 |
> |
func_t func = (func_t)nv_mem_fun(&sheepshaver_cpu::execute_emul_op).ptr(); |
362 |
> |
dg.gen_invoke_CPU_im(func, EMUL_OP_field::extract(opcode) - 3); |
363 |
> |
cg_context.done_compile = false; |
364 |
> |
compiled = true; |
365 |
> |
break; |
366 |
|
} |
262 |
– |
catch (sheepshaver_exec_return const &) { |
263 |
– |
// Nothing, simply return |
264 |
– |
} |
265 |
– |
catch (...) { |
266 |
– |
printf("ERROR: execute() received an unknown exception!\n"); |
267 |
– |
QuitEmulator(); |
367 |
|
} |
368 |
+ |
return compiled; |
369 |
+ |
#endif |
370 |
+ |
return false; |
371 |
|
} |
372 |
|
|
373 |
|
// Handle MacOS interrupt |
374 |
< |
void sheepshaver_cpu::interrupt(uint32 entry, sheepshaver_cpu *cpu) |
374 |
> |
void sheepshaver_cpu::interrupt(uint32 entry) |
375 |
|
{ |
376 |
< |
#if MULTICORE_CPU |
377 |
< |
// Initialize stack pointer from previous CPU running |
378 |
< |
gpr(1) = cpu->gpr(1); |
379 |
< |
#else |
376 |
> |
#if EMUL_TIME_STATS |
377 |
> |
interrupt_count++; |
378 |
> |
const clock_t interrupt_start = clock(); |
379 |
> |
#endif |
380 |
> |
|
381 |
> |
#if !MULTICORE_CPU |
382 |
|
// Save program counters and branch registers |
383 |
|
uint32 saved_pc = pc(); |
384 |
|
uint32 saved_lr = lr(); |
385 |
|
uint32 saved_ctr= ctr(); |
386 |
+ |
uint32 saved_sp = gpr(1); |
387 |
|
#endif |
388 |
|
|
389 |
< |
// Create stack frame |
390 |
< |
gpr(1) -= 64; |
389 |
> |
// Initialize stack pointer to SheepShaver alternate stack base |
390 |
> |
gpr(1) = SignalStackBase() - 64; |
391 |
|
|
392 |
|
// Build trampoline to return from interrupt |
393 |
< |
uint32 trampoline[] = { POWERPC_EMUL_OP | 1 }; |
393 |
> |
SheepVar32 trampoline = POWERPC_EXEC_RETURN; |
394 |
|
|
395 |
|
// Prepare registers for nanokernel interrupt routine |
396 |
< |
kernel_data->v[0x004 >> 2] = gpr(1); |
397 |
< |
kernel_data->v[0x018 >> 2] = gpr(6); |
396 |
> |
kernel_data->v[0x004 >> 2] = htonl(gpr(1)); |
397 |
> |
kernel_data->v[0x018 >> 2] = htonl(gpr(6)); |
398 |
|
|
399 |
< |
gpr(6) = kernel_data->v[0x65c >> 2]; |
399 |
> |
gpr(6) = ntohl(kernel_data->v[0x65c >> 2]); |
400 |
|
assert(gpr(6) != 0); |
401 |
|
WriteMacInt32(gpr(6) + 0x13c, gpr(7)); |
402 |
|
WriteMacInt32(gpr(6) + 0x144, gpr(8)); |
407 |
|
WriteMacInt32(gpr(6) + 0x16c, gpr(13)); |
408 |
|
|
409 |
|
gpr(1) = KernelDataAddr; |
410 |
< |
gpr(7) = kernel_data->v[0x660 >> 2]; |
410 |
> |
gpr(7) = ntohl(kernel_data->v[0x660 >> 2]); |
411 |
|
gpr(8) = 0; |
412 |
< |
gpr(10) = (uint32)trampoline; |
413 |
< |
gpr(12) = (uint32)trampoline; |
414 |
< |
gpr(13) = cr().get(); |
412 |
> |
gpr(10) = trampoline.addr(); |
413 |
> |
gpr(12) = trampoline.addr(); |
414 |
> |
gpr(13) = get_cr(); |
415 |
|
|
416 |
|
// rlwimi. r7,r7,8,0,0 |
417 |
|
uint32 result = op_ppc_rlwimi::apply(gpr(7), 8, 0x80000000, gpr(7)); |
419 |
|
gpr(7) = result; |
420 |
|
|
421 |
|
gpr(11) = 0xf072; // MSR (SRR1) |
422 |
< |
cr().set((gpr(11) & 0x0fff0000) | (cr().get() & ~0x0fff0000)); |
422 |
> |
cr().set((gpr(11) & 0x0fff0000) | (get_cr() & ~0x0fff0000)); |
423 |
|
|
424 |
|
// Enter nanokernel |
425 |
|
execute(entry); |
426 |
|
|
322 |
– |
// Cleanup stack |
323 |
– |
gpr(1) += 64; |
324 |
– |
|
427 |
|
#if !MULTICORE_CPU |
428 |
|
// Restore program counters and branch registers |
429 |
|
pc() = saved_pc; |
430 |
|
lr() = saved_lr; |
431 |
|
ctr()= saved_ctr; |
432 |
+ |
gpr(1) = saved_sp; |
433 |
+ |
#endif |
434 |
+ |
|
435 |
+ |
#if EMUL_TIME_STATS |
436 |
+ |
interrupt_time += (clock() - interrupt_start); |
437 |
|
#endif |
438 |
|
} |
439 |
|
|
440 |
|
// Execute 68k routine |
441 |
|
void sheepshaver_cpu::execute_68k(uint32 entry, M68kRegisters *r) |
442 |
|
{ |
443 |
+ |
#if EMUL_TIME_STATS |
444 |
+ |
exec68k_count++; |
445 |
+ |
const clock_t exec68k_start = clock(); |
446 |
+ |
#endif |
447 |
+ |
|
448 |
|
#if SAFE_EXEC_68K |
449 |
|
if (ReadMacInt32(XLM_RUN_MODE) != MODE_EMUL_OP) |
450 |
|
printf("FATAL: Execute68k() not called from EMUL_OP mode\n"); |
454 |
|
uint32 saved_pc = pc(); |
455 |
|
uint32 saved_lr = lr(); |
456 |
|
uint32 saved_ctr= ctr(); |
457 |
+ |
uint32 saved_cr = get_cr(); |
458 |
|
|
459 |
|
// Create MacOS stack frame |
460 |
+ |
// FIXME: make sure MacOS doesn't expect PPC registers to live on top |
461 |
|
uint32 sp = gpr(1); |
462 |
< |
gpr(1) -= 56 + 19*4 + 18*8; |
462 |
> |
gpr(1) -= 56; |
463 |
|
WriteMacInt32(gpr(1), sp); |
464 |
|
|
465 |
|
// Save PowerPC registers |
466 |
< |
memcpy(Mac2HostAddr(gpr(1)+56), &gpr(13), sizeof(uint32)*(32-13)); |
466 |
> |
uint32 saved_GPRs[19]; |
467 |
> |
memcpy(&saved_GPRs[0], &gpr(13), sizeof(uint32)*(32-13)); |
468 |
|
#if SAVE_FP_EXEC_68K |
469 |
< |
memcpy(Mac2HostAddr(gpr(1)+56+19*4), &fpr(14), sizeof(double)*(32-14)); |
469 |
> |
double saved_FPRs[18]; |
470 |
> |
memcpy(&saved_FPRs[0], &fpr(14), sizeof(double)*(32-14)); |
471 |
|
#endif |
472 |
|
|
473 |
|
// Setup registers for 68k emulator |
481 |
|
gpr(25) = ReadMacInt32(XLM_68K_R25); // MSB of SR |
482 |
|
gpr(26) = 0; |
483 |
|
gpr(28) = 0; // VBR |
484 |
< |
gpr(29) = kernel_data->ed.v[0x74 >> 2]; // Pointer to opcode table |
485 |
< |
gpr(30) = kernel_data->ed.v[0x78 >> 2]; // Address of emulator |
484 |
> |
gpr(29) = ntohl(kernel_data->ed.v[0x74 >> 2]); // Pointer to opcode table |
485 |
> |
gpr(30) = ntohl(kernel_data->ed.v[0x78 >> 2]); // Address of emulator |
486 |
|
gpr(31) = KernelDataAddr + 0x1000; |
487 |
|
|
488 |
|
// Push return address (points to EXEC_RETURN opcode) on stack |
514 |
|
r->a[i] = gpr(16 + i); |
515 |
|
|
516 |
|
// Restore PowerPC registers |
517 |
< |
memcpy(&gpr(13), Mac2HostAddr(gpr(1)+56), sizeof(uint32)*(32-13)); |
517 |
> |
memcpy(&gpr(13), &saved_GPRs[0], sizeof(uint32)*(32-13)); |
518 |
|
#if SAVE_FP_EXEC_68K |
519 |
< |
memcpy(&fpr(14), Mac2HostAddr(gpr(1)+56+19*4), sizeof(double)*(32-14)); |
519 |
> |
memcpy(&fpr(14), &saved_FPRs[0], sizeof(double)*(32-14)); |
520 |
|
#endif |
521 |
|
|
522 |
|
// Cleanup stack |
523 |
< |
gpr(1) += 56 + 19*4 + 18*8; |
523 |
> |
gpr(1) += 56; |
524 |
|
|
525 |
|
// Restore program counters and branch registers |
526 |
|
pc() = saved_pc; |
527 |
|
lr() = saved_lr; |
528 |
|
ctr()= saved_ctr; |
529 |
+ |
set_cr(saved_cr); |
530 |
+ |
|
531 |
+ |
#if EMUL_TIME_STATS |
532 |
+ |
exec68k_time += (clock() - exec68k_start); |
533 |
+ |
#endif |
534 |
|
} |
535 |
|
|
536 |
|
// Call MacOS PPC code |
537 |
|
uint32 sheepshaver_cpu::execute_macos_code(uint32 tvect, int nargs, uint32 const *args) |
538 |
|
{ |
539 |
+ |
#if EMUL_TIME_STATS |
540 |
+ |
macos_exec_count++; |
541 |
+ |
const clock_t macos_exec_start = clock(); |
542 |
+ |
#endif |
543 |
+ |
|
544 |
|
// Save program counters and branch registers |
545 |
|
uint32 saved_pc = pc(); |
546 |
|
uint32 saved_lr = lr(); |
547 |
|
uint32 saved_ctr= ctr(); |
548 |
|
|
549 |
|
// Build trampoline with EXEC_RETURN |
550 |
< |
uint32 trampoline[] = { POWERPC_EMUL_OP | 1 }; |
551 |
< |
lr() = (uint32)trampoline; |
550 |
> |
SheepVar32 trampoline = POWERPC_EXEC_RETURN; |
551 |
> |
lr() = trampoline.addr(); |
552 |
|
|
553 |
|
gpr(1) -= 64; // Create stack frame |
554 |
|
uint32 proc = ReadMacInt32(tvect); // Get routine address |
579 |
|
lr() = saved_lr; |
580 |
|
ctr()= saved_ctr; |
581 |
|
|
582 |
+ |
#if EMUL_TIME_STATS |
583 |
+ |
macos_exec_time += (clock() - macos_exec_start); |
584 |
+ |
#endif |
585 |
+ |
|
586 |
|
return retval; |
587 |
|
} |
588 |
|
|
591 |
|
{ |
592 |
|
// Save branch registers |
593 |
|
uint32 saved_lr = lr(); |
464 |
– |
uint32 saved_ctr= ctr(); |
594 |
|
|
595 |
< |
const uint32 trampoline[] = { POWERPC_EMUL_OP | 1 }; |
595 |
> |
SheepVar32 trampoline = POWERPC_EXEC_RETURN; |
596 |
> |
WriteMacInt32(trampoline.addr(), POWERPC_EXEC_RETURN); |
597 |
> |
lr() = trampoline.addr(); |
598 |
|
|
468 |
– |
lr() = (uint32)trampoline; |
469 |
– |
ctr()= entry; |
599 |
|
execute(entry); |
600 |
|
|
601 |
|
// Restore branch registers |
602 |
|
lr() = saved_lr; |
474 |
– |
ctr()= saved_ctr; |
603 |
|
} |
604 |
|
|
605 |
|
// Resource Manager thunk |
478 |
– |
extern "C" void check_load_invoc(uint32 type, int16 id, uint16 **h); |
479 |
– |
|
606 |
|
inline void sheepshaver_cpu::get_resource(uint32 old_get_resource) |
607 |
|
{ |
608 |
|
uint32 type = gpr(3); |
613 |
|
|
614 |
|
// Call old routine |
615 |
|
execute_ppc(old_get_resource); |
490 |
– |
uint16 **handle = (uint16 **)gpr(3); |
616 |
|
|
617 |
|
// Call CheckLoad() |
618 |
+ |
uint32 handle = gpr(3); |
619 |
|
check_load_invoc(type, id, handle); |
620 |
< |
gpr(3) = (uint32)handle; |
620 |
> |
gpr(3) = handle; |
621 |
|
|
622 |
|
// Cleanup stack |
623 |
|
gpr(1) += 56; |
632 |
|
static sheepshaver_cpu *interrupt_cpu = NULL; // CPU emulator to handle interrupts |
633 |
|
static sheepshaver_cpu *current_cpu = NULL; // Current CPU emulator context |
634 |
|
|
635 |
+ |
void FlushCodeCache(uintptr start, uintptr end) |
636 |
+ |
{ |
637 |
+ |
D(bug("FlushCodeCache(%08x, %08x)\n", start, end)); |
638 |
+ |
main_cpu->invalidate_cache_range(start, end); |
639 |
+ |
#if MULTICORE_CPU |
640 |
+ |
interrupt_cpu->invalidate_cache_range(start, end); |
641 |
+ |
#endif |
642 |
+ |
} |
643 |
+ |
|
644 |
|
static inline void cpu_push(sheepshaver_cpu *new_cpu) |
645 |
|
{ |
646 |
|
#if MULTICORE_CPU |
671 |
|
* Initialize CPU emulation |
672 |
|
*/ |
673 |
|
|
674 |
< |
static struct sigaction sigsegv_action; |
540 |
< |
|
541 |
< |
#if defined(__powerpc__) |
542 |
< |
#include <sys/ucontext.h> |
543 |
< |
#endif |
544 |
< |
|
545 |
< |
static void sigsegv_handler(int sig, siginfo_t *sip, void *scp) |
674 |
> |
static sigsegv_return_t sigsegv_handler(sigsegv_address_t fault_address, sigsegv_address_t fault_instruction) |
675 |
|
{ |
547 |
– |
const uintptr addr = (uintptr)sip->si_addr; |
676 |
|
#if ENABLE_VOSF |
677 |
< |
// Handle screen fault. |
678 |
< |
extern bool Screen_fault_handler(sigsegv_address_t fault_address, sigsegv_address_t fault_instruction); |
679 |
< |
if (Screen_fault_handler((sigsegv_address_t)addr, SIGSEGV_INVALID_PC)) |
680 |
< |
return; |
677 |
> |
// Handle screen fault |
678 |
> |
extern bool Screen_fault_handler(sigsegv_address_t, sigsegv_address_t); |
679 |
> |
if (Screen_fault_handler(fault_address, fault_instruction)) |
680 |
> |
return SIGSEGV_RETURN_SUCCESS; |
681 |
|
#endif |
682 |
< |
#if defined(__powerpc__) |
683 |
< |
if (addr >= ROM_BASE && addr < ROM_BASE + ROM_SIZE) { |
684 |
< |
printf("IGNORE write access to ROM at %08x\n", addr); |
685 |
< |
(((ucontext_t *)scp)->uc_mcontext.regs)->nip += 4; |
686 |
< |
return; |
687 |
< |
} |
688 |
< |
if (addr >= 0xf3012000 && addr < 0xf3014000 && 0) { |
689 |
< |
printf("IGNORE write access to ROM at %08x\n", addr); |
690 |
< |
(((ucontext_t *)scp)->uc_mcontext.regs)->nip += 4; |
691 |
< |
return; |
682 |
> |
|
683 |
> |
const uintptr addr = (uintptr)fault_address; |
684 |
> |
#if HAVE_SIGSEGV_SKIP_INSTRUCTION |
685 |
> |
// Ignore writes to ROM |
686 |
> |
if ((addr - ROM_BASE) < ROM_SIZE) |
687 |
> |
return SIGSEGV_RETURN_SKIP_INSTRUCTION; |
688 |
> |
|
689 |
> |
// Get program counter of target CPU |
690 |
> |
sheepshaver_cpu * const cpu = current_cpu; |
691 |
> |
const uint32 pc = cpu->pc(); |
692 |
> |
|
693 |
> |
// Fault in Mac ROM or RAM? |
694 |
> |
bool mac_fault = (pc >= ROM_BASE) && (pc < (ROM_BASE + ROM_AREA_SIZE)) || (pc >= RAMBase) && (pc < (RAMBase + RAMSize)); |
695 |
> |
if (mac_fault) { |
696 |
> |
|
697 |
> |
// "VM settings" during MacOS 8 installation |
698 |
> |
if (pc == ROM_BASE + 0x488160 && cpu->gpr(20) == 0xf8000000) |
699 |
> |
return SIGSEGV_RETURN_SKIP_INSTRUCTION; |
700 |
> |
|
701 |
> |
// MacOS 8.5 installation |
702 |
> |
else if (pc == ROM_BASE + 0x488140 && cpu->gpr(16) == 0xf8000000) |
703 |
> |
return SIGSEGV_RETURN_SKIP_INSTRUCTION; |
704 |
> |
|
705 |
> |
// MacOS 8 serial drivers on startup |
706 |
> |
else if (pc == ROM_BASE + 0x48e080 && (cpu->gpr(8) == 0xf3012002 || cpu->gpr(8) == 0xf3012000)) |
707 |
> |
return SIGSEGV_RETURN_SKIP_INSTRUCTION; |
708 |
> |
|
709 |
> |
// MacOS 8.1 serial drivers on startup |
710 |
> |
else if (pc == ROM_BASE + 0x48c5e0 && (cpu->gpr(20) == 0xf3012002 || cpu->gpr(20) == 0xf3012000)) |
711 |
> |
return SIGSEGV_RETURN_SKIP_INSTRUCTION; |
712 |
> |
else if (pc == ROM_BASE + 0x4a10a0 && (cpu->gpr(20) == 0xf3012002 || cpu->gpr(20) == 0xf3012000)) |
713 |
> |
return SIGSEGV_RETURN_SKIP_INSTRUCTION; |
714 |
> |
|
715 |
> |
// Ignore all other faults, if requested |
716 |
> |
if (PrefsFindBool("ignoresegv")) |
717 |
> |
return SIGSEGV_RETURN_SKIP_INSTRUCTION; |
718 |
|
} |
565 |
– |
#endif |
566 |
– |
printf("Caught SIGSEGV at address %p\n", sip->si_addr); |
567 |
– |
printf("Native PC: %08x\n", (((ucontext_t *)scp)->uc_mcontext.regs)->nip); |
568 |
– |
printf("Current CPU: %s\n", current_cpu == main_cpu ? "main" : "interrupts"); |
569 |
– |
#if 1 |
570 |
– |
dump_registers(); |
719 |
|
#else |
720 |
< |
printf("Main CPU context\n"); |
573 |
< |
main_cpu->dump_registers(); |
574 |
< |
printf("Interrupts CPU context\n"); |
575 |
< |
interrupt_cpu->dump_registers(); |
720 |
> |
#error "FIXME: You don't have the capability to skip instruction within signal handlers" |
721 |
|
#endif |
722 |
+ |
|
723 |
+ |
printf("SIGSEGV\n"); |
724 |
+ |
printf(" pc %p\n", fault_instruction); |
725 |
+ |
printf(" ea %p\n", fault_address); |
726 |
+ |
printf(" cpu %s\n", current_cpu == main_cpu ? "main" : "interrupts"); |
727 |
+ |
dump_registers(); |
728 |
|
current_cpu->dump_log(); |
729 |
|
enter_mon(); |
730 |
|
QuitEmulator(); |
731 |
+ |
|
732 |
+ |
return SIGSEGV_RETURN_FAILURE; |
733 |
|
} |
734 |
|
|
735 |
|
void init_emul_ppc(void) |
737 |
|
// Initialize main CPU emulator |
738 |
|
main_cpu = new sheepshaver_cpu(); |
739 |
|
main_cpu->set_register(powerpc_registers::GPR(3), any_register((uint32)ROM_BASE + 0x30d000)); |
740 |
+ |
main_cpu->set_register(powerpc_registers::GPR(4), any_register(KernelDataAddr + 0x1000)); |
741 |
|
WriteMacInt32(XLM_RUN_MODE, MODE_68K); |
742 |
|
|
743 |
|
#if MULTICORE_CPU |
745 |
|
interrupt_cpu = new sheepshaver_cpu(); |
746 |
|
#endif |
747 |
|
|
748 |
< |
// Install SIGSEGV handler |
749 |
< |
sigemptyset(&sigsegv_action.sa_mask); |
596 |
< |
sigsegv_action.sa_sigaction = sigsegv_handler; |
597 |
< |
sigsegv_action.sa_flags = SA_SIGINFO; |
598 |
< |
sigsegv_action.sa_restorer = NULL; |
599 |
< |
sigaction(SIGSEGV, &sigsegv_action, NULL); |
748 |
> |
// Install the handler for SIGSEGV |
749 |
> |
sigsegv_install_handler(sigsegv_handler); |
750 |
|
|
751 |
|
#if ENABLE_MON |
752 |
|
// Install "regs" command in cxmon |
753 |
|
mon_add_command("regs", dump_registers, "regs Dump PowerPC registers\n"); |
754 |
|
mon_add_command("log", dump_log, "log Dump PowerPC emulation log\n"); |
755 |
|
#endif |
756 |
+ |
|
757 |
+ |
#if EMUL_TIME_STATS |
758 |
+ |
emul_start_time = clock(); |
759 |
+ |
#endif |
760 |
+ |
} |
761 |
+ |
|
762 |
+ |
/* |
763 |
+ |
* Deinitialize emulation |
764 |
+ |
*/ |
765 |
+ |
|
766 |
+ |
void exit_emul_ppc(void) |
767 |
+ |
{ |
768 |
+ |
#if EMUL_TIME_STATS |
769 |
+ |
clock_t emul_end_time = clock(); |
770 |
+ |
|
771 |
+ |
printf("### Statistics for SheepShaver emulation parts\n"); |
772 |
+ |
const clock_t emul_time = emul_end_time - emul_start_time; |
773 |
+ |
printf("Total emulation time : %.1f sec\n", double(emul_time) / double(CLOCKS_PER_SEC)); |
774 |
+ |
printf("Total interrupt count: %d (%2.1f Hz)\n", interrupt_count, |
775 |
+ |
(double(interrupt_count) * CLOCKS_PER_SEC) / double(emul_time)); |
776 |
+ |
|
777 |
+ |
#define PRINT_STATS(LABEL, VAR_PREFIX) do { \ |
778 |
+ |
printf("Total " LABEL " count : %d\n", VAR_PREFIX##_count); \ |
779 |
+ |
printf("Total " LABEL " time : %.1f sec (%.1f%%)\n", \ |
780 |
+ |
double(VAR_PREFIX##_time) / double(CLOCKS_PER_SEC), \ |
781 |
+ |
100.0 * double(VAR_PREFIX##_time) / double(emul_time)); \ |
782 |
+ |
} while (0) |
783 |
+ |
|
784 |
+ |
PRINT_STATS("Execute68k[Trap] execution", exec68k); |
785 |
+ |
PRINT_STATS("NativeOp execution", native_exec); |
786 |
+ |
PRINT_STATS("MacOS routine execution", macos_exec); |
787 |
+ |
|
788 |
+ |
#undef PRINT_STATS |
789 |
+ |
printf("\n"); |
790 |
+ |
#endif |
791 |
+ |
|
792 |
+ |
delete main_cpu; |
793 |
+ |
#if MULTICORE_CPU |
794 |
+ |
delete interrupt_cpu; |
795 |
+ |
#endif |
796 |
|
} |
797 |
|
|
798 |
|
/* |
802 |
|
void emul_ppc(uint32 entry) |
803 |
|
{ |
804 |
|
current_cpu = main_cpu; |
805 |
+ |
#if 0 |
806 |
|
current_cpu->start_log(); |
807 |
+ |
#endif |
808 |
+ |
// start emulation loop and enable code translation or caching |
809 |
|
current_cpu->execute(entry); |
810 |
|
} |
811 |
|
|
813 |
|
* Handle PowerPC interrupt |
814 |
|
*/ |
815 |
|
|
816 |
< |
// Atomic operations |
817 |
< |
extern int atomic_add(int *var, int v); |
818 |
< |
extern int atomic_and(int *var, int v); |
819 |
< |
extern int atomic_or(int *var, int v); |
820 |
< |
|
816 |
> |
#if ASYNC_IRQ |
817 |
> |
void HandleInterrupt(void) |
818 |
> |
{ |
819 |
> |
main_cpu->handle_interrupt(); |
820 |
> |
} |
821 |
> |
#else |
822 |
|
void TriggerInterrupt(void) |
823 |
|
{ |
824 |
|
#if 0 |
825 |
|
WriteMacInt32(0x16a, ReadMacInt32(0x16a) + 1); |
826 |
|
#else |
827 |
< |
SPCFLAGS_SET( SPCFLAG_INT ); |
827 |
> |
// Trigger interrupt to main cpu only |
828 |
> |
if (main_cpu) |
829 |
> |
main_cpu->trigger_interrupt(); |
830 |
|
#endif |
831 |
|
} |
832 |
+ |
#endif |
833 |
|
|
834 |
< |
static void HandleInterrupt(void) |
834 |
> |
void sheepshaver_cpu::handle_interrupt(void) |
835 |
|
{ |
836 |
|
// Do nothing if interrupts are disabled |
837 |
< |
if (int32(ReadMacInt32(XLM_IRQ_NEST)) > 0) |
837 |
> |
if (*(int32 *)XLM_IRQ_NEST > 0) |
838 |
|
return; |
839 |
|
|
840 |
|
// Do nothing if there is no interrupt pending |
850 |
|
// 68k emulator active, trigger 68k interrupt level 1 |
851 |
|
assert(current_cpu == main_cpu); |
852 |
|
WriteMacInt16(tswap32(kernel_data->v[0x67c >> 2]), 1); |
853 |
< |
main_cpu->set_cr(main_cpu->get_cr() | tswap32(kernel_data->v[0x674 >> 2])); |
853 |
> |
set_cr(get_cr() | tswap32(kernel_data->v[0x674 >> 2])); |
854 |
|
break; |
855 |
|
|
856 |
|
#if INTERRUPTS_IN_NATIVE_MODE |
857 |
|
case MODE_NATIVE: |
858 |
|
// 68k emulator inactive, in nanokernel? |
859 |
|
assert(current_cpu == main_cpu); |
860 |
< |
if (main_cpu->gpr(1) != KernelDataAddr) { |
860 |
> |
if (gpr(1) != KernelDataAddr) { |
861 |
|
// Prepare for 68k interrupt level 1 |
862 |
|
WriteMacInt16(tswap32(kernel_data->v[0x67c >> 2]), 1); |
863 |
|
WriteMacInt32(tswap32(kernel_data->v[0x658 >> 2]) + 0xdc, |
868 |
|
DisableInterrupt(); |
869 |
|
cpu_push(interrupt_cpu); |
870 |
|
if (ROMType == ROMTYPE_NEWWORLD) |
871 |
< |
current_cpu->interrupt(ROM_BASE + 0x312b1c, main_cpu); |
871 |
> |
current_cpu->interrupt(ROM_BASE + 0x312b1c); |
872 |
|
else |
873 |
< |
current_cpu->interrupt(ROM_BASE + 0x312a3c, main_cpu); |
873 |
> |
current_cpu->interrupt(ROM_BASE + 0x312a3c); |
874 |
|
cpu_pop(); |
875 |
|
} |
876 |
|
break; |
901 |
|
if (InterruptFlags & INTFLAG_VIA) { |
902 |
|
ClearInterruptFlag(INTFLAG_VIA); |
903 |
|
ADBInterrupt(); |
904 |
< |
ExecutePPC(VideoVBL); |
904 |
> |
ExecuteNative(NATIVE_VIDEO_VBL); |
905 |
|
} |
906 |
|
} |
907 |
|
#endif |
911 |
|
} |
912 |
|
} |
913 |
|
|
717 |
– |
/* |
718 |
– |
* Execute NATIVE_OP opcode (called by PowerPC emulator) |
719 |
– |
*/ |
720 |
– |
|
721 |
– |
#define POWERPC_NATIVE_OP_INIT(LR, OP) \ |
722 |
– |
tswap32(POWERPC_EMUL_OP | ((LR) << 11) | (((uint32)OP) << 6) | 2) |
723 |
– |
|
724 |
– |
// FIXME: Make sure 32-bit relocations are used |
725 |
– |
const uint32 NativeOpTable[NATIVE_OP_MAX] = { |
726 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_PATCH_NAME_REGISTRY), |
727 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_VIDEO_INSTALL_ACCEL), |
728 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_VIDEO_VBL), |
729 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_VIDEO_DO_DRIVER_IO), |
730 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_ETHER_IRQ), |
731 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_ETHER_INIT), |
732 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_ETHER_TERM), |
733 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_ETHER_OPEN), |
734 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_ETHER_CLOSE), |
735 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_ETHER_WPUT), |
736 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_ETHER_RSRV), |
737 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_SERIAL_NOTHING), |
738 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_SERIAL_OPEN), |
739 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_SERIAL_PRIME_IN), |
740 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_SERIAL_PRIME_OUT), |
741 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_SERIAL_CONTROL), |
742 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_SERIAL_STATUS), |
743 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_SERIAL_CLOSE), |
744 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_GET_RESOURCE), |
745 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_GET_1_RESOURCE), |
746 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_GET_IND_RESOURCE), |
747 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_GET_1_IND_RESOURCE), |
748 |
– |
POWERPC_NATIVE_OP_INIT(1, NATIVE_R_GET_RESOURCE), |
749 |
– |
POWERPC_NATIVE_OP_INIT(0, NATIVE_DISABLE_INTERRUPT), |
750 |
– |
POWERPC_NATIVE_OP_INIT(0, NATIVE_ENABLE_INTERRUPT), |
751 |
– |
}; |
752 |
– |
|
914 |
|
static void get_resource(void); |
915 |
|
static void get_1_resource(void); |
916 |
|
static void get_ind_resource(void); |
921 |
|
|
922 |
|
static void NativeOp(int selector) |
923 |
|
{ |
924 |
+ |
#if EMUL_TIME_STATS |
925 |
+ |
native_exec_count++; |
926 |
+ |
const clock_t native_exec_start = clock(); |
927 |
+ |
#endif |
928 |
+ |
|
929 |
|
switch (selector) { |
930 |
|
case NATIVE_PATCH_NAME_REGISTRY: |
931 |
|
DoPatchNameRegistry(); |
940 |
|
GPR(3) = (int32)(int16)VideoDoDriverIO((void *)GPR(3), (void *)GPR(4), |
941 |
|
(void *)GPR(5), GPR(6), GPR(7)); |
942 |
|
break; |
943 |
< |
case NATIVE_GET_RESOURCE: |
944 |
< |
get_resource(); |
943 |
> |
#ifdef WORDS_BIGENDIAN |
944 |
> |
case NATIVE_ETHER_IRQ: |
945 |
> |
EtherIRQ(); |
946 |
|
break; |
947 |
< |
case NATIVE_GET_1_RESOURCE: |
948 |
< |
get_1_resource(); |
947 |
> |
case NATIVE_ETHER_INIT: |
948 |
> |
GPR(3) = InitStreamModule((void *)GPR(3)); |
949 |
|
break; |
950 |
< |
case NATIVE_GET_IND_RESOURCE: |
951 |
< |
get_ind_resource(); |
950 |
> |
case NATIVE_ETHER_TERM: |
951 |
> |
TerminateStreamModule(); |
952 |
|
break; |
953 |
< |
case NATIVE_GET_1_IND_RESOURCE: |
954 |
< |
get_1_ind_resource(); |
953 |
> |
case NATIVE_ETHER_OPEN: |
954 |
> |
GPR(3) = ether_open((queue_t *)GPR(3), (void *)GPR(4), GPR(5), GPR(6), (void*)GPR(7)); |
955 |
> |
break; |
956 |
> |
case NATIVE_ETHER_CLOSE: |
957 |
> |
GPR(3) = ether_close((queue_t *)GPR(3), GPR(4), (void *)GPR(5)); |
958 |
> |
break; |
959 |
> |
case NATIVE_ETHER_WPUT: |
960 |
> |
GPR(3) = ether_wput((queue_t *)GPR(3), (mblk_t *)GPR(4)); |
961 |
|
break; |
962 |
< |
case NATIVE_R_GET_RESOURCE: |
963 |
< |
r_get_resource(); |
962 |
> |
case NATIVE_ETHER_RSRV: |
963 |
> |
GPR(3) = ether_rsrv((queue_t *)GPR(3)); |
964 |
|
break; |
965 |
+ |
#else |
966 |
+ |
case NATIVE_ETHER_INIT: |
967 |
+ |
// FIXME: needs more complicated thunks |
968 |
+ |
GPR(3) = false; |
969 |
+ |
break; |
970 |
+ |
#endif |
971 |
|
case NATIVE_SERIAL_NOTHING: |
972 |
|
case NATIVE_SERIAL_OPEN: |
973 |
|
case NATIVE_SERIAL_PRIME_IN: |
988 |
|
GPR(3) = serial_callbacks[selector - NATIVE_SERIAL_NOTHING](GPR(3), GPR(4)); |
989 |
|
break; |
990 |
|
} |
991 |
+ |
case NATIVE_GET_RESOURCE: |
992 |
+ |
case NATIVE_GET_1_RESOURCE: |
993 |
+ |
case NATIVE_GET_IND_RESOURCE: |
994 |
+ |
case NATIVE_GET_1_IND_RESOURCE: |
995 |
+ |
case NATIVE_R_GET_RESOURCE: { |
996 |
+ |
typedef void (*GetResourceCallback)(void); |
997 |
+ |
static const GetResourceCallback get_resource_callbacks[] = { |
998 |
+ |
get_resource, |
999 |
+ |
get_1_resource, |
1000 |
+ |
get_ind_resource, |
1001 |
+ |
get_1_ind_resource, |
1002 |
+ |
r_get_resource |
1003 |
+ |
}; |
1004 |
+ |
get_resource_callbacks[selector - NATIVE_GET_RESOURCE](); |
1005 |
+ |
break; |
1006 |
+ |
} |
1007 |
|
case NATIVE_DISABLE_INTERRUPT: |
1008 |
|
DisableInterrupt(); |
1009 |
|
break; |
1010 |
|
case NATIVE_ENABLE_INTERRUPT: |
1011 |
|
EnableInterrupt(); |
1012 |
|
break; |
1013 |
+ |
case NATIVE_MAKE_EXECUTABLE: |
1014 |
+ |
MakeExecutable(0, (void *)GPR(4), GPR(5)); |
1015 |
+ |
break; |
1016 |
+ |
case NATIVE_CHECK_LOAD_INVOC: |
1017 |
+ |
check_load_invoc(GPR(3), GPR(4), GPR(5)); |
1018 |
+ |
break; |
1019 |
|
default: |
1020 |
|
printf("FATAL: NATIVE_OP called with bogus selector %d\n", selector); |
1021 |
|
QuitEmulator(); |
1022 |
|
break; |
1023 |
|
} |
823 |
– |
} |
824 |
– |
|
825 |
– |
/* |
826 |
– |
* Execute native subroutine (LR must contain return address) |
827 |
– |
*/ |
1024 |
|
|
1025 |
< |
void ExecuteNative(int selector) |
1026 |
< |
{ |
1027 |
< |
uint32 tvect[2]; |
832 |
< |
tvect[0] = tswap32(POWERPC_NATIVE_OP_FUNC(selector)); |
833 |
< |
tvect[1] = 0; // Fake TVECT |
834 |
< |
RoutineDescriptor desc = BUILD_PPC_ROUTINE_DESCRIPTOR(0, tvect); |
835 |
< |
M68kRegisters r; |
836 |
< |
Execute68k((uint32)&desc, &r); |
1025 |
> |
#if EMUL_TIME_STATS |
1026 |
> |
native_exec_time += (clock() - native_exec_start); |
1027 |
> |
#endif |
1028 |
|
} |
1029 |
|
|
1030 |
|
/* |
1045 |
|
|
1046 |
|
void Execute68kTrap(uint16 trap, M68kRegisters *r) |
1047 |
|
{ |
1048 |
< |
uint16 proc[2] = {trap, M68K_RTS}; |
1049 |
< |
Execute68k((uint32)proc, r); |
1048 |
> |
SheepVar proc_var(4); |
1049 |
> |
uint32 proc = proc_var.addr(); |
1050 |
> |
WriteMacInt16(proc, trap); |
1051 |
> |
WriteMacInt16(proc + 2, M68K_RTS); |
1052 |
> |
Execute68k(proc, r); |
1053 |
|
} |
1054 |
|
|
1055 |
|
/* |
1104 |
|
} |
1105 |
|
|
1106 |
|
/* |
913 |
– |
* Atomic operations |
914 |
– |
*/ |
915 |
– |
|
916 |
– |
int atomic_add(int *var, int v) |
917 |
– |
{ |
918 |
– |
int ret = *var; |
919 |
– |
*var += v; |
920 |
– |
return ret; |
921 |
– |
} |
922 |
– |
|
923 |
– |
int atomic_and(int *var, int v) |
924 |
– |
{ |
925 |
– |
int ret = *var; |
926 |
– |
*var &= v; |
927 |
– |
return ret; |
928 |
– |
} |
929 |
– |
|
930 |
– |
int atomic_or(int *var, int v) |
931 |
– |
{ |
932 |
– |
int ret = *var; |
933 |
– |
*var |= v; |
934 |
– |
return ret; |
935 |
– |
} |
936 |
– |
|
937 |
– |
/* |
1107 |
|
* Resource Manager thunks |
1108 |
|
*/ |
1109 |
|
|