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root/cebix/SheepShaver/src/kpx_cpu/sheepshaver_glue.cpp

Comparing SheepShaver/src/kpx_cpu/sheepshaver_glue.cpp (file contents):
Revision 1.2 by gbeauche, 2003-09-28T21:27:34Z vs.
Revision 1.11 by gbeauche, 2003-10-26T14:16:39Z

#	Line 21 | Line 21
21		#include "sysdeps.h"
22		#include "cpu_emulation.h"
23		#include "main.h"
24	+	#include "prefs.h"
25		#include "xlowmem.h"
26		#include "emul_op.h"
27		#include "rom_patches.h"
#	Line 43 | Line 44
44		#include "mon_disass.h"
45		#endif
46
47	<	#define DEBUG 1
47	>	#define DEBUG 0
48		#include "debug.h"
49
50		static void enter_mon(void)
#	Line 56 | Line 57 | static void enter_mon(void)
57		}
58
59		// Enable multicore (main/interrupts) cpu emulation?
60	<	#define MULTICORE_CPU 0
60	>	#define MULTICORE_CPU (ASYNC_IRQ ? 1 : 0)
61
62		// Enable Execute68k() safety checks?
63		#define SAFE_EXEC_68K 1
#	Line 70 | Line 71 | static void enter_mon(void)
71		// Interrupts in native mode?
72		#define INTERRUPTS_IN_NATIVE_MODE 1
73
73	–	// 68k Emulator Data
74	–	struct EmulatorData {
75	–	uint32  v[0x400];
76	–	};
77	–
78	–	// Kernel Data
79	–	struct KernelData {
80	–	uint32  v[0x400];
81	–	EmulatorData ed;
82	–	};
83	–
74		// Pointer to Kernel Data
75	<	static KernelData * const kernel_data = (KernelData *)0x68ffe000;
75	>	static KernelData * const kernel_data = (KernelData *)KERNEL_DATA_BASE;
76
77
78		/**
#	Line 99 | Line 89 | class sheepshaver_cpu
89
90		public:
91
92	<	sheepshaver_cpu()
93	<	: powerpc_cpu()
104	<	{ init_decoder(); }
92	>	// Constructor
93	>	sheepshaver_cpu();
94
95		// Condition Register accessors
96		uint32 get_cr() const           { return cr().get(); }
97		void set_cr(uint32 v)           { cr().set(v); }
98
99		// Execution loop
100	<	void execute(uint32 pc);
100	>	void execute(uint32 entry, bool enable_cache = false);
101
102		// Execute 68k routine
103		void execute_68k(uint32 entry, M68kRegisters *r);
#	Line 123 | Line 112 | public:
112		void get_resource(uint32 old_get_resource);
113
114		// Handle MacOS interrupt
115	<	void interrupt(uint32 entry, sheepshaver_cpu *cpu);
115	>	void interrupt(uint32 entry);
116	>	void handle_interrupt();
117
118		// spcflags for interrupts handling
119		static uint32 spcflags;
#	Line 141 | Line 131 | public:
131		uint32 sheepshaver_cpu::spcflags = 0;
132		lazy_allocator< sheepshaver_cpu > allocator_helper< sheepshaver_cpu, lazy_allocator >::allocator;
133
134	+	sheepshaver_cpu::sheepshaver_cpu()
135	+	: powerpc_cpu()
136	+	{
137	+	init_decoder();
138	+	}
139	+
140		void sheepshaver_cpu::init_decoder()
141		{
142		#ifndef PPC_NO_STATIC_II_INDEX_TABLE
#	Line 154 | Line 150 | void sheepshaver_cpu::init_decoder()
150		{ "sheep",
151		(execute_fn)&sheepshaver_cpu::execute_sheep,
152		NULL,
153	<	D_form, 6, 0, CFLOW_TRAP
153	>	D_form, 6, 0, CFLOW_JUMP | CFLOW_TRAP
154		}
155		};
156
#	Line 191 | Line 187 | void sheepshaver_cpu::execute_sheep(uint
187		case 0:         // EMUL_RETURN
188		QuitEmulator();
189		break;
190	<
190	>
191		case 1:         // EXEC_RETURN
192		throw sheepshaver_exec_return();
193		break;
#	Line 226 | Line 222 | void sheepshaver_cpu::execute_sheep(uint
222		}
223		}
224
229	–	// Checks for pending interrupts
230	–	struct execute_nothing {
231	–	static inline void execute(powerpc_cpu *) { }
232	–	};
233	–
234	–	static void HandleInterrupt(void);
235	–
236	–	struct execute_spcflags_check {
237	–	static inline void execute(powerpc_cpu *cpu) {
238	–	if (SPCFLAGS_TEST(SPCFLAG_ALL_BUT_EXEC_RETURN)) {
239	–	if (SPCFLAGS_TEST( SPCFLAG_ENTER_MON )) {
240	–	SPCFLAGS_CLEAR( SPCFLAG_ENTER_MON );
241	–	enter_mon();
242	–	}
243	–	if (SPCFLAGS_TEST( SPCFLAG_DOINT )) {
244	–	SPCFLAGS_CLEAR( SPCFLAG_DOINT );
245	–	HandleInterrupt();
246	–	}
247	–	if (SPCFLAGS_TEST( SPCFLAG_INT )) {
248	–	SPCFLAGS_CLEAR( SPCFLAG_INT );
249	–	SPCFLAGS_SET( SPCFLAG_DOINT );
250	–	}
251	–	}
252	–	}
253	–	};
254	–
225		// Execution loop
226	<	void sheepshaver_cpu::execute(uint32 entry)
226	>	void sheepshaver_cpu::execute(uint32 entry, bool enable_cache)
227		{
228		try {
229	<	pc() = entry;
260	<	powerpc_cpu::do_execute<execute_nothing, execute_spcflags_check>();
229	>	powerpc_cpu::execute(entry, enable_cache);
230		}
231		catch (sheepshaver_exec_return const &) {
232		// Nothing, simply return
#	Line 269 | Line 238 | void sheepshaver_cpu::execute(uint32 ent
238		}
239
240		// Handle MacOS interrupt
241	<	void sheepshaver_cpu::interrupt(uint32 entry, sheepshaver_cpu *cpu)
241	>	void sheepshaver_cpu::interrupt(uint32 entry)
242		{
243	<	#if MULTICORE_CPU
275	<	// Initialize stack pointer from previous CPU running
276	<	gpr(1) = cpu->gpr(1);
277	<	#else
243	>	#if !MULTICORE_CPU
244		// Save program counters and branch registers
245		uint32 saved_pc = pc();
246		uint32 saved_lr = lr();
247		uint32 saved_ctr= ctr();
248	+	uint32 saved_sp = gpr(1);
249		#endif
250
251	<	// Create stack frame
252	<	gpr(1) -= 64;
251	>	// Initialize stack pointer to SheepShaver alternate stack base
252	>	gpr(1) = SheepStack1Base - 64;
253
254		// Build trampoline to return from interrupt
255	<	uint32 trampoline[] = { POWERPC_EMUL_OP | 1 };
255	>	uint32 trampoline[] = { htonl(POWERPC_EMUL_OP | 1) };
256
257		// Prepare registers for nanokernel interrupt routine
258	<	kernel_data->v[0x004 >> 2] = gpr(1);
259	<	kernel_data->v[0x018 >> 2] = gpr(6);
258	>	kernel_data->v[0x004 >> 2] = htonl(gpr(1));
259	>	kernel_data->v[0x018 >> 2] = htonl(gpr(6));
260
261	<	gpr(6) = kernel_data->v[0x65c >> 2];
261	>	gpr(6) = ntohl(kernel_data->v[0x65c >> 2]);
262		assert(gpr(6) != 0);
263		WriteMacInt32(gpr(6) + 0x13c, gpr(7));
264		WriteMacInt32(gpr(6) + 0x144, gpr(8));
#	Line 302 | Line 269 | void sheepshaver_cpu::interrupt(uint32 e
269		WriteMacInt32(gpr(6) + 0x16c, gpr(13));
270
271		gpr(1)  = KernelDataAddr;
272	<	gpr(7)  = kernel_data->v[0x660 >> 2];
272	>	gpr(7)  = ntohl(kernel_data->v[0x660 >> 2]);
273		gpr(8)  = 0;
274		gpr(10) = (uint32)trampoline;
275		gpr(12) = (uint32)trampoline;
276	<	gpr(13) = cr().get();
276	>	gpr(13) = get_cr();
277
278		// rlwimi. r7,r7,8,0,0
279		uint32 result = op_ppc_rlwimi::apply(gpr(7), 8, 0x80000000, gpr(7));
#	Line 314 | Line 281 | void sheepshaver_cpu::interrupt(uint32 e
281		gpr(7) = result;
282
283		gpr(11) = 0xf072; // MSR (SRR1)
284	<	cr().set((gpr(11) & 0x0fff0000) | (cr().get() & ~0x0fff0000));
284	>	cr().set((gpr(11) & 0x0fff0000) | (get_cr() & ~0x0fff0000));
285
286		// Enter nanokernel
287		execute(entry);
288
322	–	// Cleanup stack
323	–	gpr(1) += 64;
324	–
289		#if !MULTICORE_CPU
290		// Restore program counters and branch registers
291		pc() = saved_pc;
292		lr() = saved_lr;
293		ctr()= saved_ctr;
294	+	gpr(1) = saved_sp;
295		#endif
296		}
297
#	Line 342 | Line 307 | void sheepshaver_cpu::execute_68k(uint32
307		uint32 saved_pc = pc();
308		uint32 saved_lr = lr();
309		uint32 saved_ctr= ctr();
310	+	uint32 saved_cr = get_cr();
311
312		// Create MacOS stack frame
313	+	// FIXME: make sure MacOS doesn't expect PPC registers to live on top
314		uint32 sp = gpr(1);
315	<	gpr(1) -= 56 + 19*4 + 18*8;
315	>	gpr(1) -= 56;
316		WriteMacInt32(gpr(1), sp);
317
318		// Save PowerPC registers
319	<	memcpy(Mac2HostAddr(gpr(1)+56), &gpr(13), sizeof(uint32)*(32-13));
319	>	uint32 saved_GPRs[19];
320	>	memcpy(&saved_GPRs[0], &gpr(13), sizeof(uint32)*(32-13));
321		#if SAVE_FP_EXEC_68K
322	<	memcpy(Mac2HostAddr(gpr(1)+56+19*4), &fpr(14), sizeof(double)*(32-14));
322	>	double saved_FPRs[18];
323	>	memcpy(&saved_FPRs[0], &fpr(14), sizeof(double)*(32-14));
324		#endif
325
326		// Setup registers for 68k emulator
#	Line 365 | Line 334 | void sheepshaver_cpu::execute_68k(uint32
334		gpr(25) = ReadMacInt32(XLM_68K_R25);            // MSB of SR
335		gpr(26) = 0;
336		gpr(28) = 0;                                                            // VBR
337	<	gpr(29) = kernel_data->ed.v[0x74 >> 2];         // Pointer to opcode table
338	<	gpr(30) = kernel_data->ed.v[0x78 >> 2];         // Address of emulator
337	>	gpr(29) = ntohl(kernel_data->ed.v[0x74 >> 2]);          // Pointer to opcode table
338	>	gpr(30) = ntohl(kernel_data->ed.v[0x78 >> 2]);          // Address of emulator
339		gpr(31) = KernelDataAddr + 0x1000;
340
341		// Push return address (points to EXEC_RETURN opcode) on stack
#	Line 398 | Line 367 | void sheepshaver_cpu::execute_68k(uint32
367		r->a[i] = gpr(16 + i);
368
369		// Restore PowerPC registers
370	<	memcpy(&gpr(13), Mac2HostAddr(gpr(1)+56), sizeof(uint32)*(32-13));
370	>	memcpy(&gpr(13), &saved_GPRs[0], sizeof(uint32)*(32-13));
371		#if SAVE_FP_EXEC_68K
372	<	memcpy(&fpr(14), Mac2HostAddr(gpr(1)+56+19*4), sizeof(double)*(32-14));
372	>	memcpy(&fpr(14), &saved_FPRs[0], sizeof(double)*(32-14));
373		#endif
374
375		// Cleanup stack
376	<	gpr(1) += 56 + 19*4 + 18*8;
376	>	gpr(1) += 56;
377
378		// Restore program counters and branch registers
379		pc() = saved_pc;
380		lr() = saved_lr;
381		ctr()= saved_ctr;
382	+	set_cr(saved_cr);
383		}
384
385		// Call MacOS PPC code
#	Line 421 | Line 391 | uint32 sheepshaver_cpu::execute_macos_co
391		uint32 saved_ctr= ctr();
392
393		// Build trampoline with EXEC_RETURN
394	<	uint32 trampoline[] = { POWERPC_EMUL_OP | 1 };
394	>	uint32 trampoline[] = { htonl(POWERPC_EMUL_OP | 1) };
395		lr() = (uint32)trampoline;
396
397		gpr(1) -= 64;                                                           // Create stack frame
#	Line 461 | Line 431 | inline void sheepshaver_cpu::execute_ppc
431		{
432		// Save branch registers
433		uint32 saved_lr = lr();
464	–	uint32 saved_ctr= ctr();
465	–
466	–	const uint32 trampoline[] = { POWERPC_EMUL_OP | 1 };
434
435	+	const uint32 trampoline[] = { htonl(POWERPC_EMUL_OP | 1) };
436		lr() = (uint32)trampoline;
437	<	ctr()= entry;
437	>
438		execute(entry);
439
440		// Restore branch registers
441		lr() = saved_lr;
474	–	ctr()= saved_ctr;
442		}
443
444		// Resource Manager thunk
445	<	extern "C" void check_load_invoc(uint32 type, int16 id, uint16 **h);
445	>	extern "C" void check_load_invoc(uint32 type, int16 id, uint32 h);
446
447		inline void sheepshaver_cpu::get_resource(uint32 old_get_resource)
448		{
#	Line 487 | Line 454 | inline void sheepshaver_cpu::get_resourc
454
455		// Call old routine
456		execute_ppc(old_get_resource);
490	–	uint16 **handle = (uint16 **)gpr(3);
457
458		// Call CheckLoad()
459	+	uint32 handle = gpr(3);
460		check_load_invoc(type, id, handle);
461	<	gpr(3) = (uint32)handle;
461	>	gpr(3) = handle;
462
463		// Cleanup stack
464		gpr(1) += 56;
#	Line 506 | Line 473 | static sheepshaver_cpu *main_cpu = NULL;
473		static sheepshaver_cpu *interrupt_cpu = NULL;   // CPU emulator to handle interrupts
474		static sheepshaver_cpu *current_cpu = NULL;             // Current CPU emulator context
475
476	+	void FlushCodeCache(uintptr start, uintptr end)
477	+	{
478	+	D(bug("FlushCodeCache(%08x, %08x)\n", start, end));
479	+	main_cpu->invalidate_cache_range(start, end);
480	+	#if MULTICORE_CPU
481	+	interrupt_cpu->invalidate_cache_range(start, end);
482	+	#endif
483	+	}
484	+
485		static inline void cpu_push(sheepshaver_cpu *new_cpu)
486		{
487		#if MULTICORE_CPU
#	Line 536 | Line 512 | static void dump_log(void)
512		*  Initialize CPU emulation
513		*/
514
515	<	static struct sigaction sigsegv_action;
540	<
541	<	#if defined(__powerpc__)
542	<	#include <sys/ucontext.h>
543	<	#endif
544	<
545	<	static void sigsegv_handler(int sig, siginfo_t *sip, void *scp)
515	>	static sigsegv_return_t sigsegv_handler(sigsegv_address_t fault_address, sigsegv_address_t fault_instruction)
516		{
547	–	const uintptr addr = (uintptr)sip->si_addr;
517		#if ENABLE_VOSF
518	<	// Handle screen fault.
519	<	extern bool Screen_fault_handler(sigsegv_address_t fault_address, sigsegv_address_t fault_instruction);
520	<	if (Screen_fault_handler((sigsegv_address_t)addr, SIGSEGV_INVALID_PC))
521	<	return;
553	<	#endif
554	<	#if defined(__powerpc__)
555	<	if (addr >= ROM_BASE && addr < ROM_BASE + ROM_SIZE) {
556	<	printf("IGNORE write access to ROM at %08x\n", addr);
557	<	(((ucontext_t *)scp)->uc_mcontext.regs)->nip += 4;
558	<	return;
559	<	}
560	<	if (addr >= 0xf3012000 && addr < 0xf3014000 && 0) {
561	<	printf("IGNORE write access to ROM at %08x\n", addr);
562	<	(((ucontext_t *)scp)->uc_mcontext.regs)->nip += 4;
563	<	return;
564	<	}
518	>	// Handle screen fault
519	>	extern bool Screen_fault_handler(sigsegv_address_t, sigsegv_address_t);
520	>	if (Screen_fault_handler(fault_address, fault_instruction))
521	>	return SIGSEGV_RETURN_SUCCESS;
522		#endif
523	<	printf("Caught SIGSEGV at address %p\n", sip->si_addr);
524	<	printf("Native PC: %08x\n", (((ucontext_t *)scp)->uc_mcontext.regs)->nip);
525	<	printf("Current CPU: %s\n", current_cpu == main_cpu ? "main" : "interrupts");
526	<	#if 1
527	<	dump_registers();
523	>
524	>	const uintptr addr = (uintptr)fault_address;
525	>	#if HAVE_SIGSEGV_SKIP_INSTRUCTION
526	>	// Ignore writes to ROM
527	>	if ((addr - ROM_BASE) < ROM_SIZE)
528	>	return SIGSEGV_RETURN_SKIP_INSTRUCTION;
529	>
530	>	// Ignore all other faults, if requested
531	>	if (PrefsFindBool("ignoresegv"))
532	>	return SIGSEGV_RETURN_FAILURE;
533		#else
534	<	printf("Main CPU context\n");
573	<	main_cpu->dump_registers();
574	<	printf("Interrupts CPU context\n");
575	<	interrupt_cpu->dump_registers();
534	>	#error "FIXME: You don't have the capability to skip instruction within signal handlers"
535		#endif
536	+
537	+	printf("SIGSEGV\n");
538	+	printf("  pc %p\n", fault_instruction);
539	+	printf("  ea %p\n", fault_address);
540	+	printf(" cpu %s\n", current_cpu == main_cpu ? "main" : "interrupts");
541	+	dump_registers();
542		current_cpu->dump_log();
543		enter_mon();
544		QuitEmulator();
545	+
546	+	return SIGSEGV_RETURN_FAILURE;
547		}
548
549		void init_emul_ppc(void)
#	Line 591 | Line 558 | void init_emul_ppc(void)
558		interrupt_cpu = new sheepshaver_cpu();
559		#endif
560
561	<	// Install SIGSEGV handler
562	<	sigemptyset(&sigsegv_action.sa_mask);
596	<	sigsegv_action.sa_sigaction = sigsegv_handler;
597	<	sigsegv_action.sa_flags = SA_SIGINFO;
598	<	sigsegv_action.sa_restorer = NULL;
599	<	sigaction(SIGSEGV, &sigsegv_action, NULL);
561	>	// Install the handler for SIGSEGV
562	>	sigsegv_install_handler(sigsegv_handler);
563
564		#if ENABLE_MON
565		// Install "regs" command in cxmon
#	Line 612 | Line 575 | void init_emul_ppc(void)
575		void emul_ppc(uint32 entry)
576		{
577		current_cpu = main_cpu;
578	+	#if DEBUG
579		current_cpu->start_log();
580	<	current_cpu->execute(entry);
580	>	#endif
581	>	// start emulation loop and enable code translation or caching
582	>	current_cpu->execute(entry, true);
583		}
584
585		/*
586		*  Handle PowerPC interrupt
587		*/
588
589	<	// Atomic operations
590	<	extern int atomic_add(int *var, int v);
591	<	extern int atomic_and(int *var, int v);
592	<	extern int atomic_or(int *var, int v);
593	<
589	>	#if ASYNC_IRQ
590	>	void HandleInterrupt(void)
591	>	{
592	>	main_cpu->handle_interrupt();
593	>	}
594	>	#else
595		void TriggerInterrupt(void)
596		{
597		#if 0
598		WriteMacInt32(0x16a, ReadMacInt32(0x16a) + 1);
599		#else
600	<	SPCFLAGS_SET( SPCFLAG_INT );
600	>	// Trigger interrupt to main cpu only
601	>	if (main_cpu)
602	>	main_cpu->trigger_interrupt();
603		#endif
604		}
605	+	#endif
606
607	<	static void HandleInterrupt(void)
607	>	void sheepshaver_cpu::handle_interrupt(void)
608		{
609		// Do nothing if interrupts are disabled
610		if (int32(ReadMacInt32(XLM_IRQ_NEST)) > 0)
#	Line 653 | Line 623 | static void HandleInterrupt(void)
623		// 68k emulator active, trigger 68k interrupt level 1
624		assert(current_cpu == main_cpu);
625		WriteMacInt16(tswap32(kernel_data->v[0x67c >> 2]), 1);
626	<	main_cpu->set_cr(main_cpu->get_cr() | tswap32(kernel_data->v[0x674 >> 2]));
626	>	set_cr(get_cr() | tswap32(kernel_data->v[0x674 >> 2]));
627		break;
628
629		#if INTERRUPTS_IN_NATIVE_MODE
630		case MODE_NATIVE:
631		// 68k emulator inactive, in nanokernel?
632		assert(current_cpu == main_cpu);
633	<	if (main_cpu->gpr(1) != KernelDataAddr) {
633	>	if (gpr(1) != KernelDataAddr) {
634		// Prepare for 68k interrupt level 1
635		WriteMacInt16(tswap32(kernel_data->v[0x67c >> 2]), 1);
636		WriteMacInt32(tswap32(kernel_data->v[0x658 >> 2]) + 0xdc,
#	Line 671 | Line 641 | static void HandleInterrupt(void)
641		DisableInterrupt();
642		cpu_push(interrupt_cpu);
643		if (ROMType == ROMTYPE_NEWWORLD)
644	<	current_cpu->interrupt(ROM_BASE + 0x312b1c, main_cpu);
644	>	current_cpu->interrupt(ROM_BASE + 0x312b1c);
645		else
646	<	current_cpu->interrupt(ROM_BASE + 0x312a3c, main_cpu);
646	>	current_cpu->interrupt(ROM_BASE + 0x312a3c);
647		cpu_pop();
648		}
649		break;
#	Line 748 | Line 718 | const uint32 NativeOpTable[NATIVE_OP_MAX
718		POWERPC_NATIVE_OP_INIT(1, NATIVE_R_GET_RESOURCE),
719		POWERPC_NATIVE_OP_INIT(0, NATIVE_DISABLE_INTERRUPT),
720		POWERPC_NATIVE_OP_INIT(0, NATIVE_ENABLE_INTERRUPT),
721	+	POWERPC_NATIVE_OP_INIT(1, NATIVE_MAKE_EXECUTABLE),
722		};
723
724		static void get_resource(void);
#	Line 815 | Line 786 | static void NativeOp(int selector)
786		case NATIVE_ENABLE_INTERRUPT:
787		EnableInterrupt();
788		break;
789	+	case NATIVE_MAKE_EXECUTABLE:
790	+	MakeExecutable(0, (void *)GPR(4), GPR(5));
791	+	break;
792		default:
793		printf("FATAL: NATIVE_OP called with bogus selector %d\n", selector);
794		QuitEmulator();
#	Line 854 | Line 828 | void Execute68k(uint32 pc, M68kRegisters
828
829		void Execute68kTrap(uint16 trap, M68kRegisters *r)
830		{
831	<	uint16 proc[2] = {trap, M68K_RTS};
831	>	uint16 proc[2];
832	>	proc[0] = htons(trap);
833	>	proc[1] = htons(M68K_RTS);
834		Execute68k((uint32)proc, r);
835		}
836
#	Line 910 | Line 886 | uint32 call_macos7(uint32 tvect, uint32
886		}
887
888		/*
913	–	*  Atomic operations
914	–	*/
915	–
916	–	int atomic_add(int *var, int v)
917	–	{
918	–	int ret = *var;
919	–	*var += v;
920	–	return ret;
921	–	}
922	–
923	–	int atomic_and(int *var, int v)
924	–	{
925	–	int ret = *var;
926	–	*var &= v;
927	–	return ret;
928	–	}
929	–
930	–	int atomic_or(int *var, int v)
931	–	{
932	–	int ret = *var;
933	–	*var |= v;
934	–	return ret;
935	–	}
936	–
937	–	/*
889		*  Resource Manager thunks
890		*/
891

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