ViewVC Help

View File | Revision Log | Show Annotations | Revision Graph | Root Listing

root/cebix/SheepShaver/src/kpx_cpu/sheepshaver_glue.cpp

Comparing SheepShaver/src/kpx_cpu/sheepshaver_glue.cpp (file contents):
Revision 1.4 by gbeauche, 2003-09-29T15:46:09Z vs.
Revision 1.10 by gbeauche, 2003-10-26T13:59:03Z

#	Line 44 | Line 44
44		#include "mon_disass.h"
45		#endif
46
47	<	#define DEBUG 1
47	>	#define DEBUG 0
48		#include "debug.h"
49
50		static void enter_mon(void)
#	Line 57 | Line 57 | static void enter_mon(void)
57		}
58
59		// Enable multicore (main/interrupts) cpu emulation?
60	<	#define MULTICORE_CPU 0
60	>	#define MULTICORE_CPU (ASYNC_IRQ ? 1 : 0)
61
62		// Enable Execute68k() safety checks?
63		#define SAFE_EXEC_68K 1
#	Line 89 | Line 89 | class sheepshaver_cpu
89
90		public:
91
92	<	sheepshaver_cpu()
93	<	: powerpc_cpu()
94	<	{ init_decoder(); }
92	>	// Constructor
93	>	sheepshaver_cpu();
94
95		// Condition Register accessors
96		uint32 get_cr() const           { return cr().get(); }
97		void set_cr(uint32 v)           { cr().set(v); }
98
99		// Execution loop
100	<	void execute(uint32 pc);
100	>	void execute(uint32 entry, bool enable_cache = false);
101
102		// Execute 68k routine
103		void execute_68k(uint32 entry, M68kRegisters *r);
#	Line 114 | Line 113 | public:
113
114		// Handle MacOS interrupt
115		void interrupt(uint32 entry);
116	+	void handle_interrupt();
117
118		// spcflags for interrupts handling
119		static uint32 spcflags;
#	Line 131 | Line 131 | public:
131		uint32 sheepshaver_cpu::spcflags = 0;
132		lazy_allocator< sheepshaver_cpu > allocator_helper< sheepshaver_cpu, lazy_allocator >::allocator;
133
134	+	sheepshaver_cpu::sheepshaver_cpu()
135	+	: powerpc_cpu()
136	+	{
137	+	init_decoder();
138	+	}
139	+
140		void sheepshaver_cpu::init_decoder()
141		{
142		#ifndef PPC_NO_STATIC_II_INDEX_TABLE
#	Line 144 | Line 150 | void sheepshaver_cpu::init_decoder()
150		{ "sheep",
151		(execute_fn)&sheepshaver_cpu::execute_sheep,
152		NULL,
153	<	D_form, 6, 0, CFLOW_TRAP
153	>	D_form, 6, 0, CFLOW_JUMP | CFLOW_TRAP
154		}
155		};
156
#	Line 181 | Line 187 | void sheepshaver_cpu::execute_sheep(uint
187		case 0:         // EMUL_RETURN
188		QuitEmulator();
189		break;
190	<
190	>
191		case 1:         // EXEC_RETURN
192		throw sheepshaver_exec_return();
193		break;
#	Line 216 | Line 222 | void sheepshaver_cpu::execute_sheep(uint
222		}
223		}
224
219	–	// Checks for pending interrupts
220	–	struct execute_nothing {
221	–	static inline void execute(powerpc_cpu *) { }
222	–	};
223	–
224	–	struct execute_spcflags_check {
225	–	static inline void execute(powerpc_cpu *cpu) {
226	–	#if !ASYNC_IRQ
227	–	if (SPCFLAGS_TEST(SPCFLAG_ALL_BUT_EXEC_RETURN)) {
228	–	if (SPCFLAGS_TEST( SPCFLAG_ENTER_MON )) {
229	–	SPCFLAGS_CLEAR( SPCFLAG_ENTER_MON );
230	–	enter_mon();
231	–	}
232	–	if (SPCFLAGS_TEST( SPCFLAG_DOINT )) {
233	–	SPCFLAGS_CLEAR( SPCFLAG_DOINT );
234	–	HandleInterrupt();
235	–	}
236	–	if (SPCFLAGS_TEST( SPCFLAG_INT )) {
237	–	SPCFLAGS_CLEAR( SPCFLAG_INT );
238	–	SPCFLAGS_SET( SPCFLAG_DOINT );
239	–	}
240	–	}
241	–	#endif
242	–	}
243	–	};
244	–
225		// Execution loop
226	<	void sheepshaver_cpu::execute(uint32 entry)
226	>	void sheepshaver_cpu::execute(uint32 entry, bool enable_cache)
227		{
228		try {
229	<	pc() = entry;
250	<	powerpc_cpu::do_execute<execute_nothing, execute_spcflags_check>();
229	>	powerpc_cpu::execute(entry, enable_cache);
230		}
231		catch (sheepshaver_exec_return const &) {
232		// Nothing, simply return
#	Line 273 | Line 252 | void sheepshaver_cpu::interrupt(uint32 e
252		gpr(1) = SheepStack1Base - 64;
253
254		// Build trampoline to return from interrupt
255	<	uint32 trampoline[] = { POWERPC_EMUL_OP | 1 };
255	>	uint32 trampoline[] = { htonl(POWERPC_EMUL_OP | 1) };
256
257		// Prepare registers for nanokernel interrupt routine
258	<	kernel_data->v[0x004 >> 2] = gpr(1);
259	<	kernel_data->v[0x018 >> 2] = gpr(6);
258	>	kernel_data->v[0x004 >> 2] = htonl(gpr(1));
259	>	kernel_data->v[0x018 >> 2] = htonl(gpr(6));
260
261	<	gpr(6) = kernel_data->v[0x65c >> 2];
261	>	gpr(6) = ntohl(kernel_data->v[0x65c >> 2]);
262		assert(gpr(6) != 0);
263		WriteMacInt32(gpr(6) + 0x13c, gpr(7));
264		WriteMacInt32(gpr(6) + 0x144, gpr(8));
#	Line 290 | Line 269 | void sheepshaver_cpu::interrupt(uint32 e
269		WriteMacInt32(gpr(6) + 0x16c, gpr(13));
270
271		gpr(1)  = KernelDataAddr;
272	<	gpr(7)  = kernel_data->v[0x660 >> 2];
272	>	gpr(7)  = ntohl(kernel_data->v[0x660 >> 2]);
273		gpr(8)  = 0;
274		gpr(10) = (uint32)trampoline;
275		gpr(12) = (uint32)trampoline;
276	<	gpr(13) = cr().get();
276	>	gpr(13) = get_cr();
277
278		// rlwimi. r7,r7,8,0,0
279		uint32 result = op_ppc_rlwimi::apply(gpr(7), 8, 0x80000000, gpr(7));
#	Line 302 | Line 281 | void sheepshaver_cpu::interrupt(uint32 e
281		gpr(7) = result;
282
283		gpr(11) = 0xf072; // MSR (SRR1)
284	<	cr().set((gpr(11) & 0x0fff0000) | (cr().get() & ~0x0fff0000));
284	>	cr().set((gpr(11) & 0x0fff0000) | (get_cr() & ~0x0fff0000));
285
286		// Enter nanokernel
287		execute(entry);
#	Line 328 | Line 307 | void sheepshaver_cpu::execute_68k(uint32
307		uint32 saved_pc = pc();
308		uint32 saved_lr = lr();
309		uint32 saved_ctr= ctr();
310	+	uint32 saved_cr = get_cr();
311
312		// Create MacOS stack frame
313	+	// FIXME: make sure MacOS doesn't expect PPC registers to live on top
314		uint32 sp = gpr(1);
315	<	gpr(1) -= 56 + 19*4 + 18*8;
315	>	gpr(1) -= 56;
316		WriteMacInt32(gpr(1), sp);
317
318		// Save PowerPC registers
319	<	memcpy(Mac2HostAddr(gpr(1)+56), &gpr(13), sizeof(uint32)*(32-13));
319	>	uint32 saved_GPRs[19];
320	>	memcpy(&saved_GPRs[0], &gpr(13), sizeof(uint32)*(32-13));
321		#if SAVE_FP_EXEC_68K
322	<	memcpy(Mac2HostAddr(gpr(1)+56+19*4), &fpr(14), sizeof(double)*(32-14));
322	>	double saved_FPRs[18];
323	>	memcpy(&saved_FPRs[0], &fpr(14), sizeof(double)*(32-14));
324		#endif
325
326		// Setup registers for 68k emulator
#	Line 351 | Line 334 | void sheepshaver_cpu::execute_68k(uint32
334		gpr(25) = ReadMacInt32(XLM_68K_R25);            // MSB of SR
335		gpr(26) = 0;
336		gpr(28) = 0;                                                            // VBR
337	<	gpr(29) = kernel_data->ed.v[0x74 >> 2];         // Pointer to opcode table
338	<	gpr(30) = kernel_data->ed.v[0x78 >> 2];         // Address of emulator
337	>	gpr(29) = ntohl(kernel_data->ed.v[0x74 >> 2]);          // Pointer to opcode table
338	>	gpr(30) = ntohl(kernel_data->ed.v[0x78 >> 2]);          // Address of emulator
339		gpr(31) = KernelDataAddr + 0x1000;
340
341		// Push return address (points to EXEC_RETURN opcode) on stack
#	Line 384 | Line 367 | void sheepshaver_cpu::execute_68k(uint32
367		r->a[i] = gpr(16 + i);
368
369		// Restore PowerPC registers
370	<	memcpy(&gpr(13), Mac2HostAddr(gpr(1)+56), sizeof(uint32)*(32-13));
370	>	memcpy(&gpr(13), &saved_GPRs[0], sizeof(uint32)*(32-13));
371		#if SAVE_FP_EXEC_68K
372	<	memcpy(&fpr(14), Mac2HostAddr(gpr(1)+56+19*4), sizeof(double)*(32-14));
372	>	memcpy(&fpr(14), &saved_FPRs[0], sizeof(double)*(32-14));
373		#endif
374
375		// Cleanup stack
376	<	gpr(1) += 56 + 19*4 + 18*8;
376	>	gpr(1) += 56;
377
378		// Restore program counters and branch registers
379		pc() = saved_pc;
380		lr() = saved_lr;
381		ctr()= saved_ctr;
382	+	set_cr(saved_cr);
383		}
384
385		// Call MacOS PPC code
#	Line 407 | Line 391 | uint32 sheepshaver_cpu::execute_macos_co
391		uint32 saved_ctr= ctr();
392
393		// Build trampoline with EXEC_RETURN
394	<	uint32 trampoline[] = { POWERPC_EMUL_OP | 1 };
394	>	uint32 trampoline[] = { htonl(POWERPC_EMUL_OP | 1) };
395		lr() = (uint32)trampoline;
396
397		gpr(1) -= 64;                                                           // Create stack frame
#	Line 447 | Line 431 | inline void sheepshaver_cpu::execute_ppc
431		{
432		// Save branch registers
433		uint32 saved_lr = lr();
450	–	uint32 saved_ctr= ctr();
451	–
452	–	const uint32 trampoline[] = { POWERPC_EMUL_OP | 1 };
434
435	+	const uint32 trampoline[] = { htonl(POWERPC_EMUL_OP | 1) };
436		lr() = (uint32)trampoline;
437	<	ctr()= entry;
437	>
438		execute(entry);
439
440		// Restore branch registers
441		lr() = saved_lr;
460	–	ctr()= saved_ctr;
442		}
443
444		// Resource Manager thunk
445	<	extern "C" void check_load_invoc(uint32 type, int16 id, uint16 **h);
445	>	extern "C" void check_load_invoc(uint32 type, int16 id, uint32 h);
446
447		inline void sheepshaver_cpu::get_resource(uint32 old_get_resource)
448		{
#	Line 473 | Line 454 | inline void sheepshaver_cpu::get_resourc
454
455		// Call old routine
456		execute_ppc(old_get_resource);
476	–	uint16 **handle = (uint16 **)gpr(3);
457
458		// Call CheckLoad()
459	+	uint32 handle = gpr(3);
460		check_load_invoc(type, id, handle);
461	<	gpr(3) = (uint32)handle;
461	>	gpr(3) = handle;
462
463		// Cleanup stack
464		gpr(1) += 56;
#	Line 492 | Line 473 | static sheepshaver_cpu *main_cpu = NULL;
473		static sheepshaver_cpu *interrupt_cpu = NULL;   // CPU emulator to handle interrupts
474		static sheepshaver_cpu *current_cpu = NULL;             // Current CPU emulator context
475
476	+	void FlushCodeCache(uintptr start, uintptr end)
477	+	{
478	+	D(bug("FlushCodeCache(%08x, %08x)\n", start, end));
479	+	main_cpu->invalidate_cache_range(start, end);
480	+	#if MULTICORE_CPU
481	+	interrupt_cpu->invalidate_cache_range(start, end);
482	+	#endif
483	+	}
484	+
485		static inline void cpu_push(sheepshaver_cpu *new_cpu)
486		{
487		#if MULTICORE_CPU
#	Line 585 | Line 575 | void init_emul_ppc(void)
575		void emul_ppc(uint32 entry)
576		{
577		current_cpu = main_cpu;
578	+	#if DEBUG
579		current_cpu->start_log();
580	<	current_cpu->execute(entry);
580	>	#endif
581	>	// start emulation loop and enable code translation or caching
582	>	current_cpu->execute(entry, true);
583		}
584
585		/*
586		*  Handle PowerPC interrupt
587		*/
588
596	–	// Atomic operations
597	–	extern int atomic_add(int *var, int v);
598	–	extern int atomic_and(int *var, int v);
599	–	extern int atomic_or(int *var, int v);
600	–
589		#if !ASYNC_IRQ
590		void TriggerInterrupt(void)
591		{
592		#if 0
593		WriteMacInt32(0x16a, ReadMacInt32(0x16a) + 1);
594		#else
595	<	SPCFLAGS_SET( SPCFLAG_INT );
595	>	// Trigger interrupt to main cpu only
596	>	if (main_cpu)
597	>	main_cpu->trigger_interrupt();
598		#endif
599		}
600		#endif
601
602	<	void HandleInterrupt(void)
602	>	void sheepshaver_cpu::handle_interrupt(void)
603		{
604		// Do nothing if interrupts are disabled
605		if (int32(ReadMacInt32(XLM_IRQ_NEST)) > 0)
#	Line 628 | Line 618 | void HandleInterrupt(void)
618		// 68k emulator active, trigger 68k interrupt level 1
619		assert(current_cpu == main_cpu);
620		WriteMacInt16(tswap32(kernel_data->v[0x67c >> 2]), 1);
621	<	main_cpu->set_cr(main_cpu->get_cr() | tswap32(kernel_data->v[0x674 >> 2]));
621	>	set_cr(get_cr() | tswap32(kernel_data->v[0x674 >> 2]));
622		break;
623
624		#if INTERRUPTS_IN_NATIVE_MODE
625		case MODE_NATIVE:
626		// 68k emulator inactive, in nanokernel?
627		assert(current_cpu == main_cpu);
628	<	if (main_cpu->gpr(1) != KernelDataAddr) {
628	>	if (gpr(1) != KernelDataAddr) {
629		// Prepare for 68k interrupt level 1
630		WriteMacInt16(tswap32(kernel_data->v[0x67c >> 2]), 1);
631		WriteMacInt32(tswap32(kernel_data->v[0x658 >> 2]) + 0xdc,
#	Line 723 | Line 713 | const uint32 NativeOpTable[NATIVE_OP_MAX
713		POWERPC_NATIVE_OP_INIT(1, NATIVE_R_GET_RESOURCE),
714		POWERPC_NATIVE_OP_INIT(0, NATIVE_DISABLE_INTERRUPT),
715		POWERPC_NATIVE_OP_INIT(0, NATIVE_ENABLE_INTERRUPT),
716	+	POWERPC_NATIVE_OP_INIT(1, NATIVE_MAKE_EXECUTABLE),
717		};
718
719		static void get_resource(void);
#	Line 790 | Line 781 | static void NativeOp(int selector)
781		case NATIVE_ENABLE_INTERRUPT:
782		EnableInterrupt();
783		break;
784	+	case NATIVE_MAKE_EXECUTABLE:
785	+	MakeExecutable(0, (void *)GPR(4), GPR(5));
786	+	break;
787		default:
788		printf("FATAL: NATIVE_OP called with bogus selector %d\n", selector);
789		QuitEmulator();
#	Line 829 | Line 823 | void Execute68k(uint32 pc, M68kRegisters
823
824		void Execute68kTrap(uint16 trap, M68kRegisters *r)
825		{
826	<	uint16 proc[2] = {trap, M68K_RTS};
826	>	uint16 proc[2];
827	>	proc[0] = htons(trap);
828	>	proc[1] = htons(M68K_RTS);
829		Execute68k((uint32)proc, r);
830		}
831
#	Line 885 | Line 881 | uint32 call_macos7(uint32 tvect, uint32
881		}
882
883		/*
888	–	*  Atomic operations
889	–	*/
890	–
891	–	int atomic_add(int *var, int v)
892	–	{
893	–	int ret = *var;
894	–	*var += v;
895	–	return ret;
896	–	}
897	–
898	–	int atomic_and(int *var, int v)
899	–	{
900	–	int ret = *var;
901	–	*var &= v;
902	–	return ret;
903	–	}
904	–
905	–	int atomic_or(int *var, int v)
906	–	{
907	–	int ret = *var;
908	–	*var |= v;
909	–	return ret;
910	–	}
911	–
912	–	/*
884		*  Resource Manager thunks
885		*/
886

Diff Legend

–	Removed lines
+	Added lines
<	Changed lines
>	Changed lines