177 |
|
static inline uint64 tswap64(uint64 x) { return bswap_64(x); } |
178 |
|
#endif |
179 |
|
|
180 |
+ |
// spin locks |
181 |
+ |
#ifdef __GNUC__ |
182 |
+ |
|
183 |
+ |
#ifdef __powerpc__ |
184 |
+ |
#define HAVE_TEST_AND_SET 1 |
185 |
+ |
static inline int testandset(int *p) |
186 |
+ |
{ |
187 |
+ |
int ret; |
188 |
+ |
__asm__ __volatile__("0: lwarx %0,0,%1 ;" |
189 |
+ |
" xor. %0,%3,%0;" |
190 |
+ |
" bne 1f;" |
191 |
+ |
" stwcx. %2,0,%1;" |
192 |
+ |
" bne- 0b;" |
193 |
+ |
"1: " |
194 |
+ |
: "=&r" (ret) |
195 |
+ |
: "r" (p), "r" (1), "r" (0) |
196 |
+ |
: "cr0", "memory"); |
197 |
+ |
return ret; |
198 |
+ |
} |
199 |
+ |
#endif |
200 |
+ |
|
201 |
+ |
#ifdef __i386__ |
202 |
+ |
#define HAVE_TEST_AND_SET 1 |
203 |
+ |
static inline int testandset(int *p) |
204 |
+ |
{ |
205 |
+ |
char ret; |
206 |
+ |
long int readval; |
207 |
+ |
|
208 |
+ |
__asm__ __volatile__("lock; cmpxchgl %3, %1; sete %0" |
209 |
+ |
: "=q" (ret), "=m" (*p), "=a" (readval) |
210 |
+ |
: "r" (1), "m" (*p), "a" (0) |
211 |
+ |
: "memory"); |
212 |
+ |
return ret; |
213 |
+ |
} |
214 |
+ |
#endif |
215 |
+ |
|
216 |
+ |
#ifdef __s390__ |
217 |
+ |
#define HAVE_TEST_AND_SET 1 |
218 |
+ |
static inline int testandset(int *p) |
219 |
+ |
{ |
220 |
+ |
int ret; |
221 |
+ |
|
222 |
+ |
__asm__ __volatile__("0: cs %0,%1,0(%2)\n" |
223 |
+ |
" jl 0b" |
224 |
+ |
: "=&d" (ret) |
225 |
+ |
: "r" (1), "a" (p), "0" (*p) |
226 |
+ |
: "cc", "memory" ); |
227 |
+ |
return ret; |
228 |
+ |
} |
229 |
+ |
#endif |
230 |
+ |
|
231 |
+ |
#ifdef __alpha__ |
232 |
+ |
#define HAVE_TEST_AND_SET 1 |
233 |
+ |
static inline int testandset(int *p) |
234 |
+ |
{ |
235 |
+ |
int ret; |
236 |
+ |
unsigned long one; |
237 |
+ |
|
238 |
+ |
__asm__ __volatile__("0: mov 1,%2\n" |
239 |
+ |
" ldl_l %0,%1\n" |
240 |
+ |
" stl_c %2,%1\n" |
241 |
+ |
" beq %2,1f\n" |
242 |
+ |
".subsection 2\n" |
243 |
+ |
"1: br 0b\n" |
244 |
+ |
".previous" |
245 |
+ |
: "=r" (ret), "=m" (*p), "=r" (one) |
246 |
+ |
: "m" (*p)); |
247 |
+ |
return ret; |
248 |
+ |
} |
249 |
+ |
#endif |
250 |
+ |
|
251 |
+ |
#ifdef __sparc__ |
252 |
+ |
#define HAVE_TEST_AND_SET 1 |
253 |
+ |
static inline int testandset(int *p) |
254 |
+ |
{ |
255 |
+ |
int ret; |
256 |
+ |
|
257 |
+ |
__asm__ __volatile__("ldstub [%1], %0" |
258 |
+ |
: "=r" (ret) |
259 |
+ |
: "r" (p) |
260 |
+ |
: "memory"); |
261 |
+ |
|
262 |
+ |
return (ret ? 1 : 0); |
263 |
+ |
} |
264 |
+ |
#endif |
265 |
+ |
|
266 |
+ |
#ifdef __arm__ |
267 |
+ |
#define HAVE_TEST_AND_SET 1 |
268 |
+ |
static inline int testandset(int *p) |
269 |
+ |
{ |
270 |
+ |
register unsigned int ret; |
271 |
+ |
__asm__ __volatile__("swp %0, %1, [%2]" |
272 |
+ |
: "=r"(ret) |
273 |
+ |
: "0"(1), "r"(p)); |
274 |
+ |
|
275 |
+ |
return ret; |
276 |
+ |
} |
277 |
+ |
#endif |
278 |
+ |
|
279 |
+ |
#endif /* __GNUC__ */ |
280 |
+ |
|
281 |
+ |
#if HAVE_TEST_AND_SET |
282 |
+ |
#define HAVE_SPINLOCKS 1 |
283 |
+ |
typedef int spinlock_t; |
284 |
+ |
|
285 |
+ |
const spinlock_t SPIN_LOCK_UNLOCKED = 0; |
286 |
+ |
|
287 |
+ |
static inline void spin_lock(spinlock_t *lock) |
288 |
+ |
{ |
289 |
+ |
while (testandset(lock)); |
290 |
+ |
} |
291 |
+ |
|
292 |
+ |
static inline void spin_unlock(spinlock_t *lock) |
293 |
+ |
{ |
294 |
+ |
*lock = 0; |
295 |
+ |
} |
296 |
+ |
|
297 |
+ |
static inline int spin_trylock(spinlock_t *lock) |
298 |
+ |
{ |
299 |
+ |
return !testandset(lock); |
300 |
+ |
} |
301 |
+ |
#endif |
302 |
+ |
|
303 |
|
// Time data type for Time Manager emulation |
304 |
|
#ifdef HAVE_CLOCK_GETTIME |
305 |
|
typedef struct timespec tm_time_t; |