68 |
|
#define POWERPC_ROM 1 |
69 |
|
|
70 |
|
#if EMULATED_PPC |
71 |
+ |
// Handle interrupts asynchronously? |
72 |
+ |
#define ASYNC_IRQ 0 |
73 |
|
// Mac ROM is write protected when banked memory is used |
74 |
|
#if REAL_ADDRESSING || DIRECT_ADDRESSING |
75 |
|
# define ROM_IS_WRITE_PROTECTED 0 |
77 |
|
#else |
78 |
|
# define ROM_IS_WRITE_PROTECTED 1 |
79 |
|
#endif |
80 |
+ |
// Configure PowerPC emulator |
81 |
+ |
#define PPC_CHECK_INTERRUPTS (ASYNC_IRQ ? 0 : 1) |
82 |
+ |
#define PPC_DECODE_CACHE 1 |
83 |
+ |
#define PPC_FLIGHT_RECORDER 1 |
84 |
+ |
#define PPC_PROFILE_COMPILE_TIME 0 |
85 |
+ |
#define PPC_PROFILE_GENERIC_CALLS 0 |
86 |
+ |
#define KPX_MAX_CPUS 1 |
87 |
|
#else |
88 |
|
// Mac ROM is write protected |
89 |
|
#define ROM_IS_WRITE_PROTECTED 1 |
134 |
|
#error "Unsupported size of pointer" |
135 |
|
#endif |
136 |
|
|
137 |
< |
// Helper functions to byteswap data |
137 |
> |
/** |
138 |
> |
* Helper functions to byteswap data |
139 |
> |
**/ |
140 |
> |
|
141 |
> |
#if defined(__GNUC__) |
142 |
> |
#if defined(__x86_64__) |
143 |
> |
// Linux/AMD64 currently has no asm optimized bswap_32() in <byteswap.h> |
144 |
> |
#define opt_bswap_32 do_opt_bswap_32 |
145 |
> |
static inline uint32 do_opt_bswap_32(uint32 x) |
146 |
> |
{ |
147 |
> |
uint32 v; |
148 |
> |
__asm__ __volatile__ ("bswap %0" : "=r" (v) : "0" (x)); |
149 |
> |
return v; |
150 |
> |
} |
151 |
> |
#endif |
152 |
> |
#endif |
153 |
> |
|
154 |
|
#ifdef HAVE_BYTESWAP_H |
155 |
|
#include <byteswap.h> |
156 |
|
#endif |
157 |
|
|
158 |
+ |
#ifdef opt_bswap_16 |
159 |
+ |
#undef bswap_16 |
160 |
+ |
#define bswap_16 opt_bswap_16 |
161 |
+ |
#endif |
162 |
|
#ifndef bswap_16 |
163 |
|
#define bswap_16 generic_bswap_16 |
164 |
|
#endif |
168 |
|
return ((x & 0xff) << 8) | ((x >> 8) & 0xff); |
169 |
|
} |
170 |
|
|
171 |
+ |
#ifdef opt_bswap_32 |
172 |
+ |
#undef bswap_32 |
173 |
+ |
#define bswap_32 opt_bswap_32 |
174 |
+ |
#endif |
175 |
|
#ifndef bswap_32 |
176 |
|
#define bswap_32 generic_bswap_32 |
177 |
|
#endif |
184 |
|
((x & 0x000000ff) << 24) ); |
185 |
|
} |
186 |
|
|
187 |
+ |
#ifdef opt_bswap_64 |
188 |
+ |
#undef bswap_64 |
189 |
+ |
#define bswap_64 opt_bswap_64 |
190 |
+ |
#endif |
191 |
|
#ifndef bswap_64 |
192 |
|
#define bswap_64 generic_bswap_64 |
193 |
|
#endif |
219 |
|
|
220 |
|
#ifdef __powerpc__ |
221 |
|
#define HAVE_TEST_AND_SET 1 |
222 |
< |
static inline int testandset(int *p) |
222 |
> |
static inline int testandset(volatile int *p) |
223 |
|
{ |
224 |
|
int ret; |
225 |
|
__asm__ __volatile__("0: lwarx %0,0,%1 ;" |
237 |
|
|
238 |
|
#ifdef __i386__ |
239 |
|
#define HAVE_TEST_AND_SET 1 |
240 |
< |
static inline int testandset(int *p) |
240 |
> |
static inline int testandset(volatile int *p) |
241 |
|
{ |
242 |
< |
char ret; |
242 |
> |
int ret; |
243 |
|
long int readval; |
244 |
< |
|
245 |
< |
__asm__ __volatile__("lock; cmpxchgl %3, %1; sete %0" |
246 |
< |
: "=q" (ret), "=m" (*p), "=a" (readval) |
247 |
< |
: "r" (1), "m" (*p), "a" (0) |
244 |
> |
/* Note: the "xchg" instruction does not need a "lock" prefix */ |
245 |
> |
__asm__ __volatile__("xchgl %0, %1" |
246 |
> |
: "=r" (ret), "=m" (*p), "=a" (readval) |
247 |
> |
: "0" (1), "m" (*p) |
248 |
|
: "memory"); |
249 |
|
return ret; |
250 |
|
} |
252 |
|
|
253 |
|
#ifdef __s390__ |
254 |
|
#define HAVE_TEST_AND_SET 1 |
255 |
< |
static inline int testandset(int *p) |
255 |
> |
static inline int testandset(volatile int *p) |
256 |
|
{ |
257 |
|
int ret; |
258 |
|
|
267 |
|
|
268 |
|
#ifdef __alpha__ |
269 |
|
#define HAVE_TEST_AND_SET 1 |
270 |
< |
static inline int testandset(int *p) |
270 |
> |
static inline int testandset(volatile int *p) |
271 |
|
{ |
272 |
|
int ret; |
273 |
|
unsigned long one; |
287 |
|
|
288 |
|
#ifdef __sparc__ |
289 |
|
#define HAVE_TEST_AND_SET 1 |
290 |
< |
static inline int testandset(int *p) |
290 |
> |
static inline int testandset(volatile int *p) |
291 |
|
{ |
292 |
|
int ret; |
293 |
|
|
302 |
|
|
303 |
|
#ifdef __arm__ |
304 |
|
#define HAVE_TEST_AND_SET 1 |
305 |
< |
static inline int testandset(int *p) |
305 |
> |
static inline int testandset(volatile int *p) |
306 |
|
{ |
307 |
|
register unsigned int ret; |
308 |
|
__asm__ __volatile__("swp %0, %1, [%2]" |
317 |
|
|
318 |
|
#if HAVE_TEST_AND_SET |
319 |
|
#define HAVE_SPINLOCKS 1 |
320 |
< |
typedef int spinlock_t; |
320 |
> |
typedef volatile int spinlock_t; |
321 |
|
|
322 |
< |
const spinlock_t SPIN_LOCK_UNLOCKED = 0; |
322 |
> |
static const spinlock_t SPIN_LOCK_UNLOCKED = 0; |
323 |
|
|
324 |
|
static inline void spin_lock(spinlock_t *lock) |
325 |
|
{ |
344 |
|
typedef struct timeval tm_time_t; |
345 |
|
#endif |
346 |
|
|
347 |
+ |
// Timing functions |
348 |
+ |
extern uint64 GetTicks_usec(void); |
349 |
+ |
extern void Delay_usec(uint32 usec); |
350 |
+ |
|
351 |
|
// Setup pthread attributes |
352 |
|
extern void Set_pthread_attr(pthread_attr_t *attr, int priority); |
353 |
|
|
359 |
|
uint8 alpha; |
360 |
|
} rgb_color; |
361 |
|
|
362 |
+ |
// X11 display fast locks |
363 |
+ |
#ifdef HAVE_SPINLOCKS |
364 |
+ |
#define X11_LOCK_TYPE spinlock_t |
365 |
+ |
#define X11_LOCK_INIT SPIN_LOCK_UNLOCKED |
366 |
+ |
#define XDisplayLock() spin_lock(&x_display_lock) |
367 |
+ |
#define XDisplayUnlock() spin_unlock(&x_display_lock) |
368 |
+ |
#elif defined(HAVE_PTHREADS) |
369 |
+ |
#define X11_LOCK_TYPE pthread_mutex_t |
370 |
+ |
#define X11_LOCK_INIT PTHREAD_MUTEX_INITIALIZER |
371 |
+ |
#define XDisplayLock() pthread_mutex_lock(&x_display_lock); |
372 |
+ |
#define XDisplayUnlock() pthread_mutex_unlock(&x_display_lock); |
373 |
+ |
#else |
374 |
+ |
#define XDisplayLock() |
375 |
+ |
#define XDisplayUnlock() |
376 |
+ |
#endif |
377 |
+ |
#ifdef X11_LOCK_TYPE |
378 |
+ |
extern X11_LOCK_TYPE x_display_lock; |
379 |
+ |
#endif |
380 |
+ |
|
381 |
|
// Macro for calling MacOS routines |
382 |
|
#define CallMacOS(type, tvect) call_macos((uint32)tvect) |
383 |
|
#define CallMacOS1(type, tvect, arg1) call_macos1((uint32)tvect, (uint32)arg1) |