59 |
|
# endif |
60 |
|
#endif |
61 |
|
|
62 |
< |
// Are we using a PPC emulator or the real thing? |
63 |
< |
#ifdef __powerpc__ |
64 |
< |
#define EMULATED_PPC 0 |
65 |
< |
#else |
66 |
< |
#define EMULATED_PPC 1 |
67 |
< |
#endif |
62 |
> |
// Define for external components |
63 |
> |
#define SHEEPSHAVER 1 |
64 |
> |
|
65 |
> |
// Mac and host address space are the same |
66 |
> |
#define REAL_ADDRESSING 1 |
67 |
|
|
68 |
|
#define POWERPC_ROM 1 |
69 |
|
|
70 |
+ |
#if EMULATED_PPC |
71 |
+ |
// Handle interrupts asynchronously? |
72 |
+ |
#define ASYNC_IRQ 0 |
73 |
+ |
// Mac ROM is write protected when banked memory is used |
74 |
+ |
#if REAL_ADDRESSING || DIRECT_ADDRESSING |
75 |
+ |
# define ROM_IS_WRITE_PROTECTED 0 |
76 |
+ |
# define USE_SCRATCHMEM_SUBTERFUGE 1 |
77 |
+ |
#else |
78 |
+ |
# define ROM_IS_WRITE_PROTECTED 1 |
79 |
+ |
#endif |
80 |
+ |
// Configure PowerPC emulator |
81 |
+ |
#define PPC_CHECK_INTERRUPTS (ASYNC_IRQ ? 0 : 1) |
82 |
+ |
#define PPC_NO_LAZY_PC_UPDATE 1 |
83 |
+ |
//#define PPC_NO_DECODE_CACHE 1 |
84 |
+ |
#define PPC_FLIGHT_RECORDER 1 |
85 |
+ |
#else |
86 |
+ |
// Mac ROM is write protected |
87 |
+ |
#define ROM_IS_WRITE_PROTECTED 1 |
88 |
+ |
#define USE_SCRATCHMEM_SUBTERFUGE 0 |
89 |
+ |
#endif |
90 |
+ |
|
91 |
|
// Data types |
92 |
|
typedef unsigned char uint8; |
93 |
|
typedef signed char int8; |
132 |
|
#error "Unsupported size of pointer" |
133 |
|
#endif |
134 |
|
|
135 |
+ |
// Helper functions to byteswap data |
136 |
+ |
#ifdef HAVE_BYTESWAP_H |
137 |
+ |
#include <byteswap.h> |
138 |
+ |
#endif |
139 |
+ |
|
140 |
+ |
#ifndef bswap_16 |
141 |
+ |
#define bswap_16 generic_bswap_16 |
142 |
+ |
#endif |
143 |
+ |
|
144 |
+ |
static inline uint16 generic_bswap_16(uint16 x) |
145 |
+ |
{ |
146 |
+ |
return ((x & 0xff) << 8) | ((x >> 8) & 0xff); |
147 |
+ |
} |
148 |
+ |
|
149 |
+ |
#ifndef bswap_32 |
150 |
+ |
#define bswap_32 generic_bswap_32 |
151 |
+ |
#endif |
152 |
+ |
|
153 |
+ |
static inline uint32 generic_bswap_32(uint32 x) |
154 |
+ |
{ |
155 |
+ |
return (((x & 0xff000000) >> 24) | |
156 |
+ |
((x & 0x00ff0000) >> 8) | |
157 |
+ |
((x & 0x0000ff00) << 8) | |
158 |
+ |
((x & 0x000000ff) << 24) ); |
159 |
+ |
} |
160 |
+ |
|
161 |
+ |
#ifndef bswap_64 |
162 |
+ |
#define bswap_64 generic_bswap_64 |
163 |
+ |
#endif |
164 |
+ |
|
165 |
+ |
static inline uint64 generic_bswap_64(uint64 x) |
166 |
+ |
{ |
167 |
+ |
return (((x & UVAL64(0xff00000000000000)) >> 56) | |
168 |
+ |
((x & UVAL64(0x00ff000000000000)) >> 40) | |
169 |
+ |
((x & UVAL64(0x0000ff0000000000)) >> 24) | |
170 |
+ |
((x & UVAL64(0x000000ff00000000)) >> 8) | |
171 |
+ |
((x & UVAL64(0x00000000ff000000)) << 8) | |
172 |
+ |
((x & UVAL64(0x0000000000ff0000)) << 24) | |
173 |
+ |
((x & UVAL64(0x000000000000ff00)) << 40) | |
174 |
+ |
((x & UVAL64(0x00000000000000ff)) << 56) ); |
175 |
+ |
} |
176 |
+ |
|
177 |
+ |
#ifdef WORDS_BIGENDIAN |
178 |
+ |
static inline uint16 tswap16(uint16 x) { return x; } |
179 |
+ |
static inline uint32 tswap32(uint32 x) { return x; } |
180 |
+ |
static inline uint64 tswap64(uint64 x) { return x; } |
181 |
+ |
#else |
182 |
+ |
static inline uint16 tswap16(uint16 x) { return bswap_16(x); } |
183 |
+ |
static inline uint32 tswap32(uint32 x) { return bswap_32(x); } |
184 |
+ |
static inline uint64 tswap64(uint64 x) { return bswap_64(x); } |
185 |
+ |
#endif |
186 |
+ |
|
187 |
+ |
// spin locks |
188 |
+ |
#ifdef __GNUC__ |
189 |
+ |
|
190 |
+ |
#ifdef __powerpc__ |
191 |
+ |
#define HAVE_TEST_AND_SET 1 |
192 |
+ |
static inline int testandset(int *p) |
193 |
+ |
{ |
194 |
+ |
int ret; |
195 |
+ |
__asm__ __volatile__("0: lwarx %0,0,%1 ;" |
196 |
+ |
" xor. %0,%3,%0;" |
197 |
+ |
" bne 1f;" |
198 |
+ |
" stwcx. %2,0,%1;" |
199 |
+ |
" bne- 0b;" |
200 |
+ |
"1: " |
201 |
+ |
: "=&r" (ret) |
202 |
+ |
: "r" (p), "r" (1), "r" (0) |
203 |
+ |
: "cr0", "memory"); |
204 |
+ |
return ret; |
205 |
+ |
} |
206 |
+ |
#endif |
207 |
+ |
|
208 |
+ |
#ifdef __i386__ |
209 |
+ |
#define HAVE_TEST_AND_SET 1 |
210 |
+ |
static inline int testandset(int *p) |
211 |
+ |
{ |
212 |
+ |
char ret; |
213 |
+ |
long int readval; |
214 |
+ |
|
215 |
+ |
__asm__ __volatile__("lock; cmpxchgl %3, %1; sete %0" |
216 |
+ |
: "=q" (ret), "=m" (*p), "=a" (readval) |
217 |
+ |
: "r" (1), "m" (*p), "a" (0) |
218 |
+ |
: "memory"); |
219 |
+ |
return ret; |
220 |
+ |
} |
221 |
+ |
#endif |
222 |
+ |
|
223 |
+ |
#ifdef __s390__ |
224 |
+ |
#define HAVE_TEST_AND_SET 1 |
225 |
+ |
static inline int testandset(int *p) |
226 |
+ |
{ |
227 |
+ |
int ret; |
228 |
+ |
|
229 |
+ |
__asm__ __volatile__("0: cs %0,%1,0(%2)\n" |
230 |
+ |
" jl 0b" |
231 |
+ |
: "=&d" (ret) |
232 |
+ |
: "r" (1), "a" (p), "0" (*p) |
233 |
+ |
: "cc", "memory" ); |
234 |
+ |
return ret; |
235 |
+ |
} |
236 |
+ |
#endif |
237 |
+ |
|
238 |
+ |
#ifdef __alpha__ |
239 |
+ |
#define HAVE_TEST_AND_SET 1 |
240 |
+ |
static inline int testandset(int *p) |
241 |
+ |
{ |
242 |
+ |
int ret; |
243 |
+ |
unsigned long one; |
244 |
+ |
|
245 |
+ |
__asm__ __volatile__("0: mov 1,%2\n" |
246 |
+ |
" ldl_l %0,%1\n" |
247 |
+ |
" stl_c %2,%1\n" |
248 |
+ |
" beq %2,1f\n" |
249 |
+ |
".subsection 2\n" |
250 |
+ |
"1: br 0b\n" |
251 |
+ |
".previous" |
252 |
+ |
: "=r" (ret), "=m" (*p), "=r" (one) |
253 |
+ |
: "m" (*p)); |
254 |
+ |
return ret; |
255 |
+ |
} |
256 |
+ |
#endif |
257 |
+ |
|
258 |
+ |
#ifdef __sparc__ |
259 |
+ |
#define HAVE_TEST_AND_SET 1 |
260 |
+ |
static inline int testandset(int *p) |
261 |
+ |
{ |
262 |
+ |
int ret; |
263 |
+ |
|
264 |
+ |
__asm__ __volatile__("ldstub [%1], %0" |
265 |
+ |
: "=r" (ret) |
266 |
+ |
: "r" (p) |
267 |
+ |
: "memory"); |
268 |
+ |
|
269 |
+ |
return (ret ? 1 : 0); |
270 |
+ |
} |
271 |
+ |
#endif |
272 |
+ |
|
273 |
+ |
#ifdef __arm__ |
274 |
+ |
#define HAVE_TEST_AND_SET 1 |
275 |
+ |
static inline int testandset(int *p) |
276 |
+ |
{ |
277 |
+ |
register unsigned int ret; |
278 |
+ |
__asm__ __volatile__("swp %0, %1, [%2]" |
279 |
+ |
: "=r"(ret) |
280 |
+ |
: "0"(1), "r"(p)); |
281 |
+ |
|
282 |
+ |
return ret; |
283 |
+ |
} |
284 |
+ |
#endif |
285 |
+ |
|
286 |
+ |
#endif /* __GNUC__ */ |
287 |
+ |
|
288 |
+ |
#if HAVE_TEST_AND_SET |
289 |
+ |
#define HAVE_SPINLOCKS 1 |
290 |
+ |
typedef int spinlock_t; |
291 |
+ |
|
292 |
+ |
static const spinlock_t SPIN_LOCK_UNLOCKED = 0; |
293 |
+ |
|
294 |
+ |
static inline void spin_lock(spinlock_t *lock) |
295 |
+ |
{ |
296 |
+ |
while (testandset(lock)); |
297 |
+ |
} |
298 |
+ |
|
299 |
+ |
static inline void spin_unlock(spinlock_t *lock) |
300 |
+ |
{ |
301 |
+ |
*lock = 0; |
302 |
+ |
} |
303 |
+ |
|
304 |
+ |
static inline int spin_trylock(spinlock_t *lock) |
305 |
+ |
{ |
306 |
+ |
return !testandset(lock); |
307 |
+ |
} |
308 |
+ |
#endif |
309 |
+ |
|
310 |
|
// Time data type for Time Manager emulation |
311 |
|
#ifdef HAVE_CLOCK_GETTIME |
312 |
|
typedef struct timespec tm_time_t; |