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cebix |
1.1 |
/* |
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* CPUC64_SC.cpp - Single-cycle 6510 (C64) emulation |
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* |
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cebix |
1.8 |
* Frodo Copyright (C) Christian Bauer |
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cebix |
1.1 |
* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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*/ |
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/* |
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* Notes: |
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* ------ |
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* |
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* Opcode execution: |
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* - All opcodes are resolved into single clock cycles. There is one |
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* switch case for each cycle. |
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* - The "state" variable specifies the routine to be executed in the |
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* next cycle. Its upper 8 bits contain the current opcode, its lower |
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* 8 bits contain the cycle number (0..7) within the opcode. |
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* - Opcodes are fetched in cycle 0 (state = 0) |
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* - The states 0x0010..0x0027 are used for interrupts |
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* - There is exactly one memory access in each clock cycle |
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* |
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* Memory configurations: |
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* |
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* $01 $a000-$bfff $d000-$dfff $e000-$ffff |
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* ----------------------------------------------- |
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* 0 RAM RAM RAM |
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* 1 RAM Char ROM RAM |
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* 2 RAM Char ROM Kernal ROM |
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* 3 Basic ROM Char ROM Kernal ROM |
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* 4 RAM RAM RAM |
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* 5 RAM I/O RAM |
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* 6 RAM I/O Kernal ROM |
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* 7 Basic ROM I/O Kernal ROM |
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* |
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* - All memory accesses are done with the read_byte() and |
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* write_byte() functions which also do the memory address |
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* decoding. |
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* - If a write occurs to addresses 0 or 1, new_config is |
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* called to check whether the memory configuration has |
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* changed |
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* - The possible interrupt sources are: |
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* INT_VICIRQ: I flag is checked, jump to ($fffe) |
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* INT_CIAIRQ: I flag is checked, jump to ($fffe) |
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* INT_NMI: Jump to ($fffa) |
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* INT_RESET: Jump to ($fffc) |
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* - The z_flag variable has the inverse meaning of the |
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* 6510 Z flag |
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* - Only the highest bit of the n_flag variable is used |
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* - The $f2 opcode that would normally crash the 6510 is |
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* used to implement emulator-specific functions, mainly |
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* those for the IEC routines |
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* |
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* Incompatibilities: |
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* ------------------ |
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* |
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* - If BA is low and AEC is high, read accesses should occur |
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*/ |
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#include "sysdeps.h" |
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#include "CPUC64.h" |
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#include "CPU_common.h" |
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#include "C64.h" |
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#include "VIC.h" |
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#include "SID.h" |
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#include "CIA.h" |
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#include "REU.h" |
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#include "IEC.h" |
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#include "Display.h" |
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#include "Version.h" |
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enum { |
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INT_RESET = 3 |
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}; |
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/* |
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* 6510 constructor: Initialize registers |
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*/ |
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MOS6510::MOS6510(C64 *c64, uint8 *Ram, uint8 *Basic, uint8 *Kernal, uint8 *Char, uint8 *Color) |
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: the_c64(c64), ram(Ram), basic_rom(Basic), kernal_rom(Kernal), char_rom(Char), color_ram(Color) |
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{ |
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a = x = y = 0; |
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sp = 0xff; |
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n_flag = z_flag = 0; |
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v_flag = d_flag = c_flag = false; |
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i_flag = true; |
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dfff_byte = 0x55; |
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BALow = false; |
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first_irq_cycle = first_nmi_cycle = 0; |
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cebix |
1.8 |
opflags = 0; |
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cebix |
1.1 |
} |
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/* |
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* Reset CPU asynchronously |
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*/ |
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void MOS6510::AsyncReset(void) |
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{ |
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interrupt.intr[INT_RESET] = true; |
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} |
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/* |
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* Raise NMI asynchronously (Restore key) |
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*/ |
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void MOS6510::AsyncNMI(void) |
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{ |
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if (!nmi_state) |
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interrupt.intr[INT_NMI] = true; |
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} |
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/* |
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* Get 6510 register state |
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*/ |
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void MOS6510::GetState(MOS6510State *s) |
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{ |
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s->a = a; |
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s->x = x; |
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s->y = y; |
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s->p = 0x20 | (n_flag & 0x80); |
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if (v_flag) s->p |= 0x40; |
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if (d_flag) s->p |= 0x08; |
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if (i_flag) s->p |= 0x04; |
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if (!z_flag) s->p |= 0x02; |
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if (c_flag) s->p |= 0x01; |
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s->ddr = ddr; |
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s->pr = pr; |
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s->pc = pc; |
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s->sp = sp | 0x0100; |
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s->intr[INT_VICIRQ] = interrupt.intr[INT_VICIRQ]; |
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s->intr[INT_CIAIRQ] = interrupt.intr[INT_CIAIRQ]; |
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s->intr[INT_NMI] = interrupt.intr[INT_NMI]; |
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s->intr[INT_RESET] = interrupt.intr[INT_RESET]; |
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s->nmi_state = nmi_state; |
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s->dfff_byte = dfff_byte; |
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s->instruction_complete = (state == 0); |
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} |
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/* |
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* Restore 6510 state |
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*/ |
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void MOS6510::SetState(MOS6510State *s) |
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{ |
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a = s->a; |
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x = s->x; |
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y = s->y; |
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n_flag = s->p; |
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v_flag = s->p & 0x40; |
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d_flag = s->p & 0x08; |
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i_flag = s->p & 0x04; |
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z_flag = !(s->p & 0x02); |
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c_flag = s->p & 0x01; |
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ddr = s->ddr; |
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pr = s->pr; |
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cebix |
1.7 |
pr_out = 0; // FIXME: should be saved in MOS6510State |
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cebix |
1.1 |
new_config(); |
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pc = s->pc; |
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sp = s->sp & 0xff; |
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interrupt.intr[INT_VICIRQ] = s->intr[INT_VICIRQ]; |
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interrupt.intr[INT_CIAIRQ] = s->intr[INT_CIAIRQ]; |
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interrupt.intr[INT_NMI] = s->intr[INT_NMI]; |
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interrupt.intr[INT_RESET] = s->intr[INT_RESET]; |
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nmi_state = s->nmi_state; |
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dfff_byte = s->dfff_byte; |
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if (s->instruction_complete) |
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state = 0; |
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} |
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/* |
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* Memory configuration has probably changed |
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*/ |
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void MOS6510::new_config(void) |
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{ |
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cebix |
1.7 |
pr_out = (pr_out & ~ddr) | (pr & ddr); |
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uint8 port = pr | ~ddr; |
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cebix |
1.1 |
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basic_in = (port & 3) == 3; |
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kernal_in = port & 2; |
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char_in = (port & 3) && !(port & 4); |
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io_in = (port & 3) && (port & 4); |
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} |
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/* |
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* Read a byte from I/O / ROM space |
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*/ |
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inline uint8 MOS6510::read_byte_io(uint16 adr) |
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{ |
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switch (adr >> 12) { |
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case 0xa: |
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case 0xb: |
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if (basic_in) |
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return basic_rom[adr & 0x1fff]; |
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else |
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return ram[adr]; |
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case 0xc: |
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return ram[adr]; |
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case 0xd: |
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if (io_in) |
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switch ((adr >> 8) & 0x0f) { |
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case 0x0: // VIC |
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case 0x1: |
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case 0x2: |
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case 0x3: |
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return TheVIC->ReadRegister(adr & 0x3f); |
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case 0x4: // SID |
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case 0x5: |
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case 0x6: |
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case 0x7: |
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return TheSID->ReadRegister(adr & 0x1f); |
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case 0x8: // Color RAM |
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case 0x9: |
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case 0xa: |
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case 0xb: |
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return color_ram[adr & 0x03ff] & 0x0f | TheVIC->LastVICByte & 0xf0; |
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case 0xc: // CIA 1 |
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return TheCIA1->ReadRegister(adr & 0x0f); |
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case 0xd: // CIA 2 |
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return TheCIA2->ReadRegister(adr & 0x0f); |
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case 0xe: // REU/Open I/O |
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case 0xf: |
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if ((adr & 0xfff0) == 0xdf00) |
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return TheREU->ReadRegister(adr & 0x0f); |
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else if (adr < 0xdfa0) |
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return TheVIC->LastVICByte; |
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else |
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return read_emulator_id(adr & 0x7f); |
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} |
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else if (char_in) |
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return char_rom[adr & 0x0fff]; |
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else |
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return ram[adr]; |
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case 0xe: |
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case 0xf: |
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if (kernal_in) |
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return kernal_rom[adr & 0x1fff]; |
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else |
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return ram[adr]; |
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default: // Can't happen |
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return 0; |
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} |
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} |
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/* |
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* Read a byte from the CPU's address space |
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*/ |
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uint8 MOS6510::read_byte(uint16 adr) |
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{ |
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if (adr < 0xa000) { |
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cebix |
1.7 |
if (adr >= 2) { |
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cebix |
1.1 |
return ram[adr]; |
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cebix |
1.7 |
} else if (adr == 0) { |
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cebix |
1.1 |
return ddr; |
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cebix |
1.7 |
} else { |
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uint8 byte = (pr | ~ddr) & (pr_out | 0x17); |
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if (!(ddr & 0x20)) |
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byte &= 0xdf; |
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return byte; |
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} |
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cebix |
1.1 |
} else |
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return read_byte_io(adr); |
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} |
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/* |
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* $dfa0-$dfff: Emulator identification |
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*/ |
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cebix |
1.8 |
const char frodo_id[0x5c] = "FRODO\r(C) CHRISTIAN BAUER"; |
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cebix |
1.1 |
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uint8 MOS6510::read_emulator_id(uint16 adr) |
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{ |
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switch (adr) { |
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case 0x7c: // $dffc: revision |
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return FRODO_REVISION << 4; |
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case 0x7d: // $dffd: version |
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return FRODO_VERSION; |
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case 0x7e: // $dffe returns 'F' (Frodo ID) |
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return 'F'; |
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case 0x7f: // $dfff alternates between $55 and $aa |
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dfff_byte = ~dfff_byte; |
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return dfff_byte; |
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default: |
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return frodo_id[adr - 0x20]; |
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} |
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} |
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/* |
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* Read a word (little-endian) from the CPU's address space |
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*/ |
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inline uint16 MOS6510::read_word(uint16 adr) |
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{ |
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return read_byte(adr) | (read_byte(adr+1) << 8); |
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} |
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/* |
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* Write a byte to I/O space |
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*/ |
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inline void MOS6510::write_byte_io(uint16 adr, uint8 byte) |
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{ |
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if (adr >= 0xe000) { |
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ram[adr] = byte; |
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if (adr == 0xff00) |
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TheREU->FF00Trigger(); |
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} else if (io_in) |
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switch ((adr >> 8) & 0x0f) { |
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case 0x0: // VIC |
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case 0x1: |
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case 0x2: |
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case 0x3: |
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TheVIC->WriteRegister(adr & 0x3f, byte); |
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return; |
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case 0x4: // SID |
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case 0x5: |
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case 0x6: |
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case 0x7: |
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TheSID->WriteRegister(adr & 0x1f, byte); |
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return; |
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case 0x8: // Color RAM |
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case 0x9: |
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case 0xa: |
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case 0xb: |
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color_ram[adr & 0x03ff] = byte & 0x0f; |
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return; |
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case 0xc: // CIA 1 |
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TheCIA1->WriteRegister(adr & 0x0f, byte); |
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return; |
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case 0xd: // CIA 2 |
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TheCIA2->WriteRegister(adr & 0x0f, byte); |
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return; |
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case 0xe: // REU/Open I/O |
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case 0xf: |
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if ((adr & 0xfff0) == 0xdf00) |
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TheREU->WriteRegister(adr & 0x0f, byte); |
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return; |
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} |
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else |
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ram[adr] = byte; |
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} |
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| 381 |
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/* |
| 382 |
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|
* Write a byte to the CPU's address space |
| 383 |
|
|
*/ |
| 384 |
|
|
|
| 385 |
|
|
void MOS6510::write_byte(uint16 adr, uint8 byte) |
| 386 |
|
|
{ |
| 387 |
|
|
if (adr < 0xd000) { |
| 388 |
|
|
if (adr >= 2) |
| 389 |
|
|
ram[adr] = byte; |
| 390 |
|
|
else if (adr == 0) { |
| 391 |
|
|
ddr = byte; |
| 392 |
|
|
ram[0] = TheVIC->LastVICByte; |
| 393 |
|
|
new_config(); |
| 394 |
|
|
} else { |
| 395 |
|
|
pr = byte; |
| 396 |
|
|
ram[1] = TheVIC->LastVICByte; |
| 397 |
|
|
new_config(); |
| 398 |
|
|
} |
| 399 |
|
|
} else |
| 400 |
|
|
write_byte_io(adr, byte); |
| 401 |
|
|
} |
| 402 |
|
|
|
| 403 |
|
|
|
| 404 |
|
|
/* |
| 405 |
|
|
* Read byte from 6510 address space with special memory config (used by SAM) |
| 406 |
|
|
*/ |
| 407 |
|
|
|
| 408 |
|
|
uint8 MOS6510::ExtReadByte(uint16 adr) |
| 409 |
|
|
{ |
| 410 |
|
|
// Save old memory configuration |
| 411 |
|
|
bool bi = basic_in, ki = kernal_in, ci = char_in, ii = io_in; |
| 412 |
|
|
|
| 413 |
|
|
// Set new configuration |
| 414 |
|
|
basic_in = (ExtConfig & 3) == 3; |
| 415 |
|
|
kernal_in = ExtConfig & 2; |
| 416 |
|
|
char_in = (ExtConfig & 3) && ~(ExtConfig & 4); |
| 417 |
|
|
io_in = (ExtConfig & 3) && (ExtConfig & 4); |
| 418 |
|
|
|
| 419 |
|
|
// Read byte |
| 420 |
|
|
uint8 byte = read_byte(adr); |
| 421 |
|
|
|
| 422 |
|
|
// Restore old configuration |
| 423 |
|
|
basic_in = bi; kernal_in = ki; char_in = ci; io_in = ii; |
| 424 |
|
|
|
| 425 |
|
|
return byte; |
| 426 |
|
|
} |
| 427 |
|
|
|
| 428 |
|
|
|
| 429 |
|
|
/* |
| 430 |
|
|
* Write byte to 6510 address space with special memory config (used by SAM) |
| 431 |
|
|
*/ |
| 432 |
|
|
|
| 433 |
|
|
void MOS6510::ExtWriteByte(uint16 adr, uint8 byte) |
| 434 |
|
|
{ |
| 435 |
|
|
// Save old memory configuration |
| 436 |
|
|
bool bi = basic_in, ki = kernal_in, ci = char_in, ii = io_in; |
| 437 |
|
|
|
| 438 |
|
|
// Set new configuration |
| 439 |
|
|
basic_in = (ExtConfig & 3) == 3; |
| 440 |
|
|
kernal_in = ExtConfig & 2; |
| 441 |
|
|
char_in = (ExtConfig & 3) && ~(ExtConfig & 4); |
| 442 |
|
|
io_in = (ExtConfig & 3) && (ExtConfig & 4); |
| 443 |
|
|
|
| 444 |
|
|
// Write byte |
| 445 |
|
|
write_byte(adr, byte); |
| 446 |
|
|
|
| 447 |
|
|
// Restore old configuration |
| 448 |
|
|
basic_in = bi; kernal_in = ki; char_in = ci; io_in = ii; |
| 449 |
|
|
} |
| 450 |
|
|
|
| 451 |
|
|
|
| 452 |
|
|
/* |
| 453 |
|
|
* Read byte from 6510 address space with current memory config (used by REU) |
| 454 |
|
|
*/ |
| 455 |
|
|
|
| 456 |
|
|
uint8 MOS6510::REUReadByte(uint16 adr) |
| 457 |
|
|
{ |
| 458 |
|
|
return read_byte(adr); |
| 459 |
|
|
} |
| 460 |
|
|
|
| 461 |
|
|
|
| 462 |
|
|
/* |
| 463 |
|
|
* Write byte to 6510 address space with current memory config (used by REU) |
| 464 |
|
|
*/ |
| 465 |
|
|
|
| 466 |
|
|
void MOS6510::REUWriteByte(uint16 adr, uint8 byte) |
| 467 |
|
|
{ |
| 468 |
|
|
write_byte(adr, byte); |
| 469 |
|
|
} |
| 470 |
|
|
|
| 471 |
|
|
|
| 472 |
|
|
/* |
| 473 |
|
|
* Adc instruction |
| 474 |
|
|
*/ |
| 475 |
|
|
|
| 476 |
|
|
inline void MOS6510::do_adc(uint8 byte) |
| 477 |
|
|
{ |
| 478 |
|
|
if (!d_flag) { |
| 479 |
|
|
uint16 tmp; |
| 480 |
|
|
|
| 481 |
|
|
// Binary mode |
| 482 |
|
|
tmp = a + byte + (c_flag ? 1 : 0); |
| 483 |
|
|
c_flag = tmp > 0xff; |
| 484 |
|
|
v_flag = !((a ^ byte) & 0x80) && ((a ^ tmp) & 0x80); |
| 485 |
|
|
z_flag = n_flag = a = tmp; |
| 486 |
|
|
|
| 487 |
|
|
} else { |
| 488 |
|
|
uint16 al, ah; |
| 489 |
|
|
|
| 490 |
|
|
// Decimal mode |
| 491 |
|
|
al = (a & 0x0f) + (byte & 0x0f) + (c_flag ? 1 : 0); // Calculate lower nybble |
| 492 |
|
|
if (al > 9) al += 6; // BCD fixup for lower nybble |
| 493 |
|
|
|
| 494 |
|
|
ah = (a >> 4) + (byte >> 4); // Calculate upper nybble |
| 495 |
|
|
if (al > 0x0f) ah++; |
| 496 |
|
|
|
| 497 |
|
|
z_flag = a + byte + (c_flag ? 1 : 0); // Set flags |
| 498 |
|
|
n_flag = ah << 4; // Only highest bit used |
| 499 |
|
|
v_flag = (((ah << 4) ^ a) & 0x80) && !((a ^ byte) & 0x80); |
| 500 |
|
|
|
| 501 |
|
|
if (ah > 9) ah += 6; // BCD fixup for upper nybble |
| 502 |
|
|
c_flag = ah > 0x0f; // Set carry flag |
| 503 |
|
|
a = (ah << 4) | (al & 0x0f); // Compose result |
| 504 |
|
|
} |
| 505 |
|
|
} |
| 506 |
|
|
|
| 507 |
|
|
|
| 508 |
|
|
/* |
| 509 |
|
|
* Sbc instruction |
| 510 |
|
|
*/ |
| 511 |
|
|
|
| 512 |
|
|
inline void MOS6510::do_sbc(uint8 byte) |
| 513 |
|
|
{ |
| 514 |
|
|
uint16 tmp = a - byte - (c_flag ? 0 : 1); |
| 515 |
|
|
|
| 516 |
|
|
if (!d_flag) { |
| 517 |
|
|
|
| 518 |
|
|
// Binary mode |
| 519 |
|
|
c_flag = tmp < 0x100; |
| 520 |
|
|
v_flag = ((a ^ tmp) & 0x80) && ((a ^ byte) & 0x80); |
| 521 |
|
|
z_flag = n_flag = a = tmp; |
| 522 |
|
|
|
| 523 |
|
|
} else { |
| 524 |
|
|
uint16 al, ah; |
| 525 |
|
|
|
| 526 |
|
|
// Decimal mode |
| 527 |
|
|
al = (a & 0x0f) - (byte & 0x0f) - (c_flag ? 0 : 1); // Calculate lower nybble |
| 528 |
|
|
ah = (a >> 4) - (byte >> 4); // Calculate upper nybble |
| 529 |
|
|
if (al & 0x10) { |
| 530 |
|
|
al -= 6; // BCD fixup for lower nybble |
| 531 |
|
|
ah--; |
| 532 |
|
|
} |
| 533 |
|
|
if (ah & 0x10) ah -= 6; // BCD fixup for upper nybble |
| 534 |
|
|
|
| 535 |
|
|
c_flag = tmp < 0x100; // Set flags |
| 536 |
|
|
v_flag = ((a ^ tmp) & 0x80) && ((a ^ byte) & 0x80); |
| 537 |
|
|
z_flag = n_flag = tmp; |
| 538 |
|
|
|
| 539 |
|
|
a = (ah << 4) | (al & 0x0f); // Compose result |
| 540 |
|
|
} |
| 541 |
|
|
} |
| 542 |
|
|
|
| 543 |
|
|
|
| 544 |
|
|
/* |
| 545 |
|
|
* Reset CPU |
| 546 |
|
|
*/ |
| 547 |
|
|
|
| 548 |
|
|
void MOS6510::Reset(void) |
| 549 |
|
|
{ |
| 550 |
|
|
// Delete 'CBM80' if present |
| 551 |
|
|
if (ram[0x8004] == 0xc3 && ram[0x8005] == 0xc2 && ram[0x8006] == 0xcd |
| 552 |
|
|
&& ram[0x8007] == 0x38 && ram[0x8008] == 0x30) |
| 553 |
|
|
ram[0x8004] = 0; |
| 554 |
|
|
|
| 555 |
|
|
// Initialize extra 6510 registers and memory configuration |
| 556 |
cebix |
1.7 |
ddr = pr = pr_out = 0; |
| 557 |
cebix |
1.1 |
new_config(); |
| 558 |
|
|
|
| 559 |
|
|
// Clear all interrupt lines |
| 560 |
|
|
interrupt.intr_any = 0; |
| 561 |
|
|
nmi_state = false; |
| 562 |
cebix |
1.8 |
opflags = 0; |
| 563 |
cebix |
1.1 |
|
| 564 |
|
|
// Read reset vector |
| 565 |
|
|
pc = read_word(0xfffc); |
| 566 |
|
|
state = 0; |
| 567 |
|
|
} |
| 568 |
|
|
|
| 569 |
|
|
|
| 570 |
|
|
/* |
| 571 |
|
|
* Illegal opcode encountered |
| 572 |
|
|
*/ |
| 573 |
|
|
|
| 574 |
|
|
void MOS6510::illegal_op(uint8 op, uint16 at) |
| 575 |
|
|
{ |
| 576 |
|
|
char illop_msg[80]; |
| 577 |
|
|
|
| 578 |
|
|
sprintf(illop_msg, "Illegal opcode %02x at %04x.", op, at); |
| 579 |
|
|
ShowRequester(illop_msg, "Reset"); |
| 580 |
|
|
the_c64->Reset(); |
| 581 |
|
|
Reset(); |
| 582 |
|
|
} |
| 583 |
|
|
|
| 584 |
|
|
|
| 585 |
|
|
/* |
| 586 |
|
|
* Emulate one 6510 clock cycle |
| 587 |
|
|
*/ |
| 588 |
|
|
|
| 589 |
|
|
// Read byte from memory |
| 590 |
|
|
#define read_to(adr, to) \ |
| 591 |
|
|
if (BALow) \ |
| 592 |
|
|
return; \ |
| 593 |
|
|
to = read_byte(adr); |
| 594 |
|
|
|
| 595 |
|
|
// Read byte from memory, throw away result |
| 596 |
|
|
#define read_idle(adr) \ |
| 597 |
|
|
if (BALow) \ |
| 598 |
|
|
return; \ |
| 599 |
|
|
read_byte(adr); |
| 600 |
|
|
|
| 601 |
|
|
void MOS6510::EmulateCycle(void) |
| 602 |
|
|
{ |
| 603 |
|
|
uint8 data, tmp; |
| 604 |
|
|
|
| 605 |
|
|
// Any pending interrupts in state 0 (opcode fetch)? |
| 606 |
|
|
if (!state && interrupt.intr_any) { |
| 607 |
cebix |
1.8 |
if (interrupt.intr[INT_RESET]) { |
| 608 |
cebix |
1.1 |
Reset(); |
| 609 |
cebix |
1.8 |
} else if (interrupt.intr[INT_NMI]) { |
| 610 |
|
|
uint32 int_delay = (opflags & OPFLAG_INT_DELAYED) ? 1 : 0; // Taken branches to the same page delay the NMI |
| 611 |
|
|
if (the_c64->CycleCounter - first_nmi_cycle - int_delay >= 2) { |
| 612 |
|
|
interrupt.intr[INT_NMI] = false; // Simulate an edge-triggered input |
| 613 |
|
|
state = 0x0010; |
| 614 |
|
|
opflags = 0; |
| 615 |
|
|
} |
| 616 |
|
|
} else if ((interrupt.intr[INT_VICIRQ] || interrupt.intr[INT_CIAIRQ]) && |
| 617 |
|
|
(!i_flag || (opflags & OPFLAG_IRQ_DISABLED)) && !(opflags & OPFLAG_IRQ_ENABLED)) { |
| 618 |
|
|
uint32 int_delay = (opflags & OPFLAG_INT_DELAYED) ? 1 : 0; // Taken branches to the same page delay the IRQ |
| 619 |
|
|
if (the_c64->CycleCounter - first_irq_cycle - int_delay >= 2) { |
| 620 |
|
|
state = 0x0008; |
| 621 |
|
|
opflags = 0; |
| 622 |
|
|
} |
| 623 |
|
|
} |
| 624 |
cebix |
1.1 |
} |
| 625 |
|
|
|
| 626 |
|
|
#include "CPU_emulcycle.h" |
| 627 |
|
|
|
| 628 |
|
|
// Extension opcode |
| 629 |
|
|
case O_EXT: |
| 630 |
|
|
if (pc < 0xe000) { |
| 631 |
|
|
illegal_op(0xf2, pc-1); |
| 632 |
|
|
break; |
| 633 |
|
|
} |
| 634 |
|
|
switch (read_byte(pc++)) { |
| 635 |
|
|
case 0x00: |
| 636 |
|
|
ram[0x90] |= TheIEC->Out(ram[0x95], ram[0xa3] & 0x80); |
| 637 |
|
|
c_flag = false; |
| 638 |
|
|
pc = 0xedac; |
| 639 |
|
|
Last; |
| 640 |
|
|
case 0x01: |
| 641 |
|
|
ram[0x90] |= TheIEC->OutATN(ram[0x95]); |
| 642 |
|
|
c_flag = false; |
| 643 |
|
|
pc = 0xedac; |
| 644 |
|
|
Last; |
| 645 |
|
|
case 0x02: |
| 646 |
|
|
ram[0x90] |= TheIEC->OutSec(ram[0x95]); |
| 647 |
|
|
c_flag = false; |
| 648 |
|
|
pc = 0xedac; |
| 649 |
|
|
Last; |
| 650 |
|
|
case 0x03: |
| 651 |
cebix |
1.4 |
ram[0x90] |= TheIEC->In(a); |
| 652 |
cebix |
1.1 |
set_nz(a); |
| 653 |
|
|
c_flag = false; |
| 654 |
|
|
pc = 0xedac; |
| 655 |
|
|
Last; |
| 656 |
|
|
case 0x04: |
| 657 |
|
|
TheIEC->SetATN(); |
| 658 |
|
|
pc = 0xedfb; |
| 659 |
|
|
Last; |
| 660 |
|
|
case 0x05: |
| 661 |
|
|
TheIEC->RelATN(); |
| 662 |
|
|
pc = 0xedac; |
| 663 |
|
|
Last; |
| 664 |
|
|
case 0x06: |
| 665 |
|
|
TheIEC->Turnaround(); |
| 666 |
|
|
pc = 0xedac; |
| 667 |
|
|
Last; |
| 668 |
|
|
case 0x07: |
| 669 |
|
|
TheIEC->Release(); |
| 670 |
|
|
pc = 0xedac; |
| 671 |
|
|
Last; |
| 672 |
|
|
default: |
| 673 |
|
|
illegal_op(0xf2, pc-1); |
| 674 |
|
|
break; |
| 675 |
|
|
} |
| 676 |
|
|
break; |
| 677 |
|
|
|
| 678 |
|
|
default: |
| 679 |
|
|
illegal_op(op, pc-1); |
| 680 |
|
|
break; |
| 681 |
|
|
} |
| 682 |
|
|
} |
