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root/cebix/BasiliskII/src/uae_cpu/table68k
Revision: 1.8
Committed: 2002-09-01T15:17:13Z (22 years, 3 months ago) by gbeauche
Branch: MAIN
CVS Tags: nigel-build-19, nigel-build-12, nigel-build-13, nigel-build-16, nigel-build-17, nigel-build-15, HEAD
Changes since 1.7: +209 -196 lines
Log Message: 
- Merge with Basilisk II/JIT cpu core, interpretive part for now
- Clean use of USE_PREFETCH_BUFFER macro and dependent bits

File Contents

# User Rev Content
1 cebix 1.1 % 0: bit 0
2     % 1: bit 1
3     % c: condition code
4     % C: condition codes, except F
5     % f: direction
6     % i: immediate
7 gbeauche 1.8 % E: immediate, except 00 (for EmulOp instructions)
8 cebix 1.1 % I: immediate, except 00 and ff
9     % j: immediate 1..8
10     % J: immediate 0..15
11     % k: immediate 0..7
12     % K: immediate 0..63
13 gbeauche 1.8 % p: immediate 0..3 (CINV and CPUSH instructions: Cache Field)
14 cebix 1.1 % s: source mode
15     % S: source reg
16     % d: dest mode
17     % D: dest reg
18     % r: reg
19     % z: size
20     %
21     % Actually, a sssSSS may appear as a destination, and
22     % vice versa. The only difference between sssSSS and
23     % dddDDD are the valid addressing modes. There is
24     % no match for immediate and pc-rel. addressing modes
25     % in case of dddDDD.
26     %
27     % Arp: --> -(Ar)
28     % ArP: --> (Ar)+
29 gbeauche 1.8 % L: --> (xxx.L)
30 cebix 1.1 %
31     % Fields on a line:
32     % 16 chars bitpattern :
33 cebix 1.2 % CPU level / privilege level :
34 cebix 1.1 % CPU level 0: 68000
35     % 1: 68010
36     % 2: 68020
37 cebix 1.2 % 3: 68020/68881
38     % 4: 68040
39 cebix 1.1 % privilege level 0: not privileged
40     % 1: unprivileged only on 68000 (check regs.s)
41     % 2: privileged (check regs.s)
42     % 3: privileged if size == word (check regs.s)
43     % Flags set by instruction: XNZVC :
44     % Flags used by instruction: XNZVC :
45     % - means flag unaffected / unused
46     % 0 means flag reset
47     % 1 means flag set
48     % ? means programmer was too lazy to check or instruction may trap
49     % everything else means flag set/used
50     % x means flag is unknown and well-behaved programs shouldn't check it
51 gbeauche 1.8 %
52     % Control flow
53     % two letters, combination of
54     % - nothing
55     % T the instruction may trap or cause an exception
56     % B branch instruction
57     % J jump instruction
58     % R return instruction
59     %
60 cebix 1.1 % srcaddr status destaddr status :
61     % bitmasks of
62     % 1 means fetched
63     % 2 means stored
64     % 4 means jump offset
65     % 8 means jump address
66     % instruction
67     %
68    
69 gbeauche 1.8 0000 0000 0011 1100:00:XNZVC:XNZVC:--:10: ORSR.B #1
70     0000 0000 0111 1100:02:XNZVC:XNZVC:T-:10: ORSR.W #1
71     0000 0zz0 11ss sSSS:20:-?Z?C:-----:T-:11: CHK2.z #1,s[!Dreg,Areg,Aipi,Apdi,Immd]
72     0000 0000 zzdd dDDD:00:-NZ00:-----:--:13: OR.z #z,d[!Areg]
73     0000 0010 0011 1100:00:XNZVC:XNZVC:--:10: ANDSR.B #1
74     0000 0010 0111 1100:02:XNZVC:XNZVC:T-:10: ANDSR.W #1
75     0000 0010 zzdd dDDD:00:-NZ00:-----:--:13: AND.z #z,d[!Areg]
76     0000 0100 zzdd dDDD:00:XNZVC:-----:--:13: SUB.z #z,d[!Areg]
77     0000 0110 zzdd dDDD:00:XNZVC:-----:--:13: ADD.z #z,d[!Areg]
78     0000 0110 11ss sSSS:20:-----:XNZVC:--:10: CALLM s[!Dreg,Areg,Aipi,Apdi,Immd]
79     0000 0110 11ss sSSS:20:XNZVC:-----:-R:10: RTM s[Dreg,Areg]
80     0000 1000 00ss sSSS:00:--Z--:-----:--:11: BTST #1,s[!Areg]
81     0000 1000 01ss sSSS:00:--Z--:-----:--:13: BCHG #1,s[!Areg,Immd]
82     0000 1000 10ss sSSS:00:--Z--:-----:--:13: BCLR #1,s[!Areg,Immd]
83     0000 1000 11ss sSSS:00:--Z--:-----:--:13: BSET #1,s[!Areg,Immd]
84     0000 1010 0011 1100:00:XNZVC:XNZVC:--:10: EORSR.B #1
85     0000 1010 0111 1100:02:XNZVC:XNZVC:T-:10: EORSR.W #1
86     0000 1010 zzdd dDDD:00:-NZ00:-----:--:13: EOR.z #z,d[!Areg]
87     0000 1100 zzss sSSS:00:-NZVC:-----:--:11: CMP.z #z,s[!Areg,Immd]
88    
89     0000 1010 11ss sSSS:20:-NZVC:-----:--:13: CAS.B #1,s[!Dreg,Areg,Immd,PC8r,PC16]
90     0000 1100 11ss sSSS:20:-NZVC:-----:--:13: CAS.W #1,s[!Dreg,Areg,Immd,PC8r,PC16]
91     0000 1100 1111 1100:20:-NZVC:-----:--:10: CAS2.W #2
92     0000 1110 zzss sSSS:22:-----:-----:T-:13: MOVES.z #1,s[!Dreg,Areg,Immd,PC8r,PC16]
93     0000 1110 11ss sSSS:20:-NZVC:-----:--:13: CAS.L #1,s[!Dreg,Areg,Immd,PC8r,PC16]
94     0000 1110 1111 1100:20:-NZVC:-----:--:10: CAS2.L #2
95    
96     0000 rrr1 00dd dDDD:00:-----:-----:--:12: MVPMR.W d[Areg-Ad16],Dr
97     0000 rrr1 01dd dDDD:00:-----:-----:--:12: MVPMR.L d[Areg-Ad16],Dr
98     0000 rrr1 10dd dDDD:00:-----:-----:--:12: MVPRM.W Dr,d[Areg-Ad16]
99     0000 rrr1 11dd dDDD:00:-----:-----:--:12: MVPRM.L Dr,d[Areg-Ad16]
100     0000 rrr1 00ss sSSS:00:--Z--:-----:--:11: BTST Dr,s[!Areg]
101     0000 rrr1 01ss sSSS:00:--Z--:-----:--:13: BCHG Dr,s[!Areg,Immd]
102     0000 rrr1 10ss sSSS:00:--Z--:-----:--:13: BCLR Dr,s[!Areg,Immd]
103     0000 rrr1 11ss sSSS:00:--Z--:-----:--:13: BSET Dr,s[!Areg,Immd]
104    
105     0001 DDDd ddss sSSS:00:-NZ00:-----:--:12: MOVE.B s,d[!Areg]
106     0010 DDDd ddss sSSS:00:-----:-----:--:12: MOVEA.L s,d[Areg]
107     0010 DDDd ddss sSSS:00:-NZ00:-----:--:12: MOVE.L s,d[!Areg]
108     0011 DDDd ddss sSSS:00:-----:-----:--:12: MOVEA.W s,d[Areg]
109     0011 DDDd ddss sSSS:00:-NZ00:-----:--:12: MOVE.W s,d[!Areg]
110    
111     0100 0000 zzdd dDDD:00:XxZxC:X-Z--:--:30: NEGX.z d[!Areg]
112     0100 0000 11dd dDDD:01:-----:XNZVC:T-:10: MVSR2.W d[!Areg]
113     0100 0010 zzdd dDDD:00:-0100:-----:--:20: CLR.z d[!Areg]
114     0100 0010 11dd dDDD:10:-----:XNZVC:--:10: MVSR2.B d[!Areg]
115     0100 0100 zzdd dDDD:00:XNZVC:-----:--:30: NEG.z d[!Areg]
116     0100 0100 11ss sSSS:00:XNZVC:-----:--:10: MV2SR.B s[!Areg]
117     0100 0110 zzdd dDDD:00:-NZ00:-----:--:30: NOT.z d[!Areg]
118     0100 0110 11ss sSSS:02:XNZVC:XNZVC:T-:10: MV2SR.W s[!Areg]
119     0100 1000 0000 1rrr:20:-----:-----:--:31: LINK.L Ar,#2
120     0100 1000 00dd dDDD:00:X?Z?C:X-Z--:--:30: NBCD.B d[!Areg]
121     0100 1000 0100 1kkk:20:-----:-----:T-:10: BKPT #k
122     0100 1000 01ss sSSS:00:-NZ00:-----:--:30: SWAP.W s[Dreg]
123     0100 1000 01ss sSSS:00:-----:-----:--:00: PEA.L s[!Dreg,Areg,Aipi,Apdi,Immd]
124     0100 1000 10dd dDDD:00:-NZ00:-----:--:30: EXT.W d[Dreg]
125     0100 1000 10dd dDDD:00:-----:-----:--:02: MVMLE.W #1,d[!Dreg,Areg,Aipi]
126     0100 1000 11dd dDDD:00:-NZ00:-----:--:30: EXT.L d[Dreg]
127     0100 1000 11dd dDDD:00:-----:-----:--:02: MVMLE.L #1,d[!Dreg,Areg,Aipi]
128     0100 1001 11dd dDDD:00:-NZ00:-----:--:30: EXT.B d[Dreg]
129     0100 1010 zzss sSSS:00:-NZ00:-----:--:10: TST.z s
130     0100 1010 11dd dDDD:00:-NZ00:-----:--:30: TAS.B d[!Areg]
131     0100 1010 1111 1100:00:-----:-----:T-:00: ILLEGAL
132     0100 1100 00ss sSSS:20:-NZVC:-----:--:13: MULL.L #1,s[!Areg]
133     0100 1100 01ss sSSS:20:-NZV0:-----:T-:13: DIVL.L #1,s[!Areg]
134     0100 1100 10ss sSSS:00:-----:-----:--:01: MVMEL.W #1,s[!Dreg,Areg,Apdi,Immd]
135     0100 1100 11ss sSSS:00:-----:-----:--:01: MVMEL.L #1,s[!Dreg,Areg,Apdi,Immd]
136     0100 1110 0100 JJJJ:00:-----:XNZVC:--:10: TRAP #J
137     0100 1110 0101 0rrr:00:-----:-----:--:31: LINK.W Ar,#1
138     0100 1110 0101 1rrr:00:-----:-----:--:30: UNLK.L Ar
139     0100 1110 0110 0rrr:02:-----:-----:T-:10: MVR2USP.L Ar
140     0100 1110 0110 1rrr:02:-----:-----:T-:20: MVUSP2R.L Ar
141     0100 1110 0111 0000:02:-----:-----:T-:00: RESET
142     0100 1110 0111 0001:00:-----:-----:--:00: NOP
143     0100 1110 0111 0010:02:XNZVC:-----:T-:10: STOP #1
144     0100 1110 0111 0011:02:XNZVC:-----:TR:00: RTE
145     0100 1110 0111 0100:00:-----:-----:-R:10: RTD #1
146     0100 1110 0111 0101:00:-----:-----:-R:00: RTS
147     0100 1110 0111 0110:00:-----:XNZVC:T-:00: TRAPV
148     0100 1110 0111 0111:00:XNZVC:-----:-R:00: RTR
149     0100 1110 0111 1010:12:-----:-----:T-:10: MOVEC2 #1
150     0100 1110 0111 1011:12:-----:-----:T-:10: MOVE2C #1
151     0100 1110 10ss sSSS:00:-----:-----:-J:80: JSR.L s[!Dreg,Areg,Aipi,Apdi,Immd]
152     0100 rrr1 00ss sSSS:00:-N???:-----:T-:11: CHK.L s[!Areg],Dr
153     0100 rrr1 10ss sSSS:00:-N???:-----:T-:11: CHK.W s[!Areg],Dr
154     0100 1110 11ss sSSS:00:-----:-----:-J:80: JMP.L s[!Dreg,Areg,Aipi,Apdi,Immd]
155     0100 rrr1 11ss sSSS:00:-----:-----:--:02: LEA.L s[!Dreg,Areg,Aipi,Apdi,Immd],Ar
156    
157     0101 jjj0 01dd dDDD:00:-----:-----:--:13: ADDA.W #j,d[Areg]
158     0101 jjj0 10dd dDDD:00:-----:-----:--:13: ADDA.L #j,d[Areg]
159     0101 jjj0 zzdd dDDD:00:XNZVC:-----:--:13: ADD.z #j,d[!Areg]
160     0101 jjj1 01dd dDDD:00:-----:-----:--:13: SUBA.W #j,d[Areg]
161     0101 jjj1 10dd dDDD:00:-----:-----:--:13: SUBA.L #j,d[Areg]
162     0101 jjj1 zzdd dDDD:00:XNZVC:-----:--:13: SUB.z #j,d[!Areg]
163    
164     0101 cccc 1100 1rrr:00:-----:-????:-B:31: DBcc.W Dr,#1
165     0101 cccc 11dd dDDD:00:-----:-????:--:20: Scc.B d[!Areg]
166     0101 cccc 1111 1010:20:-----:-????:T-:10: TRAPcc #1
167     0101 cccc 1111 1011:20:-----:-????:T-:10: TRAPcc #2
168     0101 cccc 1111 1100:20:-----:-????:T-:00: TRAPcc
169 cebix 1.1
170     % Bxx.L is 68020 only, but setting the CPU level to 2 would give illegal
171     % instruction exceptions when compiling a 68000 only emulation, which isn't
172     % what we want either.
173 gbeauche 1.8 0110 0001 0000 0000:00:-----:-----:-B:40: BSR.W #1
174     0110 0001 IIII IIII:00:-----:-----:-B:40: BSR.B #i
175     0110 0001 1111 1111:00:-----:-----:-B:40: BSR.L #2
176     0110 CCCC 0000 0000:00:-----:-????:-B:40: Bcc.W #1
177     0110 CCCC IIII IIII:00:-----:-????:-B:40: Bcc.B #i
178     0110 CCCC 1111 1111:00:-----:-????:-B:40: Bcc.L #2
179    
180     0111 rrr0 iiii iiii:00:-NZ00:-----:--:12: MOVE.L #i,Dr
181    
182     1000 rrr0 zzss sSSS:00:-NZ00:-----:--:13: OR.z s[!Areg],Dr
183     1000 rrr0 11ss sSSS:00:-NZV0:-----:T-:13: DIVU.W s[!Areg],Dr
184     1000 rrr1 00dd dDDD:00:XxZxC:X-Z--:--:13: SBCD.B d[Dreg],Dr
185     1000 rrr1 00dd dDDD:00:XxZxC:X-Z--:--:13: SBCD.B d[Areg-Apdi],Arp
186     1000 rrr1 zzdd dDDD:00:-NZ00:-----:--:13: OR.z Dr,d[!Areg,Dreg]
187     1000 rrr1 01dd dDDD:20:-----:-----:--:12: PACK d[Dreg],Dr
188     1000 rrr1 01dd dDDD:20:-----:-----:--:12: PACK d[Areg-Apdi],Arp
189     1000 rrr1 10dd dDDD:20:-----:-----:--:12: UNPK d[Dreg],Dr
190     1000 rrr1 10dd dDDD:20:-----:-----:--:12: UNPK d[Areg-Apdi],Arp
191     1000 rrr1 11ss sSSS:00:-NZV0:-----:T-:13: DIVS.W s[!Areg],Dr
192    
193     1001 rrr0 zzss sSSS:00:XNZVC:-----:--:13: SUB.z s,Dr
194     1001 rrr0 11ss sSSS:00:-----:-----:--:13: SUBA.W s,Ar
195     1001 rrr1 zzdd dDDD:00:XNZVC:X-Z--:--:13: SUBX.z d[Dreg],Dr
196     1001 rrr1 zzdd dDDD:00:XNZVC:X-Z--:--:13: SUBX.z d[Areg-Apdi],Arp
197     1001 rrr1 zzdd dDDD:00:XNZVC:-----:--:13: SUB.z Dr,d[!Areg,Dreg]
198     1001 rrr1 11ss sSSS:00:-----:-----:--:13: SUBA.L s,Ar
199    
200     1011 rrr0 zzss sSSS:00:-NZVC:-----:--:11: CMP.z s,Dr
201     1011 rrr0 11ss sSSS:00:-NZVC:-----:--:11: CMPA.W s,Ar
202     1011 rrr1 11ss sSSS:00:-NZVC:-----:--:11: CMPA.L s,Ar
203     1011 rrr1 zzdd dDDD:00:-NZVC:-----:--:11: CMPM.z d[Areg-Aipi],ArP
204     1011 rrr1 zzdd dDDD:00:-NZ00:-----:--:13: EOR.z Dr,d[!Areg]
205    
206     1100 rrr0 zzss sSSS:00:-NZ00:-----:--:13: AND.z s[!Areg],Dr
207     1100 rrr0 11ss sSSS:00:-NZ00:-----:--:13: MULU.W s[!Areg],Dr
208     1100 rrr1 00dd dDDD:00:XxZxC:X-Z--:--:13: ABCD.B d[Dreg],Dr
209     1100 rrr1 00dd dDDD:00:XxZxC:X-Z--:--:13: ABCD.B d[Areg-Apdi],Arp
210     1100 rrr1 zzdd dDDD:00:-NZ00:-----:--:13: AND.z Dr,d[!Areg,Dreg]
211     1100 rrr1 01dd dDDD:00:-----:-----:--:33: EXG.L Dr,d[Dreg]
212     1100 rrr1 01dd dDDD:00:-----:-----:--:33: EXG.L Ar,d[Areg]
213     1100 rrr1 10dd dDDD:00:-----:-----:--:33: EXG.L Dr,d[Areg]
214     1100 rrr1 11ss sSSS:00:-NZ00:-----:--:13: MULS.W s[!Areg],Dr
215    
216     1101 rrr0 zzss sSSS:00:XNZVC:-----:--:13: ADD.z s,Dr
217     1101 rrr0 11ss sSSS:00:-----:-----:--:13: ADDA.W s,Ar
218     1101 rrr1 zzdd dDDD:00:XNZVC:X-Z--:--:13: ADDX.z d[Dreg],Dr
219     1101 rrr1 zzdd dDDD:00:XNZVC:X-Z--:--:13: ADDX.z d[Areg-Apdi],Arp
220     1101 rrr1 zzdd dDDD:00:XNZVC:-----:--:13: ADD.z Dr,d[!Areg,Dreg]
221     1101 rrr1 11ss sSSS:00:-----:-----:--:13: ADDA.L s,Ar
222    
223     1110 jjjf zz00 0RRR:00:XNZVC:-----:--:13: ASf.z #j,DR
224     1110 jjjf zz00 1RRR:00:XNZ0C:-----:--:13: LSf.z #j,DR
225     1110 jjjf zz01 0RRR:00:XNZ0C:X----:--:13: ROXf.z #j,DR
226     1110 jjjf zz01 1RRR:00:-NZ0C:-----:--:13: ROf.z #j,DR
227     1110 rrrf zz10 0RRR:00:XNZVC:-----:--:13: ASf.z Dr,DR
228     1110 rrrf zz10 1RRR:00:XNZ0C:-----:--:13: LSf.z Dr,DR
229     1110 rrrf zz11 0RRR:00:XNZ0C:X----:--:13: ROXf.z Dr,DR
230     1110 rrrf zz11 1RRR:00:-NZ0C:-----:--:13: ROf.z Dr,DR
231     1110 000f 11dd dDDD:00:XNZVC:-----:--:13: ASfW.W d[!Dreg,Areg]
232     1110 001f 11dd dDDD:00:XNZ0C:-----:--:13: LSfW.W d[!Dreg,Areg]
233     1110 010f 11dd dDDD:00:XNZ0C:X----:--:13: ROXfW.W d[!Dreg,Areg]
234     1110 011f 11dd dDDD:00:-NZ0C:-----:--:13: ROfW.W d[!Dreg,Areg]
235    
236     1110 1000 11ss sSSS:20:-NZ00:-----:--:11: BFTST #1,s[!Areg,Apdi,Aipi,Immd]
237     1110 1001 11ss sSSS:20:-NZ00:-----:--:11: BFEXTU #1,s[!Areg,Apdi,Aipi,Immd]
238     1110 1010 11ss sSSS:20:-NZ00:-----:--:13: BFCHG #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
239     1110 1011 11ss sSSS:20:-NZ00:-----:--:11: BFEXTS #1,s[!Areg,Apdi,Aipi,Immd]
240     1110 1100 11ss sSSS:20:-NZ00:-----:--:13: BFCLR #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
241     1110 1101 11ss sSSS:20:-NZ00:-----:--:11: BFFFO #1,s[!Areg,Apdi,Aipi,Immd]
242     1110 1110 11ss sSSS:20:-NZ00:-----:--:13: BFSET #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
243     1110 1111 11ss sSSS:20:-NZ00:-----:--:13: BFINS #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
244 cebix 1.1
245     % floating point co processor
246 gbeauche 1.8 1111 0010 00ss sSSS:30:-----:-----:--:11: FPP #1,s
247     1111 0010 01ss sSSS:30:-----:-----:-B:11: FDBcc #1,s[Areg-Dreg]
248     1111 0010 01ss sSSS:30:-----:-----:--:11: FScc #1,s[!Areg,Immd,PC8r,PC16]
249     1111 0010 0111 1010:30:-----:-----:T-:10: FTRAPcc #1
250     1111 0010 0111 1011:30:-----:-----:T-:10: FTRAPcc #2
251     1111 0010 0111 1100:30:-----:-----:T-:00: FTRAPcc
252     1111 0010 10KK KKKK:30:-----:-----:-B:11: FBcc #K,#1
253     1111 0010 11KK KKKK:30:-----:-----:-B:11: FBcc #K,#2
254     1111 0011 00ss sSSS:32:-----:-----:--:20: FSAVE s[!Dreg,Areg,Aipi,Immd,PC8r,PC16]
255     1111 0011 01ss sSSS:32:-----:-----:--:10: FRESTORE s[!Dreg,Areg,Apdi,Immd]
256 cebix 1.1
257 cebix 1.2 % 68040 instructions
258 gbeauche 1.8 1111 0101 iiii iSSS:40:-----:-----:T-:11: MMUOP #i,s
259     1111 0100 pp00 1rrr:42:-----:-----:T-:02: CINVL #p,Ar
260     1111 0100 pp01 0rrr:42:-----:-----:T-:02: CINVP #p,Ar
261     1111 0100 pp01 1rrr:42:-----:-----:T-:00: CINVA #p
262     1111 0100 pp10 1rrr:42:-----:-----:T-:02: CPUSHL #p,Ar
263     1111 0100 pp11 0rrr:42:-----:-----:T-:02: CPUSHP #p,Ar
264     1111 0100 pp11 1rrr:42:-----:-----:T-:00: CPUSHA #p
265 gbeauche 1.6 % destination register number is encoded in the following word
266 gbeauche 1.8 1111 0110 0010 0rrr:40:-----:-----:--:12: MOVE16 ArP,AxP
267     1111 0110 00ss sSSS:40:-----:-----:--:12: MOVE16 s[Dreg-Aipi],L
268     1111 0110 00dd dDDD:40:-----:-----:--:12: MOVE16 L,d[Areg-Aipi]
269     1111 0110 00ss sSSS:40:-----:-----:--:12: MOVE16 s[Aind],L
270     1111 0110 00dd dDDD:40:-----:-----:--:12: MOVE16 L,d[Aipi-Aind]
271    
272     % EmulOp instructions
273     0111 0001 0000 0000:00:-----:-----:-R:00: EMULOP_RETURN
274     0111 0001 EEEE EEEE:00:-----:-----:-J:10: EMULOP #E