Revision 1.8 - (view) (annotate) - [select for diffs]
2002-09-01T15:17:13Z (22 years, 3 months ago) by gbeauche
Branch: MAIN
CVS Tags: HEAD, nigel-build-12, nigel-build-13, nigel-build-15, nigel-build-16, nigel-build-17, nigel-build-19
Changes since 1.7: +209 -196 lines
Diff to previous 1.7 , to selected 1.1

- Merge with Basilisk II/JIT cpu core, interpretive part for now
- Clean use of USE_PREFETCH_BUFFER macro and dependent bits

- When X86_ASSEMBLY is set, aka when cpuopti is used, do call the
  instruction handler by hand and make sure to save %ebp too
- Really merge cpu core with uae-0.8.21:
  - Trace mode fixes (Bernd Roesch & Bernd Schmidt)
  - Reintegrate PTEST and PFLUSH instructions back as no-ops

Revision 1.6 - (view) (annotate) - [select for diffs]
2001-08-19T16:21:01Z (23 years, 3 months ago) by gbeauche
Branch: MAIN
CVS Tags: snapshot-15012002
Changes since 1.5: +12 -15 lines
Diff to previous 1.5 , to selected 1.1

- merge 680x0 emulation core with uae 0.8.17

- NEGX may use X & Z flags

Revision 1.4 - (view) (annotate) - [select for diffs]
2001-03-19T13:11:40Z (23 years, 8 months ago) by gbeauche
Branch: MAIN
CVS Tags: release-0_9-1, snapshot-29052001
Changes since 1.3: +12 -6 lines
Diff to previous 1.3 , to selected 1.1

Additions:
- MOVE16 (Ay)+,(xxx).L
- MOVE16 (xxx).L,(Ay)+
- MOVE16 (Ay),(xxx).L
- MOVE16 (xxx).L,(Ay)

Fixes:
- MOVE16 (Ax)+,(Ay)+ where x == y: address register shall be incremented
  only once
- CINV, CPUSH: 'p' field matches correctly the instruction 'cache field'

- fixed ADDQ and SUBQ bitmasks

Revision 1.2 - (view) (annotate) - [select for diffs]
1999-10-28T15:33:26Z (25 years, 1 month ago) by cebix
Branch: MAIN
CVS Tags: release-0_8-1, snapshot-02111999, snapshot-13072000, snapshot-22121999
Changes since 1.1: +11 -2 lines
Diff to previous 1.1

- added some 68040 instructions: CINV, CPUSH, MOVE16 (Ax)+,(Ay)+, MOVEC regs,
  and FPU state frames; enough to boot MacOS
- CPU type can be selected in GTK prefs editor

Initial revision