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root/cebix/BasiliskII/src/uae_cpu/table68k
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Comparing BasiliskII/src/uae_cpu/table68k (file contents):
Revision 1.2 by cebix, 1999-10-28T15:33:26Z vs.
Revision 1.6 by gbeauche, 2001-08-19T16:21:01Z

# Line 9 | Line 9
9   % J: immediate 0..15
10   % k: immediate 0..7
11   % K: immediate 0..63
12 + % p: immediate 0..3 (CINV and CPUSH: cache field)
13   % s: source mode
14   % S: source reg
15   % d: dest mode
# Line 24 | Line 25
25   %
26   % Arp: --> -(Ar)
27   % ArP: --> (Ar)+
28 + % L: (xxx).L
29   %
30   % Fields on a line:
31   % 16 chars bitpattern :
# Line 98 | Line 100
100   0011 DDDd ddss sSSS:00:-----:-----:12: MOVEA.W s,d[Areg]
101   0011 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.W  s,d[!Areg]
102  
103 < 0100 0000 zzdd dDDD:00:XxZxC:-----:30: NEGX.z  d[!Areg]
103 > 0100 0000 zzdd dDDD:00:XxZxC:X-Z--:30: NEGX.z  d[!Areg]
104   0100 0000 11dd dDDD:01:?????:?????:10: MVSR2.W d[!Areg]
105   0100 0010 zzdd dDDD:00:-0100:-----:20: CLR.z   d[!Areg]
106   0100 0010 11dd dDDD:10:?????:?????:10: MVSR2.B d[!Areg]
# Line 144 | Line 146
146   0100 1110 11ss sSSS:00://///://///:80: JMP.L   s[!Dreg,Areg,Aipi,Apdi,Immd]
147   0100 rrr1 11ss sSSS:00:-----:-----:02: LEA.L   s[!Dreg,Areg,Aipi,Apdi,Immd],Ar
148  
149 < 0101 jjj0 zzdd dDDD:00:-----:-----:13: ADDA.z  #j,d[Areg]      
149 > 0101 jjj0 01dd dDDD:00:-----:-----:13: ADDA.W  #j,d[Areg]      
150 > 0101 jjj0 10dd dDDD:00:-----:-----:13: ADDA.L  #j,d[Areg]      
151   0101 jjj0 zzdd dDDD:00:XNZVC:-----:13: ADD.z   #j,d[!Areg]
152 < 0101 jjj1 zzdd dDDD:00:-----:-----:13: SUBA.z  #j,d[Areg]      
152 > 0101 jjj1 01dd dDDD:00:-----:-----:13: SUBA.W  #j,d[Areg]      
153 > 0101 jjj1 10dd dDDD:00:-----:-----:13: SUBA.L  #j,d[Areg]      
154   0101 jjj1 zzdd dDDD:00:XNZVC:-----:13: SUB.z   #j,d[!Areg]
155 < 0101 cccc 1100 1rrr:00:-----:+++++:31: DBcc.W  Dr,#1
156 < 0101 cccc 11dd dDDD:00:-----:+++++:20: Scc.B   d[!Areg]
155 > 0101 cccc 1100 1rrr:00:-----:-++++:31: DBcc.W  Dr,#1
156 > 0101 cccc 11dd dDDD:00:-----:-++++:20: Scc.B   d[!Areg]
157   0101 cccc 1111 1010:20:?????:?????:10: TRAPcc  #1
158   0101 cccc 1111 1011:20:?????:?????:10: TRAPcc  #2
159   0101 cccc 1111 1100:20:?????:?????:00: TRAPcc
# Line 160 | Line 164
164   0110 0001 0000 0000:00://///://///:40: BSR.W   #1
165   0110 0001 IIII IIII:00://///://///:40: BSR.B   #i
166   0110 0001 1111 1111:00://///://///:40: BSR.L   #2
167 < 0110 CCCC 0000 0000:00:-----:+++++:40: Bcc.W   #1
168 < 0110 CCCC IIII IIII:00:-----:+++++:40: Bcc.B   #i
169 < 0110 CCCC 1111 1111:00:-----:+++++:40: Bcc.L   #2
167 > 0110 CCCC 0000 0000:00:-----:-++++:40: Bcc.W   #1
168 > 0110 CCCC IIII IIII:00:-----:-++++:40: Bcc.B   #i
169 > 0110 CCCC 1111 1111:00:-----:-++++:40: Bcc.L   #2
170  
171   0111 rrr0 iiii iiii:00:-NZ00:-----:12: MOVE.L  #i,Dr
172  
# Line 242 | Line 246
246   1111 0011 01ss sSSS:32:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd]
247  
248   % 68040 instructions
249 < 1111 0100 ii00 1rrr:42:-----:-----:02: CINVL    #i,Ar
250 < 1111 0100 ii01 0rrr:42:-----:-----:02: CINVP    #i,Ar
251 < 1111 0100 ii01 1rrr:42:-----:-----:00: CINVA    #i
252 < 1111 0100 ii10 1rrr:42:-----:-----:02: CPUSHL   #i,Ar
253 < 1111 0100 ii11 0rrr:42:-----:-----:02: CPUSHP   #i,Ar
254 < 1111 0100 ii11 1rrr:42:-----:-----:00: CPUSHA   #i
255 < 1111 0110 0010 0rrr:40:-----:-----:12: MOVE16   ArP,ARP
249 > 1111 0100 pp00 1rrr:42:-----:-----:02: CINVL    #p,Ar
250 > 1111 0100 pp01 0rrr:42:-----:-----:02: CINVP    #p,Ar
251 > 1111 0100 pp01 1rrr:42:-----:-----:00: CINVA    #p
252 > 1111 0100 pp10 1rrr:42:-----:-----:02: CPUSHL   #p,Ar
253 > 1111 0100 pp11 0rrr:42:-----:-----:02: CPUSHP   #p,Ar
254 > 1111 0100 pp11 1rrr:42:-----:-----:00: CPUSHA   #p
255 > % destination register number is encoded in the following word
256 > 1111 0110 0010 0rrr:40:-----:-----:12: MOVE16   ArP,AxP
257 > 1111 0110 00ss sSSS:40:-----:-----:12: MOVE16   s[Dreg-Aipi],L
258 > 1111 0110 00dd dDDD:40:-----:-----:12: MOVE16   L,d[Areg-Aipi]
259 > 1111 0110 00ss sSSS:40:-----:-----:12: MOVE16   s[Aind],L
260 > 1111 0110 00dd dDDD:40:-----:-----:12: MOVE16   L,d[Aipi-Aind]

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