| 1 |
cebix |
1.1 |
% 0: bit 0 |
| 2 |
|
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% 1: bit 1 |
| 3 |
|
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% c: condition code |
| 4 |
|
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% C: condition codes, except F |
| 5 |
|
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% f: direction |
| 6 |
|
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% i: immediate |
| 7 |
|
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% I: immediate, except 00 and ff |
| 8 |
|
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% j: immediate 1..8 |
| 9 |
|
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% J: immediate 0..15 |
| 10 |
|
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% k: immediate 0..7 |
| 11 |
|
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% K: immediate 0..63 |
| 12 |
gbeauche |
1.4 |
% p: immediate 0..3 (CINV and CPUSH: cache field) |
| 13 |
cebix |
1.1 |
% s: source mode |
| 14 |
|
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% S: source reg |
| 15 |
|
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% d: dest mode |
| 16 |
|
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% D: dest reg |
| 17 |
|
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% r: reg |
| 18 |
|
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% z: size |
| 19 |
|
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% |
| 20 |
|
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% Actually, a sssSSS may appear as a destination, and |
| 21 |
|
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% vice versa. The only difference between sssSSS and |
| 22 |
|
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% dddDDD are the valid addressing modes. There is |
| 23 |
|
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% no match for immediate and pc-rel. addressing modes |
| 24 |
|
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% in case of dddDDD. |
| 25 |
|
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% |
| 26 |
|
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% Arp: --> -(Ar) |
| 27 |
|
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% ArP: --> (Ar)+ |
| 28 |
gbeauche |
1.6 |
% L: (xxx).L |
| 29 |
cebix |
1.1 |
% |
| 30 |
|
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% Fields on a line: |
| 31 |
|
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% 16 chars bitpattern : |
| 32 |
cebix |
1.2 |
% CPU level / privilege level : |
| 33 |
cebix |
1.1 |
% CPU level 0: 68000 |
| 34 |
|
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% 1: 68010 |
| 35 |
|
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% 2: 68020 |
| 36 |
cebix |
1.2 |
% 3: 68020/68881 |
| 37 |
|
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% 4: 68040 |
| 38 |
cebix |
1.1 |
% privilege level 0: not privileged |
| 39 |
|
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% 1: unprivileged only on 68000 (check regs.s) |
| 40 |
|
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% 2: privileged (check regs.s) |
| 41 |
|
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% 3: privileged if size == word (check regs.s) |
| 42 |
|
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% Flags set by instruction: XNZVC : |
| 43 |
|
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% Flags used by instruction: XNZVC : |
| 44 |
|
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% - means flag unaffected / unused |
| 45 |
|
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% 0 means flag reset |
| 46 |
|
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% 1 means flag set |
| 47 |
|
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% ? means programmer was too lazy to check or instruction may trap |
| 48 |
|
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% + means instruction is conditional branch |
| 49 |
|
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% everything else means flag set/used |
| 50 |
|
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% / means instruction is unconditional branch/call |
| 51 |
|
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% x means flag is unknown and well-behaved programs shouldn't check it |
| 52 |
|
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% srcaddr status destaddr status : |
| 53 |
|
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% bitmasks of |
| 54 |
|
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% 1 means fetched |
| 55 |
|
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% 2 means stored |
| 56 |
|
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% 4 means jump offset |
| 57 |
|
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% 8 means jump address |
| 58 |
|
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% instruction |
| 59 |
|
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% |
| 60 |
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| 61 |
|
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0000 0000 0011 1100:00:XNZVC:XNZVC:10: ORSR.B #1 |
| 62 |
|
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0000 0000 0111 1100:02:?????:?????:10: ORSR.W #1 |
| 63 |
|
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0000 0zz0 11ss sSSS:20:?????:?????:11: CHK2.z #1,s[!Dreg,Areg,Aipi,Apdi,Immd] |
| 64 |
|
|
0000 0000 zzdd dDDD:00:-NZ00:-----:13: OR.z #z,d[!Areg] |
| 65 |
|
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0000 0010 0011 1100:00:XNZVC:XNZVC:10: ANDSR.B #1 |
| 66 |
|
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0000 0010 0111 1100:02:?????:?????:10: ANDSR.W #1 |
| 67 |
|
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0000 0010 zzdd dDDD:00:-NZ00:-----:13: AND.z #z,d[!Areg] |
| 68 |
|
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0000 0100 zzdd dDDD:00:XNZVC:-----:13: SUB.z #z,d[!Areg] |
| 69 |
|
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0000 0110 zzdd dDDD:00:XNZVC:-----:13: ADD.z #z,d[!Areg] |
| 70 |
|
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0000 0110 11ss sSSS:20:?????:?????:10: CALLM s[!Dreg,Areg,Aipi,Apdi,Immd] |
| 71 |
|
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0000 0110 11ss sSSS:20:?????:?????:10: RTM s[Dreg,Areg] |
| 72 |
|
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0000 1000 00ss sSSS:00:--Z--:-----:11: BTST #1,s[!Areg] |
| 73 |
|
|
0000 1000 01ss sSSS:00:--Z--:-----:13: BCHG #1,s[!Areg,Immd] |
| 74 |
|
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0000 1000 10ss sSSS:00:--Z--:-----:13: BCLR #1,s[!Areg,Immd] |
| 75 |
|
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0000 1000 11ss sSSS:00:--Z--:-----:13: BSET #1,s[!Areg,Immd] |
| 76 |
|
|
0000 1010 0011 1100:00:XNZVC:XNZVC:10: EORSR.B #1 |
| 77 |
|
|
0000 1010 0111 1100:02:?????:?????:10: EORSR.W #1 |
| 78 |
|
|
0000 1010 zzdd dDDD:00:-NZ00:-----:13: EOR.z #z,d[!Areg] |
| 79 |
|
|
0000 1100 zzss sSSS:00:-NZVC:-----:11: CMP.z #z,s[!Areg,Immd] |
| 80 |
|
|
|
| 81 |
|
|
0000 1010 11ss sSSS:20:?????:?????:13: CAS.B #1,s[!Dreg,Areg,Immd,PC8r,PC16] |
| 82 |
|
|
0000 1100 11ss sSSS:20:?????:?????:13: CAS.W #1,s[!Dreg,Areg,Immd,PC8r,PC16] |
| 83 |
|
|
0000 1100 1111 1100:20:?????:?????:10: CAS2.W #2 |
| 84 |
|
|
0000 1110 zzss sSSS:22:?????:?????:13: MOVES.z #1,s[!Dreg,Areg,Immd,PC8r,PC16] |
| 85 |
|
|
0000 1110 11ss sSSS:20:?????:?????:13: CAS.L #1,s[!Dreg,Areg,Immd,PC8r,PC16] |
| 86 |
|
|
0000 1110 1111 1100:20:?????:?????:10: CAS2.L #2 |
| 87 |
|
|
|
| 88 |
|
|
0000 rrr1 00dd dDDD:00:-----:-----:12: MVPMR.W d[Areg-Ad16],Dr |
| 89 |
|
|
0000 rrr1 01dd dDDD:00:-----:-----:12: MVPMR.L d[Areg-Ad16],Dr |
| 90 |
|
|
0000 rrr1 10dd dDDD:00:-----:-----:12: MVPRM.W Dr,d[Areg-Ad16] |
| 91 |
|
|
0000 rrr1 11dd dDDD:00:-----:-----:12: MVPRM.L Dr,d[Areg-Ad16] |
| 92 |
|
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0000 rrr1 00ss sSSS:00:--Z--:-----:11: BTST Dr,s[!Areg] |
| 93 |
|
|
0000 rrr1 01ss sSSS:00:--Z--:-----:13: BCHG Dr,s[!Areg,Immd] |
| 94 |
|
|
0000 rrr1 10ss sSSS:00:--Z--:-----:13: BCLR Dr,s[!Areg,Immd] |
| 95 |
|
|
0000 rrr1 11ss sSSS:00:--Z--:-----:13: BSET Dr,s[!Areg,Immd] |
| 96 |
|
|
|
| 97 |
|
|
0001 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.B s,d[!Areg] |
| 98 |
|
|
0010 DDDd ddss sSSS:00:-----:-----:12: MOVEA.L s,d[Areg] |
| 99 |
|
|
0010 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.L s,d[!Areg] |
| 100 |
|
|
0011 DDDd ddss sSSS:00:-----:-----:12: MOVEA.W s,d[Areg] |
| 101 |
|
|
0011 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.W s,d[!Areg] |
| 102 |
|
|
|
| 103 |
gbeauche |
1.5 |
0100 0000 zzdd dDDD:00:XxZxC:X-Z--:30: NEGX.z d[!Areg] |
| 104 |
cebix |
1.1 |
0100 0000 11dd dDDD:01:?????:?????:10: MVSR2.W d[!Areg] |
| 105 |
|
|
0100 0010 zzdd dDDD:00:-0100:-----:20: CLR.z d[!Areg] |
| 106 |
|
|
0100 0010 11dd dDDD:10:?????:?????:10: MVSR2.B d[!Areg] |
| 107 |
|
|
0100 0100 zzdd dDDD:00:XNZVC:-----:30: NEG.z d[!Areg] |
| 108 |
|
|
0100 0100 11ss sSSS:00:XNZVC:-----:10: MV2SR.B s[!Areg] |
| 109 |
|
|
0100 0110 zzdd dDDD:00:-NZ00:-----:30: NOT.z d[!Areg] |
| 110 |
|
|
0100 0110 11ss sSSS:02:?????:?????:10: MV2SR.W s[!Areg] |
| 111 |
|
|
0100 1000 0000 1rrr:20:-----:-----:31: LINK.L Ar,#2 |
| 112 |
|
|
0100 1000 00dd dDDD:00:X?Z?C:X-Z--:30: NBCD.B d[!Areg] |
| 113 |
|
|
0100 1000 0100 1kkk:20:?????:?????:10: BKPT #k |
| 114 |
|
|
0100 1000 01ss sSSS:00:-NZ00:-----:30: SWAP.W s[Dreg] |
| 115 |
|
|
0100 1000 01ss sSSS:00:-----:-----:00: PEA.L s[!Dreg,Areg,Aipi,Apdi,Immd] |
| 116 |
|
|
0100 1000 10dd dDDD:00:-NZ00:-----:30: EXT.W d[Dreg] |
| 117 |
|
|
0100 1000 10dd dDDD:00:-----:-----:02: MVMLE.W #1,d[!Dreg,Areg,Aipi] |
| 118 |
|
|
0100 1000 11dd dDDD:00:-NZ00:-----:30: EXT.L d[Dreg] |
| 119 |
|
|
0100 1000 11dd dDDD:00:-----:-----:02: MVMLE.L #1,d[!Dreg,Areg,Aipi] |
| 120 |
|
|
0100 1001 11dd dDDD:00:-NZ00:-----:30: EXT.B d[Dreg] |
| 121 |
|
|
0100 1010 zzss sSSS:00:-NZ00:-----:10: TST.z s |
| 122 |
|
|
0100 1010 11dd dDDD:00:?????:?????:30: TAS.B d[!Areg] |
| 123 |
|
|
0100 1010 1111 1100:00:?????:?????:00: ILLEGAL |
| 124 |
|
|
0100 1100 00ss sSSS:20:-NZVC:-----:13: MULL.L #1,s[!Areg] |
| 125 |
|
|
0100 1100 01ss sSSS:20:?????:?????:13: DIVL.L #1,s[!Areg] |
| 126 |
|
|
0100 1100 10ss sSSS:00:-----:-----:01: MVMEL.W #1,s[!Dreg,Areg,Apdi,Immd] |
| 127 |
|
|
0100 1100 11ss sSSS:00:-----:-----:01: MVMEL.L #1,s[!Dreg,Areg,Apdi,Immd] |
| 128 |
|
|
0100 1110 0100 JJJJ:00:-----:XNZVC:10: TRAP #J |
| 129 |
|
|
0100 1110 0101 0rrr:00:-----:-----:31: LINK.W Ar,#1 |
| 130 |
|
|
0100 1110 0101 1rrr:00:-----:-----:30: UNLK.L Ar |
| 131 |
|
|
0100 1110 0110 0rrr:02:-----:-----:10: MVR2USP.L Ar |
| 132 |
|
|
0100 1110 0110 1rrr:02:-----:-----:20: MVUSP2R.L Ar |
| 133 |
|
|
0100 1110 0111 0000:02:-----:-----:00: RESET |
| 134 |
|
|
0100 1110 0111 0001:00:-----:-----:00: NOP |
| 135 |
|
|
0100 1110 0111 0010:02:XNZVC:-----:10: STOP #1 |
| 136 |
|
|
0100 1110 0111 0011:02:XNZVC:-----:00: RTE |
| 137 |
|
|
0100 1110 0111 0100:00:?????:?????:10: RTD #1 |
| 138 |
|
|
0100 1110 0111 0101:00:-----:-----:00: RTS |
| 139 |
|
|
0100 1110 0111 0110:00:-----:XNZVC:00: TRAPV |
| 140 |
|
|
0100 1110 0111 0111:00:XNZVC:-----:00: RTR |
| 141 |
|
|
0100 1110 0111 1010:12:?????:?????:10: MOVEC2 #1 |
| 142 |
|
|
0100 1110 0111 1011:12:?????:?????:10: MOVE2C #1 |
| 143 |
|
|
0100 1110 10ss sSSS:00://///://///:80: JSR.L s[!Dreg,Areg,Aipi,Apdi,Immd] |
| 144 |
|
|
0100 rrr1 00ss sSSS:00:?????:?????:11: CHK.L s[!Areg],Dr |
| 145 |
|
|
0100 rrr1 10ss sSSS:00:?????:?????:11: CHK.W s[!Areg],Dr |
| 146 |
|
|
0100 1110 11ss sSSS:00://///://///:80: JMP.L s[!Dreg,Areg,Aipi,Apdi,Immd] |
| 147 |
|
|
0100 rrr1 11ss sSSS:00:-----:-----:02: LEA.L s[!Dreg,Areg,Aipi,Apdi,Immd],Ar |
| 148 |
|
|
|
| 149 |
gbeauche |
1.3 |
0101 jjj0 01dd dDDD:00:-----:-----:13: ADDA.W #j,d[Areg] |
| 150 |
|
|
0101 jjj0 10dd dDDD:00:-----:-----:13: ADDA.L #j,d[Areg] |
| 151 |
cebix |
1.1 |
0101 jjj0 zzdd dDDD:00:XNZVC:-----:13: ADD.z #j,d[!Areg] |
| 152 |
gbeauche |
1.3 |
0101 jjj1 01dd dDDD:00:-----:-----:13: SUBA.W #j,d[Areg] |
| 153 |
|
|
0101 jjj1 10dd dDDD:00:-----:-----:13: SUBA.L #j,d[Areg] |
| 154 |
cebix |
1.1 |
0101 jjj1 zzdd dDDD:00:XNZVC:-----:13: SUB.z #j,d[!Areg] |
| 155 |
gbeauche |
1.6 |
0101 cccc 1100 1rrr:00:-----:-++++:31: DBcc.W Dr,#1 |
| 156 |
|
|
0101 cccc 11dd dDDD:00:-----:-++++:20: Scc.B d[!Areg] |
| 157 |
cebix |
1.1 |
0101 cccc 1111 1010:20:?????:?????:10: TRAPcc #1 |
| 158 |
|
|
0101 cccc 1111 1011:20:?????:?????:10: TRAPcc #2 |
| 159 |
|
|
0101 cccc 1111 1100:20:?????:?????:00: TRAPcc |
| 160 |
|
|
|
| 161 |
|
|
% Bxx.L is 68020 only, but setting the CPU level to 2 would give illegal |
| 162 |
|
|
% instruction exceptions when compiling a 68000 only emulation, which isn't |
| 163 |
|
|
% what we want either. |
| 164 |
|
|
0110 0001 0000 0000:00://///://///:40: BSR.W #1 |
| 165 |
|
|
0110 0001 IIII IIII:00://///://///:40: BSR.B #i |
| 166 |
|
|
0110 0001 1111 1111:00://///://///:40: BSR.L #2 |
| 167 |
gbeauche |
1.6 |
0110 CCCC 0000 0000:00:-----:-++++:40: Bcc.W #1 |
| 168 |
|
|
0110 CCCC IIII IIII:00:-----:-++++:40: Bcc.B #i |
| 169 |
|
|
0110 CCCC 1111 1111:00:-----:-++++:40: Bcc.L #2 |
| 170 |
cebix |
1.1 |
|
| 171 |
|
|
0111 rrr0 iiii iiii:00:-NZ00:-----:12: MOVE.L #i,Dr |
| 172 |
|
|
|
| 173 |
|
|
1000 rrr0 zzss sSSS:00:-NZ00:-----:13: OR.z s[!Areg],Dr |
| 174 |
|
|
1000 rrr0 11ss sSSS:00:?????:?????:13: DIVU.W s[!Areg],Dr |
| 175 |
|
|
1000 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: SBCD.B d[Dreg],Dr |
| 176 |
|
|
1000 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: SBCD.B d[Areg-Apdi],Arp |
| 177 |
|
|
1000 rrr1 zzdd dDDD:00:-NZ00:-----:13: OR.z Dr,d[!Areg,Dreg] |
| 178 |
|
|
1000 rrr1 01dd dDDD:20:?????:?????:12: PACK d[Dreg],Dr |
| 179 |
|
|
1000 rrr1 01dd dDDD:20:?????:?????:12: PACK d[Areg-Apdi],Arp |
| 180 |
|
|
1000 rrr1 10dd dDDD:20:?????:?????:12: UNPK d[Dreg],Dr |
| 181 |
|
|
1000 rrr1 10dd dDDD:20:?????:?????:12: UNPK d[Areg-Apdi],Arp |
| 182 |
|
|
1000 rrr1 11ss sSSS:00:?????:?????:13: DIVS.W s[!Areg],Dr |
| 183 |
|
|
|
| 184 |
|
|
1001 rrr0 zzss sSSS:00:XNZVC:-----:13: SUB.z s,Dr |
| 185 |
|
|
1001 rrr0 11ss sSSS:00:-----:-----:13: SUBA.W s,Ar |
| 186 |
|
|
1001 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: SUBX.z d[Dreg],Dr |
| 187 |
|
|
1001 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: SUBX.z d[Areg-Apdi],Arp |
| 188 |
|
|
1001 rrr1 zzdd dDDD:00:XNZVC:-----:13: SUB.z Dr,d[!Areg,Dreg] |
| 189 |
|
|
1001 rrr1 11ss sSSS:00:-----:-----:13: SUBA.L s,Ar |
| 190 |
|
|
|
| 191 |
|
|
1011 rrr0 zzss sSSS:00:-NZVC:-----:11: CMP.z s,Dr |
| 192 |
|
|
1011 rrr0 11ss sSSS:00:-NZVC:-----:11: CMPA.W s,Ar |
| 193 |
|
|
1011 rrr1 11ss sSSS:00:-NZVC:-----:11: CMPA.L s,Ar |
| 194 |
|
|
1011 rrr1 zzdd dDDD:00:-NZVC:-----:11: CMPM.z d[Areg-Aipi],ArP |
| 195 |
|
|
1011 rrr1 zzdd dDDD:00:-NZ00:-----:13: EOR.z Dr,d[!Areg] |
| 196 |
|
|
|
| 197 |
|
|
1100 rrr0 zzss sSSS:00:-NZ00:-----:13: AND.z s[!Areg],Dr |
| 198 |
|
|
1100 rrr0 11ss sSSS:00:-NZ00:-----:13: MULU.W s[!Areg],Dr |
| 199 |
|
|
1100 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: ABCD.B d[Dreg],Dr |
| 200 |
|
|
1100 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: ABCD.B d[Areg-Apdi],Arp |
| 201 |
|
|
1100 rrr1 zzdd dDDD:00:-NZ00:-----:13: AND.z Dr,d[!Areg,Dreg] |
| 202 |
|
|
1100 rrr1 01dd dDDD:00:-----:-----:33: EXG.L Dr,d[Dreg] |
| 203 |
|
|
1100 rrr1 01dd dDDD:00:-----:-----:33: EXG.L Ar,d[Areg] |
| 204 |
|
|
1100 rrr1 10dd dDDD:00:-----:-----:33: EXG.L Dr,d[Areg] |
| 205 |
|
|
1100 rrr1 11ss sSSS:00:-NZ00:-----:13: MULS.W s[!Areg],Dr |
| 206 |
|
|
|
| 207 |
|
|
1101 rrr0 zzss sSSS:00:XNZVC:-----:13: ADD.z s,Dr |
| 208 |
|
|
1101 rrr0 11ss sSSS:00:-----:-----:13: ADDA.W s,Ar |
| 209 |
|
|
1101 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: ADDX.z d[Dreg],Dr |
| 210 |
|
|
1101 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: ADDX.z d[Areg-Apdi],Arp |
| 211 |
|
|
1101 rrr1 zzdd dDDD:00:XNZVC:-----:13: ADD.z Dr,d[!Areg,Dreg] |
| 212 |
|
|
1101 rrr1 11ss sSSS:00:-----:-----:13: ADDA.L s,Ar |
| 213 |
|
|
|
| 214 |
|
|
1110 jjjf zz00 0RRR:00:XNZVC:-----:13: ASf.z #j,DR |
| 215 |
|
|
1110 jjjf zz00 1RRR:00:XNZ0C:-----:13: LSf.z #j,DR |
| 216 |
|
|
1110 jjjf zz01 0RRR:00:XNZ0C:X----:13: ROXf.z #j,DR |
| 217 |
|
|
1110 jjjf zz01 1RRR:00:-NZ0C:-----:13: ROf.z #j,DR |
| 218 |
|
|
1110 rrrf zz10 0RRR:00:XNZVC:X----:13: ASf.z Dr,DR |
| 219 |
|
|
1110 rrrf zz10 1RRR:00:XNZ0C:X----:13: LSf.z Dr,DR |
| 220 |
|
|
1110 rrrf zz11 0RRR:00:XNZ0C:X----:13: ROXf.z Dr,DR |
| 221 |
|
|
1110 rrrf zz11 1RRR:00:-NZ0C:-----:13: ROf.z Dr,DR |
| 222 |
|
|
1110 000f 11dd dDDD:00:XNZVC:-----:13: ASfW.W d[!Dreg,Areg] |
| 223 |
|
|
1110 001f 11dd dDDD:00:XNZ0C:-----:13: LSfW.W d[!Dreg,Areg] |
| 224 |
|
|
1110 010f 11dd dDDD:00:XNZ0C:X----:13: ROXfW.W d[!Dreg,Areg] |
| 225 |
|
|
1110 011f 11dd dDDD:00:-NZ0C:-----:13: ROfW.W d[!Dreg,Areg] |
| 226 |
|
|
|
| 227 |
|
|
1110 1000 11ss sSSS:20:?????:?????:11: BFTST #1,s[!Areg,Apdi,Aipi,Immd] |
| 228 |
|
|
1110 1001 11ss sSSS:20:?????:?????:11: BFEXTU #1,s[!Areg,Apdi,Aipi,Immd] |
| 229 |
|
|
1110 1010 11ss sSSS:20:?????:?????:13: BFCHG #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16] |
| 230 |
|
|
1110 1011 11ss sSSS:20:?????:?????:11: BFEXTS #1,s[!Areg,Apdi,Aipi,Immd] |
| 231 |
|
|
1110 1100 11ss sSSS:20:?????:?????:13: BFCLR #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16] |
| 232 |
|
|
1110 1101 11ss sSSS:20:?????:?????:11: BFFFO #1,s[!Areg,Apdi,Aipi,Immd] |
| 233 |
|
|
1110 1110 11ss sSSS:20:?????:?????:13: BFSET #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16] |
| 234 |
|
|
1110 1111 11ss sSSS:20:?????:?????:13: BFINS #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16] |
| 235 |
|
|
|
| 236 |
|
|
% floating point co processor |
| 237 |
|
|
1111 0010 00ss sSSS:30:?????:?????:11: FPP #1,s |
| 238 |
|
|
1111 0010 01ss sSSS:30:?????:?????:11: FDBcc #1,s[Areg-Dreg] |
| 239 |
|
|
1111 0010 01ss sSSS:30:?????:?????:11: FScc #1,s[!Areg,Immd,PC8r,PC16] |
| 240 |
|
|
1111 0010 0111 1010:30:?????:?????:10: FTRAPcc #1 |
| 241 |
|
|
1111 0010 0111 1011:30:?????:?????:10: FTRAPcc #2 |
| 242 |
|
|
1111 0010 0111 1100:30:?????:?????:00: FTRAPcc |
| 243 |
|
|
1111 0010 10KK KKKK:30:?????:?????:11: FBcc #K,#1 |
| 244 |
|
|
1111 0010 11KK KKKK:30:?????:?????:11: FBcc #K,#2 |
| 245 |
|
|
1111 0011 00ss sSSS:32:?????:?????:20: FSAVE s[!Dreg,Areg,Aipi,Immd,PC8r,PC16] |
| 246 |
|
|
1111 0011 01ss sSSS:32:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd] |
| 247 |
|
|
|
| 248 |
cebix |
1.2 |
% 68040 instructions |
| 249 |
gbeauche |
1.4 |
1111 0100 pp00 1rrr:42:-----:-----:02: CINVL #p,Ar |
| 250 |
|
|
1111 0100 pp01 0rrr:42:-----:-----:02: CINVP #p,Ar |
| 251 |
|
|
1111 0100 pp01 1rrr:42:-----:-----:00: CINVA #p |
| 252 |
|
|
1111 0100 pp10 1rrr:42:-----:-----:02: CPUSHL #p,Ar |
| 253 |
|
|
1111 0100 pp11 0rrr:42:-----:-----:02: CPUSHP #p,Ar |
| 254 |
|
|
1111 0100 pp11 1rrr:42:-----:-----:00: CPUSHA #p |
| 255 |
gbeauche |
1.6 |
% destination register number is encoded in the following word |
| 256 |
|
|
1111 0110 0010 0rrr:40:-----:-----:12: MOVE16 ArP,AxP |
| 257 |
|
|
1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Dreg-Aipi],L |
| 258 |
|
|
1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 L,d[Areg-Aipi] |
| 259 |
|
|
1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Aind],L |
| 260 |
|
|
1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 L,d[Aipi-Aind] |
