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root/cebix/BasiliskII/src/uae_cpu/readcpu.cpp
Revision: 1.9
Committed: 2005-06-06T19:22:56Z (19 years, 5 months ago) by gbeauche
Branch: MAIN
CVS Tags: nigel-build-19, nigel-build-17
Changes since 1.8: +28 -51 lines
Log Message:
Really make translation through constant jumps functional. This can be
disabled with the new prefs item "jitinline". Some rapid Speedometer 4
benchmarks showed only a 4% improvement.

File Contents

# User Rev Content
1 cebix 1.1 /*
2     * UAE - The Un*x Amiga Emulator
3     *
4     * Read 68000 CPU specs from file "table68k"
5     *
6     * Copyright 1995,1996 Bernd Schmidt
7     */
8    
9     #include <stdio.h>
10     #include <stdlib.h>
11     #include <string.h>
12     #include <ctype.h>
13    
14     #include "sysdeps.h"
15     #include "readcpu.h"
16    
17     int nr_cpuop_funcs;
18    
19     struct mnemolookup lookuptab[] = {
20     { i_ILLG, "ILLEGAL" },
21     { i_OR, "OR" },
22     { i_CHK, "CHK" },
23     { i_CHK2, "CHK2" },
24     { i_AND, "AND" },
25     { i_EOR, "EOR" },
26     { i_ORSR, "ORSR" },
27     { i_ANDSR, "ANDSR" },
28     { i_EORSR, "EORSR" },
29     { i_SUB, "SUB" },
30     { i_SUBA, "SUBA" },
31     { i_SUBX, "SUBX" },
32     { i_SBCD, "SBCD" },
33     { i_ADD, "ADD" },
34     { i_ADDA, "ADDA" },
35     { i_ADDX, "ADDX" },
36     { i_ABCD, "ABCD" },
37     { i_NEG, "NEG" },
38     { i_NEGX, "NEGX" },
39     { i_NBCD, "NBCD" },
40     { i_CLR, "CLR" },
41     { i_NOT, "NOT" },
42     { i_TST, "TST" },
43     { i_BTST, "BTST" },
44     { i_BCHG, "BCHG" },
45     { i_BCLR, "BCLR" },
46     { i_BSET, "BSET" },
47     { i_CMP, "CMP" },
48     { i_CMPM, "CMPM" },
49     { i_CMPA, "CMPA" },
50     { i_MVPRM, "MVPRM" },
51     { i_MVPMR, "MVPMR" },
52     { i_MOVE, "MOVE" },
53     { i_MOVEA, "MOVEA" },
54     { i_MVSR2, "MVSR2" },
55     { i_MV2SR, "MV2SR" },
56     { i_SWAP, "SWAP" },
57     { i_EXG, "EXG" },
58     { i_EXT, "EXT" },
59     { i_MVMEL, "MVMEL" },
60     { i_MVMLE, "MVMLE" },
61     { i_TRAP, "TRAP" },
62     { i_MVR2USP, "MVR2USP" },
63     { i_MVUSP2R, "MVUSP2R" },
64     { i_NOP, "NOP" },
65     { i_RESET, "RESET" },
66     { i_RTE, "RTE" },
67     { i_RTD, "RTD" },
68     { i_LINK, "LINK" },
69     { i_UNLK, "UNLK" },
70     { i_RTS, "RTS" },
71     { i_STOP, "STOP" },
72     { i_TRAPV, "TRAPV" },
73     { i_RTR, "RTR" },
74     { i_JSR, "JSR" },
75     { i_JMP, "JMP" },
76     { i_BSR, "BSR" },
77     { i_Bcc, "Bcc" },
78     { i_LEA, "LEA" },
79     { i_PEA, "PEA" },
80     { i_DBcc, "DBcc" },
81     { i_Scc, "Scc" },
82     { i_DIVU, "DIVU" },
83     { i_DIVS, "DIVS" },
84     { i_MULU, "MULU" },
85     { i_MULS, "MULS" },
86     { i_ASR, "ASR" },
87     { i_ASL, "ASL" },
88     { i_LSR, "LSR" },
89     { i_LSL, "LSL" },
90     { i_ROL, "ROL" },
91     { i_ROR, "ROR" },
92     { i_ROXL, "ROXL" },
93     { i_ROXR, "ROXR" },
94     { i_ASRW, "ASRW" },
95     { i_ASLW, "ASLW" },
96     { i_LSRW, "LSRW" },
97     { i_LSLW, "LSLW" },
98     { i_ROLW, "ROLW" },
99     { i_RORW, "RORW" },
100     { i_ROXLW, "ROXLW" },
101     { i_ROXRW, "ROXRW" },
102    
103     { i_MOVE2C, "MOVE2C" },
104     { i_MOVEC2, "MOVEC2" },
105     { i_CAS, "CAS" },
106     { i_CAS2, "CAS2" },
107     { i_MULL, "MULL" },
108     { i_DIVL, "DIVL" },
109     { i_BFTST, "BFTST" },
110     { i_BFEXTU, "BFEXTU" },
111     { i_BFCHG, "BFCHG" },
112     { i_BFEXTS, "BFEXTS" },
113     { i_BFCLR, "BFCLR" },
114     { i_BFFFO, "BFFFO" },
115     { i_BFSET, "BFSET" },
116     { i_BFINS, "BFINS" },
117     { i_PACK, "PACK" },
118     { i_UNPK, "UNPK" },
119     { i_TAS, "TAS" },
120     { i_BKPT, "BKPT" },
121     { i_CALLM, "CALLM" },
122     { i_RTM, "RTM" },
123     { i_TRAPcc, "TRAPcc" },
124     { i_MOVES, "MOVES" },
125     { i_FPP, "FPP" },
126     { i_FDBcc, "FDBcc" },
127     { i_FScc, "FScc" },
128     { i_FTRAPcc, "FTRAPcc" },
129     { i_FBcc, "FBcc" },
130     { i_FBcc, "FBcc" },
131     { i_FSAVE, "FSAVE" },
132     { i_FRESTORE, "FRESTORE" },
133 cebix 1.2
134     { i_CINVL, "CINVL" },
135     { i_CINVP, "CINVP" },
136     { i_CINVA, "CINVA" },
137     { i_CPUSHL, "CPUSHL" },
138     { i_CPUSHP, "CPUSHP" },
139     { i_CPUSHA, "CPUSHA" },
140     { i_MOVE16, "MOVE16" },
141    
142 gbeauche 1.5 { i_EMULOP_RETURN, "EMULOP_RETURN" },
143     { i_EMULOP, "EMULOP" },
144    
145 cebix 1.1 { i_MMUOP, "MMUOP" },
146     { i_ILLG, "" },
147     };
148    
149     struct instr *table68k;
150    
151     static __inline__ amodes mode_from_str (const char *str)
152     {
153     if (strncmp (str, "Dreg", 4) == 0) return Dreg;
154     if (strncmp (str, "Areg", 4) == 0) return Areg;
155     if (strncmp (str, "Aind", 4) == 0) return Aind;
156     if (strncmp (str, "Apdi", 4) == 0) return Apdi;
157     if (strncmp (str, "Aipi", 4) == 0) return Aipi;
158     if (strncmp (str, "Ad16", 4) == 0) return Ad16;
159     if (strncmp (str, "Ad8r", 4) == 0) return Ad8r;
160     if (strncmp (str, "absw", 4) == 0) return absw;
161     if (strncmp (str, "absl", 4) == 0) return absl;
162     if (strncmp (str, "PC16", 4) == 0) return PC16;
163     if (strncmp (str, "PC8r", 4) == 0) return PC8r;
164     if (strncmp (str, "Immd", 4) == 0) return imm;
165     abort ();
166     return (amodes)0;
167     }
168    
169     static __inline__ amodes mode_from_mr (int mode, int reg)
170     {
171     switch (mode) {
172     case 0: return Dreg;
173     case 1: return Areg;
174     case 2: return Aind;
175     case 3: return Aipi;
176     case 4: return Apdi;
177     case 5: return Ad16;
178     case 6: return Ad8r;
179     case 7:
180     switch (reg) {
181     case 0: return absw;
182     case 1: return absl;
183     case 2: return PC16;
184     case 3: return PC8r;
185     case 4: return imm;
186     case 5:
187     case 6:
188     case 7: return am_illg;
189     }
190     }
191     abort ();
192     return (amodes)0;
193     }
194    
195     static void build_insn (int insn)
196     {
197     int find = -1;
198     int variants;
199     struct instr_def id;
200     const char *opcstr;
201 gbeauche 1.5 int i, n;
202 cebix 1.1
203     int flaglive = 0, flagdead = 0;
204 gbeauche 1.5 int cflow = 0;
205 cebix 1.1
206     id = defs68k[insn];
207    
208 gbeauche 1.5 // Control flow information
209     cflow = id.cflow;
210    
211     // Mask of flags set/used
212     unsigned char flags_set(0), flags_used(0);
213    
214     for (i = 0, n = 4; i < 5; i++, n--) {
215     switch (id.flaginfo[i].flagset) {
216     case fa_unset: case fa_isjmp: break;
217     default: flags_set |= (1 << n);
218     }
219    
220     switch (id.flaginfo[i].flaguse) {
221     case fu_unused: case fu_isjmp: break;
222     default: flags_used |= (1 << n);
223     }
224     }
225    
226 cebix 1.1 for (i = 0; i < 5; i++) {
227     switch (id.flaginfo[i].flagset){
228     case fa_unset: break;
229     case fa_zero: flagdead |= 1 << i; break;
230     case fa_one: flagdead |= 1 << i; break;
231     case fa_dontcare: flagdead |= 1 << i; break;
232     case fa_unknown: flagdead = -1; goto out1;
233     case fa_set: flagdead |= 1 << i; break;
234     }
235     }
236    
237     out1:
238     for (i = 0; i < 5; i++) {
239     switch (id.flaginfo[i].flaguse) {
240     case fu_unused: break;
241     case fu_unknown: flaglive = -1; goto out2;
242     case fu_used: flaglive |= 1 << i; break;
243     }
244     }
245     out2:
246    
247     opcstr = id.opcstr;
248     for (variants = 0; variants < (1 << id.n_variable); variants++) {
249     int bitcnt[lastbit];
250     int bitval[lastbit];
251     int bitpos[lastbit];
252     int i;
253     uae_u16 opc = id.bits;
254     uae_u16 msk, vmsk;
255     int pos = 0;
256     int mnp = 0;
257     int bitno = 0;
258 gbeauche 1.8 char mnemonic[64];
259 cebix 1.1
260     wordsizes sz = sz_long;
261     int srcgather = 0, dstgather = 0;
262     int usesrc = 0, usedst = 0;
263     int srctype = 0;
264     int srcpos = -1, dstpos = -1;
265    
266     amodes srcmode = am_unknown, destmode = am_unknown;
267     int srcreg = -1, destreg = -1;
268    
269     for (i = 0; i < lastbit; i++)
270     bitcnt[i] = bitval[i] = 0;
271    
272     vmsk = 1 << id.n_variable;
273    
274     for (i = 0, msk = 0x8000; i < 16; i++, msk >>= 1) {
275     if (!(msk & id.mask)) {
276     int currbit = id.bitpos[bitno++];
277     int bit_set;
278     vmsk >>= 1;
279     bit_set = variants & vmsk ? 1 : 0;
280     if (bit_set)
281     opc |= msk;
282     bitpos[currbit] = 15 - i;
283     bitcnt[currbit]++;
284     bitval[currbit] <<= 1;
285     bitval[currbit] |= bit_set;
286     }
287     }
288    
289     if (bitval[bitj] == 0) bitval[bitj] = 8;
290     /* first check whether this one does not match after all */
291     if (bitval[bitz] == 3 || bitval[bitC] == 1)
292     continue;
293     if (bitcnt[bitI] && (bitval[bitI] == 0x00 || bitval[bitI] == 0xff))
294     continue;
295 gbeauche 1.5 if (bitcnt[bitE] && (bitval[bitE] == 0x00))
296     continue;
297 cebix 1.1
298     /* bitI and bitC get copied to biti and bitc */
299     if (bitcnt[bitI]) {
300     bitval[biti] = bitval[bitI]; bitpos[biti] = bitpos[bitI];
301     }
302     if (bitcnt[bitC])
303     bitval[bitc] = bitval[bitC];
304    
305     pos = 0;
306     while (opcstr[pos] && !isspace(opcstr[pos])) {
307     if (opcstr[pos] == '.') {
308     pos++;
309     switch (opcstr[pos]) {
310    
311     case 'B': sz = sz_byte; break;
312     case 'W': sz = sz_word; break;
313     case 'L': sz = sz_long; break;
314     case 'z':
315     switch (bitval[bitz]) {
316     case 0: sz = sz_byte; break;
317     case 1: sz = sz_word; break;
318     case 2: sz = sz_long; break;
319     default: abort();
320     }
321     break;
322     default: abort();
323     }
324     } else {
325     mnemonic[mnp] = opcstr[pos];
326     if (mnemonic[mnp] == 'f') {
327     find = -1;
328     switch (bitval[bitf]) {
329     case 0: mnemonic[mnp] = 'R'; break;
330     case 1: mnemonic[mnp] = 'L'; break;
331     default: abort();
332     }
333     }
334     mnp++;
335 gbeauche 1.8 if ((unsigned)mnp >= sizeof(mnemonic) - 1) {
336     mnemonic[sizeof(mnemonic) - 1] = 0;
337     fprintf(stderr, "Instruction %s overflow\n", mnemonic);
338     abort();
339     }
340 cebix 1.1 }
341     pos++;
342     }
343     mnemonic[mnp] = 0;
344    
345     /* now, we have read the mnemonic and the size */
346     while (opcstr[pos] && isspace(opcstr[pos]))
347     pos++;
348    
349     /* A goto a day keeps the D******a away. */
350     if (opcstr[pos] == 0)
351     goto endofline;
352    
353     /* parse the source address */
354     usesrc = 1;
355     switch (opcstr[pos++]) {
356     case 'D':
357     srcmode = Dreg;
358     switch (opcstr[pos++]) {
359     case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break;
360     case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break;
361     default: abort();
362     }
363    
364     break;
365     case 'A':
366     srcmode = Areg;
367     switch (opcstr[pos++]) {
368     case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break;
369     case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break;
370     default: abort();
371     }
372     switch (opcstr[pos]) {
373     case 'p': srcmode = Apdi; pos++; break;
374     case 'P': srcmode = Aipi; pos++; break;
375     }
376     break;
377 gbeauche 1.4 case 'L':
378     srcmode = absl;
379     break;
380 cebix 1.1 case '#':
381     switch (opcstr[pos++]) {
382     case 'z': srcmode = imm; break;
383     case '0': srcmode = imm0; break;
384     case '1': srcmode = imm1; break;
385     case '2': srcmode = imm2; break;
386     case 'i': srcmode = immi; srcreg = (uae_s32)(uae_s8)bitval[biti];
387     if (CPU_EMU_SIZE < 4) {
388     /* Used for branch instructions */
389     srctype = 1;
390     srcgather = 1;
391     srcpos = bitpos[biti];
392     }
393     break;
394     case 'j': srcmode = immi; srcreg = bitval[bitj];
395     if (CPU_EMU_SIZE < 3) {
396     /* 1..8 for ADDQ/SUBQ and rotshi insns */
397     srcgather = 1;
398     srctype = 3;
399     srcpos = bitpos[bitj];
400     }
401     break;
402     case 'J': srcmode = immi; srcreg = bitval[bitJ];
403     if (CPU_EMU_SIZE < 5) {
404     /* 0..15 */
405     srcgather = 1;
406     srctype = 2;
407     srcpos = bitpos[bitJ];
408     }
409     break;
410     case 'k': srcmode = immi; srcreg = bitval[bitk];
411     if (CPU_EMU_SIZE < 3) {
412     srcgather = 1;
413     srctype = 4;
414     srcpos = bitpos[bitk];
415     }
416     break;
417     case 'K': srcmode = immi; srcreg = bitval[bitK];
418     if (CPU_EMU_SIZE < 5) {
419     /* 0..15 */
420     srcgather = 1;
421     srctype = 5;
422     srcpos = bitpos[bitK];
423     }
424     break;
425 gbeauche 1.5 case 'E': srcmode = immi; srcreg = bitval[bitE];
426     if (CPU_EMU_SIZE < 5) { // gb-- what is CPU_EMU_SIZE used for ??
427     /* 1..255 */
428     srcgather = 1;
429     srctype = 6;
430     srcpos = bitpos[bitE];
431     }
432     break;
433 gbeauche 1.3 case 'p': srcmode = immi; srcreg = bitval[bitp];
434 gbeauche 1.4 if (CPU_EMU_SIZE < 5) {
435 gbeauche 1.3 /* 0..3 */
436     srcgather = 1;
437     srctype = 7;
438     srcpos = bitpos[bitp];
439     }
440     break;
441 cebix 1.1 default: abort();
442     }
443     break;
444     case 'd':
445     srcreg = bitval[bitD];
446     srcmode = mode_from_mr(bitval[bitd],bitval[bitD]);
447     if (srcmode == am_illg)
448     continue;
449     if (CPU_EMU_SIZE < 2 &&
450     (srcmode == Areg || srcmode == Dreg || srcmode == Aind
451     || srcmode == Ad16 || srcmode == Ad8r || srcmode == Aipi
452     || srcmode == Apdi))
453     {
454     srcgather = 1; srcpos = bitpos[bitD];
455     }
456     if (opcstr[pos] == '[') {
457     pos++;
458     if (opcstr[pos] == '!') {
459     /* exclusion */
460     do {
461     pos++;
462     if (mode_from_str(opcstr+pos) == srcmode)
463     goto nomatch;
464     pos += 4;
465     } while (opcstr[pos] == ',');
466     pos++;
467     } else {
468     if (opcstr[pos+4] == '-') {
469     /* replacement */
470     if (mode_from_str(opcstr+pos) == srcmode)
471     srcmode = mode_from_str(opcstr+pos+5);
472     else
473     goto nomatch;
474     pos += 10;
475     } else {
476     /* normal */
477     while(mode_from_str(opcstr+pos) != srcmode) {
478     pos += 4;
479     if (opcstr[pos] == ']')
480     goto nomatch;
481     pos++;
482     }
483     while(opcstr[pos] != ']') pos++;
484     pos++;
485     break;
486     }
487     }
488     }
489     /* Some addressing modes are invalid as destination */
490     if (srcmode == imm || srcmode == PC16 || srcmode == PC8r)
491     goto nomatch;
492     break;
493     case 's':
494     srcreg = bitval[bitS];
495     srcmode = mode_from_mr(bitval[bits],bitval[bitS]);
496    
497     if (srcmode == am_illg)
498     continue;
499     if (CPU_EMU_SIZE < 2 &&
500     (srcmode == Areg || srcmode == Dreg || srcmode == Aind
501     || srcmode == Ad16 || srcmode == Ad8r || srcmode == Aipi
502     || srcmode == Apdi))
503     {
504     srcgather = 1; srcpos = bitpos[bitS];
505     }
506     if (opcstr[pos] == '[') {
507     pos++;
508     if (opcstr[pos] == '!') {
509     /* exclusion */
510     do {
511     pos++;
512     if (mode_from_str(opcstr+pos) == srcmode)
513     goto nomatch;
514     pos += 4;
515     } while (opcstr[pos] == ',');
516     pos++;
517     } else {
518     if (opcstr[pos+4] == '-') {
519     /* replacement */
520     if (mode_from_str(opcstr+pos) == srcmode)
521     srcmode = mode_from_str(opcstr+pos+5);
522     else
523     goto nomatch;
524     pos += 10;
525     } else {
526     /* normal */
527     while(mode_from_str(opcstr+pos) != srcmode) {
528     pos += 4;
529     if (opcstr[pos] == ']')
530     goto nomatch;
531     pos++;
532     }
533     while(opcstr[pos] != ']') pos++;
534     pos++;
535     }
536     }
537     }
538     break;
539     default: abort();
540     }
541     /* safety check - might have changed */
542     if (srcmode != Areg && srcmode != Dreg && srcmode != Aind
543     && srcmode != Ad16 && srcmode != Ad8r && srcmode != Aipi
544     && srcmode != Apdi && srcmode != immi)
545     {
546     srcgather = 0;
547     }
548     if (srcmode == Areg && sz == sz_byte)
549     goto nomatch;
550    
551     if (opcstr[pos] != ',')
552     goto endofline;
553     pos++;
554    
555     /* parse the destination address */
556     usedst = 1;
557     switch (opcstr[pos++]) {
558     case 'D':
559     destmode = Dreg;
560     switch (opcstr[pos++]) {
561     case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break;
562     case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break;
563     default: abort();
564     }
565 gbeauche 1.4 if (dstpos < 0 || dstpos >= 32)
566     abort();
567 cebix 1.1 break;
568     case 'A':
569     destmode = Areg;
570     switch (opcstr[pos++]) {
571     case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break;
572     case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break;
573 gbeauche 1.4 case 'x': destreg = 0; dstgather = 0; dstpos = 0; break;
574 cebix 1.1 default: abort();
575     }
576 gbeauche 1.4 if (dstpos < 0 || dstpos >= 32)
577     abort();
578 cebix 1.1 switch (opcstr[pos]) {
579     case 'p': destmode = Apdi; pos++; break;
580     case 'P': destmode = Aipi; pos++; break;
581     }
582     break;
583 gbeauche 1.4 case 'L':
584     destmode = absl;
585     break;
586 cebix 1.1 case '#':
587     switch (opcstr[pos++]) {
588     case 'z': destmode = imm; break;
589     case '0': destmode = imm0; break;
590     case '1': destmode = imm1; break;
591     case '2': destmode = imm2; break;
592     case 'i': destmode = immi; destreg = (uae_s32)(uae_s8)bitval[biti]; break;
593     case 'j': destmode = immi; destreg = bitval[bitj]; break;
594     case 'J': destmode = immi; destreg = bitval[bitJ]; break;
595     case 'k': destmode = immi; destreg = bitval[bitk]; break;
596     case 'K': destmode = immi; destreg = bitval[bitK]; break;
597     default: abort();
598     }
599     break;
600     case 'd':
601     destreg = bitval[bitD];
602     destmode = mode_from_mr(bitval[bitd],bitval[bitD]);
603     if (destmode == am_illg)
604     continue;
605     if (CPU_EMU_SIZE < 1 &&
606     (destmode == Areg || destmode == Dreg || destmode == Aind
607     || destmode == Ad16 || destmode == Ad8r || destmode == Aipi
608     || destmode == Apdi))
609     {
610     dstgather = 1; dstpos = bitpos[bitD];
611     }
612    
613     if (opcstr[pos] == '[') {
614     pos++;
615     if (opcstr[pos] == '!') {
616     /* exclusion */
617     do {
618     pos++;
619     if (mode_from_str(opcstr+pos) == destmode)
620     goto nomatch;
621     pos += 4;
622     } while (opcstr[pos] == ',');
623     pos++;
624     } else {
625     if (opcstr[pos+4] == '-') {
626     /* replacement */
627     if (mode_from_str(opcstr+pos) == destmode)
628     destmode = mode_from_str(opcstr+pos+5);
629     else
630     goto nomatch;
631     pos += 10;
632     } else {
633     /* normal */
634     while(mode_from_str(opcstr+pos) != destmode) {
635     pos += 4;
636     if (opcstr[pos] == ']')
637     goto nomatch;
638     pos++;
639     }
640     while(opcstr[pos] != ']') pos++;
641     pos++;
642     break;
643     }
644     }
645     }
646     /* Some addressing modes are invalid as destination */
647     if (destmode == imm || destmode == PC16 || destmode == PC8r)
648     goto nomatch;
649     break;
650     case 's':
651     destreg = bitval[bitS];
652     destmode = mode_from_mr(bitval[bits],bitval[bitS]);
653    
654     if (destmode == am_illg)
655     continue;
656     if (CPU_EMU_SIZE < 1 &&
657     (destmode == Areg || destmode == Dreg || destmode == Aind
658     || destmode == Ad16 || destmode == Ad8r || destmode == Aipi
659     || destmode == Apdi))
660     {
661     dstgather = 1; dstpos = bitpos[bitS];
662     }
663    
664     if (opcstr[pos] == '[') {
665     pos++;
666     if (opcstr[pos] == '!') {
667     /* exclusion */
668     do {
669     pos++;
670     if (mode_from_str(opcstr+pos) == destmode)
671     goto nomatch;
672     pos += 4;
673     } while (opcstr[pos] == ',');
674     pos++;
675     } else {
676     if (opcstr[pos+4] == '-') {
677     /* replacement */
678     if (mode_from_str(opcstr+pos) == destmode)
679     destmode = mode_from_str(opcstr+pos+5);
680     else
681     goto nomatch;
682     pos += 10;
683     } else {
684     /* normal */
685     while(mode_from_str(opcstr+pos) != destmode) {
686     pos += 4;
687     if (opcstr[pos] == ']')
688     goto nomatch;
689     pos++;
690     }
691     while(opcstr[pos] != ']') pos++;
692     pos++;
693     }
694     }
695     }
696     break;
697     default: abort();
698     }
699     /* safety check - might have changed */
700     if (destmode != Areg && destmode != Dreg && destmode != Aind
701     && destmode != Ad16 && destmode != Ad8r && destmode != Aipi
702     && destmode != Apdi)
703     {
704     dstgather = 0;
705     }
706    
707     if (destmode == Areg && sz == sz_byte)
708     goto nomatch;
709     #if 0
710     if (sz == sz_byte && (destmode == Aipi || destmode == Apdi)) {
711     dstgather = 0;
712     }
713     #endif
714     endofline:
715     /* now, we have a match */
716     if (table68k[opc].mnemo != i_ILLG)
717     fprintf(stderr, "Double match: %x: %s\n", opc, opcstr);
718     if (find == -1) {
719     for (find = 0;; find++) {
720     if (strcmp(mnemonic, lookuptab[find].name) == 0) {
721     table68k[opc].mnemo = lookuptab[find].mnemo;
722     break;
723     }
724     if (strlen(lookuptab[find].name) == 0) abort();
725     }
726     }
727     else {
728     table68k[opc].mnemo = lookuptab[find].mnemo;
729     }
730     table68k[opc].cc = bitval[bitc];
731     if (table68k[opc].mnemo == i_BTST
732     || table68k[opc].mnemo == i_BSET
733     || table68k[opc].mnemo == i_BCLR
734     || table68k[opc].mnemo == i_BCHG)
735     {
736     sz = destmode == Dreg ? sz_long : sz_byte;
737     }
738     table68k[opc].size = sz;
739     table68k[opc].sreg = srcreg;
740     table68k[opc].dreg = destreg;
741     table68k[opc].smode = srcmode;
742     table68k[opc].dmode = destmode;
743     table68k[opc].spos = srcgather ? srcpos : -1;
744     table68k[opc].dpos = dstgather ? dstpos : -1;
745     table68k[opc].suse = usesrc;
746     table68k[opc].duse = usedst;
747     table68k[opc].stype = srctype;
748     table68k[opc].plev = id.plevel;
749     table68k[opc].clev = id.cpulevel;
750     #if 0
751     for (i = 0; i < 5; i++) {
752     table68k[opc].flaginfo[i].flagset = id.flaginfo[i].flagset;
753     table68k[opc].flaginfo[i].flaguse = id.flaginfo[i].flaguse;
754     }
755     #endif
756 gbeauche 1.5
757 gbeauche 1.9 // Fix flags used information for Scc, Bcc, TRAPcc, DBcc instructions
758     if ( table68k[opc].mnemo == i_Scc
759     || table68k[opc].mnemo == i_Bcc
760     || table68k[opc].mnemo == i_DBcc
761     || table68k[opc].mnemo == i_TRAPcc
762     ) {
763     switch (table68k[opc].cc) {
764     // CC mask: XNZVC
765     // 8421
766     case 0: flags_used = 0x00; break; /* T */
767     case 1: flags_used = 0x00; break; /* F */
768     case 2: flags_used = 0x05; break; /* HI */
769     case 3: flags_used = 0x05; break; /* LS */
770     case 4: flags_used = 0x01; break; /* CC */
771     case 5: flags_used = 0x01; break; /* CS */
772     case 6: flags_used = 0x04; break; /* NE */
773     case 7: flags_used = 0x04; break; /* EQ */
774     case 8: flags_used = 0x02; break; /* VC */
775     case 9: flags_used = 0x02; break; /* VS */
776     case 10:flags_used = 0x08; break; /* PL */
777     case 11:flags_used = 0x08; break; /* MI */
778     case 12:flags_used = 0x0A; break; /* GE */
779     case 13:flags_used = 0x0A; break; /* LT */
780     case 14:flags_used = 0x0E; break; /* GT */
781     case 15:flags_used = 0x0E; break; /* LE */
782     }
783     }
784    
785 gbeauche 1.5 #if 1
786     /* gb-- flagdead and flaglive would not have correct information */
787     table68k[opc].flagdead = flags_set;
788     table68k[opc].flaglive = flags_used;
789     #else
790 cebix 1.1 table68k[opc].flagdead = flagdead;
791     table68k[opc].flaglive = flaglive;
792 gbeauche 1.5 #endif
793     table68k[opc].cflow = cflow;
794 cebix 1.1 nomatch:
795     /* FOO! */;
796     }
797     }
798    
799    
800     void read_table68k (void)
801     {
802     int i;
803    
804     table68k = (struct instr *)malloc (65536 * sizeof (struct instr));
805     for (i = 0; i < 65536; i++) {
806     table68k[i].mnemo = i_ILLG;
807     table68k[i].handler = -1;
808     }
809     for (i = 0; i < n_defs68k; i++) {
810     build_insn (i);
811     }
812     }
813    
814     static int mismatch;
815    
816     static void handle_merges (long int opcode)
817     {
818     uae_u16 smsk;
819     uae_u16 dmsk;
820     int sbitdst, dstend;
821     int srcreg, dstreg;
822    
823     if (table68k[opcode].spos == -1) {
824     sbitdst = 1; smsk = 0;
825     } else {
826     switch (table68k[opcode].stype) {
827     case 0:
828     smsk = 7; sbitdst = 8; break;
829     case 1:
830     smsk = 255; sbitdst = 256; break;
831     case 2:
832     smsk = 15; sbitdst = 16; break;
833     case 3:
834     smsk = 7; sbitdst = 8; break;
835     case 4:
836     smsk = 7; sbitdst = 8; break;
837     case 5:
838     smsk = 63; sbitdst = 64; break;
839 gbeauche 1.5 case 6:
840     smsk = 255; sbitdst = 256; break;
841 gbeauche 1.3 case 7:
842     smsk = 3; sbitdst = 4; break;
843 cebix 1.1 default:
844     smsk = 0; sbitdst = 0;
845     abort();
846     break;
847     }
848     smsk <<= table68k[opcode].spos;
849     }
850     if (table68k[opcode].dpos == -1) {
851     dstend = 1; dmsk = 0;
852     } else {
853     dmsk = 7 << table68k[opcode].dpos;
854     dstend = 8;
855     }
856     for (srcreg=0; srcreg < sbitdst; srcreg++) {
857     for (dstreg=0; dstreg < dstend; dstreg++) {
858     uae_u16 code = opcode;
859    
860     code = (code & ~smsk) | (srcreg << table68k[opcode].spos);
861     code = (code & ~dmsk) | (dstreg << table68k[opcode].dpos);
862    
863     /* Check whether this is in fact the same instruction.
864     * The instructions should never differ, except for the
865     * Bcc.(BW) case. */
866     if (table68k[code].mnemo != table68k[opcode].mnemo
867     || table68k[code].size != table68k[opcode].size
868     || table68k[code].suse != table68k[opcode].suse
869     || table68k[code].duse != table68k[opcode].duse)
870     {
871     mismatch++; continue;
872     }
873     if (table68k[opcode].suse
874     && (table68k[opcode].spos != table68k[code].spos
875     || table68k[opcode].smode != table68k[code].smode
876     || table68k[opcode].stype != table68k[code].stype))
877     {
878     mismatch++; continue;
879     }
880     if (table68k[opcode].duse
881     && (table68k[opcode].dpos != table68k[code].dpos
882     || table68k[opcode].dmode != table68k[code].dmode))
883     {
884     mismatch++; continue;
885     }
886    
887     if (code != opcode)
888     table68k[code].handler = opcode;
889     }
890     }
891     }
892    
893     void do_merges (void)
894     {
895     long int opcode;
896     int nr = 0;
897     mismatch = 0;
898     for (opcode = 0; opcode < 65536; opcode++) {
899     if (table68k[opcode].handler != -1 || table68k[opcode].mnemo == i_ILLG)
900     continue;
901     nr++;
902     handle_merges (opcode);
903     }
904     nr_cpuop_funcs = nr;
905     }
906    
907     int get_no_mismatches (void)
908     {
909     return mismatch;
910     }