1 |
cebix |
1.1 |
/* |
2 |
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* UAE - The Un*x Amiga Emulator |
3 |
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* |
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* Read 68000 CPU specs from file "table68k" |
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* |
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* Copyright 1995,1996 Bernd Schmidt |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <ctype.h> |
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14 |
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#include "sysdeps.h" |
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#include "readcpu.h" |
16 |
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17 |
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int nr_cpuop_funcs; |
18 |
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19 |
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struct mnemolookup lookuptab[] = { |
20 |
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{ i_ILLG, "ILLEGAL" }, |
21 |
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{ i_OR, "OR" }, |
22 |
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{ i_CHK, "CHK" }, |
23 |
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{ i_CHK2, "CHK2" }, |
24 |
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{ i_AND, "AND" }, |
25 |
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{ i_EOR, "EOR" }, |
26 |
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{ i_ORSR, "ORSR" }, |
27 |
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{ i_ANDSR, "ANDSR" }, |
28 |
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{ i_EORSR, "EORSR" }, |
29 |
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{ i_SUB, "SUB" }, |
30 |
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{ i_SUBA, "SUBA" }, |
31 |
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{ i_SUBX, "SUBX" }, |
32 |
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{ i_SBCD, "SBCD" }, |
33 |
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{ i_ADD, "ADD" }, |
34 |
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{ i_ADDA, "ADDA" }, |
35 |
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{ i_ADDX, "ADDX" }, |
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{ i_ABCD, "ABCD" }, |
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{ i_NEG, "NEG" }, |
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{ i_NEGX, "NEGX" }, |
39 |
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{ i_NBCD, "NBCD" }, |
40 |
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{ i_CLR, "CLR" }, |
41 |
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{ i_NOT, "NOT" }, |
42 |
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{ i_TST, "TST" }, |
43 |
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{ i_BTST, "BTST" }, |
44 |
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{ i_BCHG, "BCHG" }, |
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{ i_BCLR, "BCLR" }, |
46 |
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{ i_BSET, "BSET" }, |
47 |
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{ i_CMP, "CMP" }, |
48 |
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{ i_CMPM, "CMPM" }, |
49 |
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{ i_CMPA, "CMPA" }, |
50 |
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{ i_MVPRM, "MVPRM" }, |
51 |
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{ i_MVPMR, "MVPMR" }, |
52 |
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{ i_MOVE, "MOVE" }, |
53 |
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{ i_MOVEA, "MOVEA" }, |
54 |
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{ i_MVSR2, "MVSR2" }, |
55 |
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{ i_MV2SR, "MV2SR" }, |
56 |
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{ i_SWAP, "SWAP" }, |
57 |
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{ i_EXG, "EXG" }, |
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{ i_EXT, "EXT" }, |
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{ i_MVMEL, "MVMEL" }, |
60 |
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{ i_MVMLE, "MVMLE" }, |
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{ i_TRAP, "TRAP" }, |
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{ i_MVR2USP, "MVR2USP" }, |
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{ i_MVUSP2R, "MVUSP2R" }, |
64 |
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{ i_NOP, "NOP" }, |
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{ i_RESET, "RESET" }, |
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{ i_RTE, "RTE" }, |
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{ i_RTD, "RTD" }, |
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{ i_LINK, "LINK" }, |
69 |
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{ i_UNLK, "UNLK" }, |
70 |
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{ i_RTS, "RTS" }, |
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{ i_STOP, "STOP" }, |
72 |
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{ i_TRAPV, "TRAPV" }, |
73 |
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{ i_RTR, "RTR" }, |
74 |
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{ i_JSR, "JSR" }, |
75 |
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{ i_JMP, "JMP" }, |
76 |
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{ i_BSR, "BSR" }, |
77 |
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{ i_Bcc, "Bcc" }, |
78 |
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{ i_LEA, "LEA" }, |
79 |
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{ i_PEA, "PEA" }, |
80 |
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{ i_DBcc, "DBcc" }, |
81 |
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{ i_Scc, "Scc" }, |
82 |
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{ i_DIVU, "DIVU" }, |
83 |
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{ i_DIVS, "DIVS" }, |
84 |
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{ i_MULU, "MULU" }, |
85 |
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{ i_MULS, "MULS" }, |
86 |
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{ i_ASR, "ASR" }, |
87 |
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{ i_ASL, "ASL" }, |
88 |
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{ i_LSR, "LSR" }, |
89 |
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{ i_LSL, "LSL" }, |
90 |
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{ i_ROL, "ROL" }, |
91 |
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{ i_ROR, "ROR" }, |
92 |
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{ i_ROXL, "ROXL" }, |
93 |
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{ i_ROXR, "ROXR" }, |
94 |
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{ i_ASRW, "ASRW" }, |
95 |
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{ i_ASLW, "ASLW" }, |
96 |
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{ i_LSRW, "LSRW" }, |
97 |
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{ i_LSLW, "LSLW" }, |
98 |
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{ i_ROLW, "ROLW" }, |
99 |
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{ i_RORW, "RORW" }, |
100 |
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{ i_ROXLW, "ROXLW" }, |
101 |
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{ i_ROXRW, "ROXRW" }, |
102 |
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103 |
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{ i_MOVE2C, "MOVE2C" }, |
104 |
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{ i_MOVEC2, "MOVEC2" }, |
105 |
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{ i_CAS, "CAS" }, |
106 |
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{ i_CAS2, "CAS2" }, |
107 |
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{ i_MULL, "MULL" }, |
108 |
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{ i_DIVL, "DIVL" }, |
109 |
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{ i_BFTST, "BFTST" }, |
110 |
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{ i_BFEXTU, "BFEXTU" }, |
111 |
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{ i_BFCHG, "BFCHG" }, |
112 |
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{ i_BFEXTS, "BFEXTS" }, |
113 |
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{ i_BFCLR, "BFCLR" }, |
114 |
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{ i_BFFFO, "BFFFO" }, |
115 |
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{ i_BFSET, "BFSET" }, |
116 |
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{ i_BFINS, "BFINS" }, |
117 |
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{ i_PACK, "PACK" }, |
118 |
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{ i_UNPK, "UNPK" }, |
119 |
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{ i_TAS, "TAS" }, |
120 |
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{ i_BKPT, "BKPT" }, |
121 |
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{ i_CALLM, "CALLM" }, |
122 |
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{ i_RTM, "RTM" }, |
123 |
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{ i_TRAPcc, "TRAPcc" }, |
124 |
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{ i_MOVES, "MOVES" }, |
125 |
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{ i_FPP, "FPP" }, |
126 |
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{ i_FDBcc, "FDBcc" }, |
127 |
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{ i_FScc, "FScc" }, |
128 |
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{ i_FTRAPcc, "FTRAPcc" }, |
129 |
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{ i_FBcc, "FBcc" }, |
130 |
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{ i_FBcc, "FBcc" }, |
131 |
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{ i_FSAVE, "FSAVE" }, |
132 |
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{ i_FRESTORE, "FRESTORE" }, |
133 |
cebix |
1.2 |
|
134 |
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{ i_CINVL, "CINVL" }, |
135 |
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{ i_CINVP, "CINVP" }, |
136 |
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{ i_CINVA, "CINVA" }, |
137 |
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{ i_CPUSHL, "CPUSHL" }, |
138 |
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{ i_CPUSHP, "CPUSHP" }, |
139 |
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{ i_CPUSHA, "CPUSHA" }, |
140 |
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{ i_MOVE16, "MOVE16" }, |
141 |
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142 |
gbeauche |
1.5 |
{ i_EMULOP_RETURN, "EMULOP_RETURN" }, |
143 |
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{ i_EMULOP, "EMULOP" }, |
144 |
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145 |
cebix |
1.1 |
{ i_MMUOP, "MMUOP" }, |
146 |
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{ i_ILLG, "" }, |
147 |
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}; |
148 |
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149 |
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struct instr *table68k; |
150 |
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151 |
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static __inline__ amodes mode_from_str (const char *str) |
152 |
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{ |
153 |
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if (strncmp (str, "Dreg", 4) == 0) return Dreg; |
154 |
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if (strncmp (str, "Areg", 4) == 0) return Areg; |
155 |
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if (strncmp (str, "Aind", 4) == 0) return Aind; |
156 |
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if (strncmp (str, "Apdi", 4) == 0) return Apdi; |
157 |
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if (strncmp (str, "Aipi", 4) == 0) return Aipi; |
158 |
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if (strncmp (str, "Ad16", 4) == 0) return Ad16; |
159 |
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if (strncmp (str, "Ad8r", 4) == 0) return Ad8r; |
160 |
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if (strncmp (str, "absw", 4) == 0) return absw; |
161 |
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if (strncmp (str, "absl", 4) == 0) return absl; |
162 |
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if (strncmp (str, "PC16", 4) == 0) return PC16; |
163 |
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if (strncmp (str, "PC8r", 4) == 0) return PC8r; |
164 |
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if (strncmp (str, "Immd", 4) == 0) return imm; |
165 |
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abort (); |
166 |
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return (amodes)0; |
167 |
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} |
168 |
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169 |
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static __inline__ amodes mode_from_mr (int mode, int reg) |
170 |
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{ |
171 |
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switch (mode) { |
172 |
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case 0: return Dreg; |
173 |
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case 1: return Areg; |
174 |
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case 2: return Aind; |
175 |
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case 3: return Aipi; |
176 |
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case 4: return Apdi; |
177 |
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case 5: return Ad16; |
178 |
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case 6: return Ad8r; |
179 |
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case 7: |
180 |
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switch (reg) { |
181 |
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case 0: return absw; |
182 |
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case 1: return absl; |
183 |
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case 2: return PC16; |
184 |
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case 3: return PC8r; |
185 |
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case 4: return imm; |
186 |
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case 5: |
187 |
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case 6: |
188 |
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case 7: return am_illg; |
189 |
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} |
190 |
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} |
191 |
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abort (); |
192 |
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return (amodes)0; |
193 |
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} |
194 |
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195 |
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static void build_insn (int insn) |
196 |
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{ |
197 |
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int find = -1; |
198 |
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int variants; |
199 |
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struct instr_def id; |
200 |
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const char *opcstr; |
201 |
gbeauche |
1.5 |
int i, n; |
202 |
cebix |
1.1 |
|
203 |
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int flaglive = 0, flagdead = 0; |
204 |
gbeauche |
1.5 |
int cflow = 0; |
205 |
cebix |
1.1 |
|
206 |
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id = defs68k[insn]; |
207 |
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208 |
gbeauche |
1.5 |
// Control flow information |
209 |
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cflow = id.cflow; |
210 |
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211 |
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// Mask of flags set/used |
212 |
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unsigned char flags_set(0), flags_used(0); |
213 |
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214 |
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for (i = 0, n = 4; i < 5; i++, n--) { |
215 |
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switch (id.flaginfo[i].flagset) { |
216 |
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case fa_unset: case fa_isjmp: break; |
217 |
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default: flags_set |= (1 << n); |
218 |
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} |
219 |
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220 |
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switch (id.flaginfo[i].flaguse) { |
221 |
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case fu_unused: case fu_isjmp: break; |
222 |
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default: flags_used |= (1 << n); |
223 |
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} |
224 |
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} |
225 |
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226 |
cebix |
1.1 |
for (i = 0; i < 5; i++) { |
227 |
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switch (id.flaginfo[i].flagset){ |
228 |
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case fa_unset: break; |
229 |
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case fa_zero: flagdead |= 1 << i; break; |
230 |
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case fa_one: flagdead |= 1 << i; break; |
231 |
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case fa_dontcare: flagdead |= 1 << i; break; |
232 |
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case fa_unknown: flagdead = -1; goto out1; |
233 |
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case fa_set: flagdead |= 1 << i; break; |
234 |
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} |
235 |
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} |
236 |
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237 |
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out1: |
238 |
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for (i = 0; i < 5; i++) { |
239 |
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switch (id.flaginfo[i].flaguse) { |
240 |
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case fu_unused: break; |
241 |
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case fu_unknown: flaglive = -1; goto out2; |
242 |
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case fu_used: flaglive |= 1 << i; break; |
243 |
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} |
244 |
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} |
245 |
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out2: |
246 |
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247 |
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opcstr = id.opcstr; |
248 |
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for (variants = 0; variants < (1 << id.n_variable); variants++) { |
249 |
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int bitcnt[lastbit]; |
250 |
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int bitval[lastbit]; |
251 |
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int bitpos[lastbit]; |
252 |
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int i; |
253 |
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uae_u16 opc = id.bits; |
254 |
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uae_u16 msk, vmsk; |
255 |
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int pos = 0; |
256 |
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int mnp = 0; |
257 |
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int bitno = 0; |
258 |
gbeauche |
1.8 |
char mnemonic[64]; |
259 |
cebix |
1.1 |
|
260 |
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wordsizes sz = sz_long; |
261 |
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int srcgather = 0, dstgather = 0; |
262 |
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int usesrc = 0, usedst = 0; |
263 |
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int srctype = 0; |
264 |
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int srcpos = -1, dstpos = -1; |
265 |
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266 |
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amodes srcmode = am_unknown, destmode = am_unknown; |
267 |
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int srcreg = -1, destreg = -1; |
268 |
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269 |
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for (i = 0; i < lastbit; i++) |
270 |
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bitcnt[i] = bitval[i] = 0; |
271 |
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272 |
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vmsk = 1 << id.n_variable; |
273 |
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274 |
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for (i = 0, msk = 0x8000; i < 16; i++, msk >>= 1) { |
275 |
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if (!(msk & id.mask)) { |
276 |
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int currbit = id.bitpos[bitno++]; |
277 |
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int bit_set; |
278 |
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vmsk >>= 1; |
279 |
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bit_set = variants & vmsk ? 1 : 0; |
280 |
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if (bit_set) |
281 |
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opc |= msk; |
282 |
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bitpos[currbit] = 15 - i; |
283 |
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bitcnt[currbit]++; |
284 |
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bitval[currbit] <<= 1; |
285 |
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bitval[currbit] |= bit_set; |
286 |
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} |
287 |
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} |
288 |
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289 |
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if (bitval[bitj] == 0) bitval[bitj] = 8; |
290 |
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/* first check whether this one does not match after all */ |
291 |
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if (bitval[bitz] == 3 || bitval[bitC] == 1) |
292 |
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continue; |
293 |
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if (bitcnt[bitI] && (bitval[bitI] == 0x00 || bitval[bitI] == 0xff)) |
294 |
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continue; |
295 |
gbeauche |
1.5 |
if (bitcnt[bitE] && (bitval[bitE] == 0x00)) |
296 |
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continue; |
297 |
cebix |
1.1 |
|
298 |
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/* bitI and bitC get copied to biti and bitc */ |
299 |
|
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if (bitcnt[bitI]) { |
300 |
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bitval[biti] = bitval[bitI]; bitpos[biti] = bitpos[bitI]; |
301 |
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} |
302 |
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if (bitcnt[bitC]) |
303 |
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bitval[bitc] = bitval[bitC]; |
304 |
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305 |
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pos = 0; |
306 |
|
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while (opcstr[pos] && !isspace(opcstr[pos])) { |
307 |
|
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if (opcstr[pos] == '.') { |
308 |
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pos++; |
309 |
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switch (opcstr[pos]) { |
310 |
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311 |
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case 'B': sz = sz_byte; break; |
312 |
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case 'W': sz = sz_word; break; |
313 |
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case 'L': sz = sz_long; break; |
314 |
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case 'z': |
315 |
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switch (bitval[bitz]) { |
316 |
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case 0: sz = sz_byte; break; |
317 |
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case 1: sz = sz_word; break; |
318 |
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case 2: sz = sz_long; break; |
319 |
|
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default: abort(); |
320 |
|
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} |
321 |
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break; |
322 |
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default: abort(); |
323 |
|
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} |
324 |
|
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} else { |
325 |
|
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mnemonic[mnp] = opcstr[pos]; |
326 |
|
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if (mnemonic[mnp] == 'f') { |
327 |
|
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find = -1; |
328 |
|
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switch (bitval[bitf]) { |
329 |
|
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case 0: mnemonic[mnp] = 'R'; break; |
330 |
|
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case 1: mnemonic[mnp] = 'L'; break; |
331 |
|
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default: abort(); |
332 |
|
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} |
333 |
|
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} |
334 |
|
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mnp++; |
335 |
gbeauche |
1.8 |
if ((unsigned)mnp >= sizeof(mnemonic) - 1) { |
336 |
|
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mnemonic[sizeof(mnemonic) - 1] = 0; |
337 |
|
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fprintf(stderr, "Instruction %s overflow\n", mnemonic); |
338 |
|
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abort(); |
339 |
|
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} |
340 |
cebix |
1.1 |
} |
341 |
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pos++; |
342 |
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} |
343 |
|
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mnemonic[mnp] = 0; |
344 |
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345 |
|
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/* now, we have read the mnemonic and the size */ |
346 |
|
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while (opcstr[pos] && isspace(opcstr[pos])) |
347 |
|
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pos++; |
348 |
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349 |
|
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/* A goto a day keeps the D******a away. */ |
350 |
|
|
if (opcstr[pos] == 0) |
351 |
|
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goto endofline; |
352 |
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353 |
|
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/* parse the source address */ |
354 |
|
|
usesrc = 1; |
355 |
|
|
switch (opcstr[pos++]) { |
356 |
|
|
case 'D': |
357 |
|
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srcmode = Dreg; |
358 |
|
|
switch (opcstr[pos++]) { |
359 |
|
|
case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break; |
360 |
|
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case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break; |
361 |
|
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default: abort(); |
362 |
|
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} |
363 |
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|
364 |
|
|
break; |
365 |
|
|
case 'A': |
366 |
|
|
srcmode = Areg; |
367 |
|
|
switch (opcstr[pos++]) { |
368 |
|
|
case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break; |
369 |
|
|
case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break; |
370 |
|
|
default: abort(); |
371 |
|
|
} |
372 |
|
|
switch (opcstr[pos]) { |
373 |
|
|
case 'p': srcmode = Apdi; pos++; break; |
374 |
|
|
case 'P': srcmode = Aipi; pos++; break; |
375 |
|
|
} |
376 |
|
|
break; |
377 |
gbeauche |
1.4 |
case 'L': |
378 |
|
|
srcmode = absl; |
379 |
|
|
break; |
380 |
cebix |
1.1 |
case '#': |
381 |
|
|
switch (opcstr[pos++]) { |
382 |
|
|
case 'z': srcmode = imm; break; |
383 |
|
|
case '0': srcmode = imm0; break; |
384 |
|
|
case '1': srcmode = imm1; break; |
385 |
|
|
case '2': srcmode = imm2; break; |
386 |
|
|
case 'i': srcmode = immi; srcreg = (uae_s32)(uae_s8)bitval[biti]; |
387 |
|
|
if (CPU_EMU_SIZE < 4) { |
388 |
|
|
/* Used for branch instructions */ |
389 |
|
|
srctype = 1; |
390 |
|
|
srcgather = 1; |
391 |
|
|
srcpos = bitpos[biti]; |
392 |
|
|
} |
393 |
|
|
break; |
394 |
|
|
case 'j': srcmode = immi; srcreg = bitval[bitj]; |
395 |
|
|
if (CPU_EMU_SIZE < 3) { |
396 |
|
|
/* 1..8 for ADDQ/SUBQ and rotshi insns */ |
397 |
|
|
srcgather = 1; |
398 |
|
|
srctype = 3; |
399 |
|
|
srcpos = bitpos[bitj]; |
400 |
|
|
} |
401 |
|
|
break; |
402 |
|
|
case 'J': srcmode = immi; srcreg = bitval[bitJ]; |
403 |
|
|
if (CPU_EMU_SIZE < 5) { |
404 |
|
|
/* 0..15 */ |
405 |
|
|
srcgather = 1; |
406 |
|
|
srctype = 2; |
407 |
|
|
srcpos = bitpos[bitJ]; |
408 |
|
|
} |
409 |
|
|
break; |
410 |
|
|
case 'k': srcmode = immi; srcreg = bitval[bitk]; |
411 |
|
|
if (CPU_EMU_SIZE < 3) { |
412 |
|
|
srcgather = 1; |
413 |
|
|
srctype = 4; |
414 |
|
|
srcpos = bitpos[bitk]; |
415 |
|
|
} |
416 |
|
|
break; |
417 |
|
|
case 'K': srcmode = immi; srcreg = bitval[bitK]; |
418 |
|
|
if (CPU_EMU_SIZE < 5) { |
419 |
|
|
/* 0..15 */ |
420 |
|
|
srcgather = 1; |
421 |
|
|
srctype = 5; |
422 |
|
|
srcpos = bitpos[bitK]; |
423 |
|
|
} |
424 |
|
|
break; |
425 |
gbeauche |
1.5 |
case 'E': srcmode = immi; srcreg = bitval[bitE]; |
426 |
|
|
if (CPU_EMU_SIZE < 5) { // gb-- what is CPU_EMU_SIZE used for ?? |
427 |
|
|
/* 1..255 */ |
428 |
|
|
srcgather = 1; |
429 |
|
|
srctype = 6; |
430 |
|
|
srcpos = bitpos[bitE]; |
431 |
|
|
} |
432 |
|
|
break; |
433 |
gbeauche |
1.3 |
case 'p': srcmode = immi; srcreg = bitval[bitp]; |
434 |
gbeauche |
1.4 |
if (CPU_EMU_SIZE < 5) { |
435 |
gbeauche |
1.3 |
/* 0..3 */ |
436 |
|
|
srcgather = 1; |
437 |
|
|
srctype = 7; |
438 |
|
|
srcpos = bitpos[bitp]; |
439 |
|
|
} |
440 |
|
|
break; |
441 |
cebix |
1.1 |
default: abort(); |
442 |
|
|
} |
443 |
|
|
break; |
444 |
|
|
case 'd': |
445 |
|
|
srcreg = bitval[bitD]; |
446 |
|
|
srcmode = mode_from_mr(bitval[bitd],bitval[bitD]); |
447 |
|
|
if (srcmode == am_illg) |
448 |
|
|
continue; |
449 |
|
|
if (CPU_EMU_SIZE < 2 && |
450 |
|
|
(srcmode == Areg || srcmode == Dreg || srcmode == Aind |
451 |
|
|
|| srcmode == Ad16 || srcmode == Ad8r || srcmode == Aipi |
452 |
|
|
|| srcmode == Apdi)) |
453 |
|
|
{ |
454 |
|
|
srcgather = 1; srcpos = bitpos[bitD]; |
455 |
|
|
} |
456 |
|
|
if (opcstr[pos] == '[') { |
457 |
|
|
pos++; |
458 |
|
|
if (opcstr[pos] == '!') { |
459 |
|
|
/* exclusion */ |
460 |
|
|
do { |
461 |
|
|
pos++; |
462 |
|
|
if (mode_from_str(opcstr+pos) == srcmode) |
463 |
|
|
goto nomatch; |
464 |
|
|
pos += 4; |
465 |
|
|
} while (opcstr[pos] == ','); |
466 |
|
|
pos++; |
467 |
|
|
} else { |
468 |
|
|
if (opcstr[pos+4] == '-') { |
469 |
|
|
/* replacement */ |
470 |
|
|
if (mode_from_str(opcstr+pos) == srcmode) |
471 |
|
|
srcmode = mode_from_str(opcstr+pos+5); |
472 |
|
|
else |
473 |
|
|
goto nomatch; |
474 |
|
|
pos += 10; |
475 |
|
|
} else { |
476 |
|
|
/* normal */ |
477 |
|
|
while(mode_from_str(opcstr+pos) != srcmode) { |
478 |
|
|
pos += 4; |
479 |
|
|
if (opcstr[pos] == ']') |
480 |
|
|
goto nomatch; |
481 |
|
|
pos++; |
482 |
|
|
} |
483 |
|
|
while(opcstr[pos] != ']') pos++; |
484 |
|
|
pos++; |
485 |
|
|
break; |
486 |
|
|
} |
487 |
|
|
} |
488 |
|
|
} |
489 |
|
|
/* Some addressing modes are invalid as destination */ |
490 |
|
|
if (srcmode == imm || srcmode == PC16 || srcmode == PC8r) |
491 |
|
|
goto nomatch; |
492 |
|
|
break; |
493 |
|
|
case 's': |
494 |
|
|
srcreg = bitval[bitS]; |
495 |
|
|
srcmode = mode_from_mr(bitval[bits],bitval[bitS]); |
496 |
|
|
|
497 |
|
|
if (srcmode == am_illg) |
498 |
|
|
continue; |
499 |
|
|
if (CPU_EMU_SIZE < 2 && |
500 |
|
|
(srcmode == Areg || srcmode == Dreg || srcmode == Aind |
501 |
|
|
|| srcmode == Ad16 || srcmode == Ad8r || srcmode == Aipi |
502 |
|
|
|| srcmode == Apdi)) |
503 |
|
|
{ |
504 |
|
|
srcgather = 1; srcpos = bitpos[bitS]; |
505 |
|
|
} |
506 |
|
|
if (opcstr[pos] == '[') { |
507 |
|
|
pos++; |
508 |
|
|
if (opcstr[pos] == '!') { |
509 |
|
|
/* exclusion */ |
510 |
|
|
do { |
511 |
|
|
pos++; |
512 |
|
|
if (mode_from_str(opcstr+pos) == srcmode) |
513 |
|
|
goto nomatch; |
514 |
|
|
pos += 4; |
515 |
|
|
} while (opcstr[pos] == ','); |
516 |
|
|
pos++; |
517 |
|
|
} else { |
518 |
|
|
if (opcstr[pos+4] == '-') { |
519 |
|
|
/* replacement */ |
520 |
|
|
if (mode_from_str(opcstr+pos) == srcmode) |
521 |
|
|
srcmode = mode_from_str(opcstr+pos+5); |
522 |
|
|
else |
523 |
|
|
goto nomatch; |
524 |
|
|
pos += 10; |
525 |
|
|
} else { |
526 |
|
|
/* normal */ |
527 |
|
|
while(mode_from_str(opcstr+pos) != srcmode) { |
528 |
|
|
pos += 4; |
529 |
|
|
if (opcstr[pos] == ']') |
530 |
|
|
goto nomatch; |
531 |
|
|
pos++; |
532 |
|
|
} |
533 |
|
|
while(opcstr[pos] != ']') pos++; |
534 |
|
|
pos++; |
535 |
|
|
} |
536 |
|
|
} |
537 |
|
|
} |
538 |
|
|
break; |
539 |
|
|
default: abort(); |
540 |
|
|
} |
541 |
|
|
/* safety check - might have changed */ |
542 |
|
|
if (srcmode != Areg && srcmode != Dreg && srcmode != Aind |
543 |
|
|
&& srcmode != Ad16 && srcmode != Ad8r && srcmode != Aipi |
544 |
|
|
&& srcmode != Apdi && srcmode != immi) |
545 |
|
|
{ |
546 |
|
|
srcgather = 0; |
547 |
|
|
} |
548 |
|
|
if (srcmode == Areg && sz == sz_byte) |
549 |
|
|
goto nomatch; |
550 |
|
|
|
551 |
|
|
if (opcstr[pos] != ',') |
552 |
|
|
goto endofline; |
553 |
|
|
pos++; |
554 |
|
|
|
555 |
|
|
/* parse the destination address */ |
556 |
|
|
usedst = 1; |
557 |
|
|
switch (opcstr[pos++]) { |
558 |
|
|
case 'D': |
559 |
|
|
destmode = Dreg; |
560 |
|
|
switch (opcstr[pos++]) { |
561 |
|
|
case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break; |
562 |
|
|
case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break; |
563 |
|
|
default: abort(); |
564 |
|
|
} |
565 |
gbeauche |
1.4 |
if (dstpos < 0 || dstpos >= 32) |
566 |
|
|
abort(); |
567 |
cebix |
1.1 |
break; |
568 |
|
|
case 'A': |
569 |
|
|
destmode = Areg; |
570 |
|
|
switch (opcstr[pos++]) { |
571 |
|
|
case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break; |
572 |
|
|
case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break; |
573 |
gbeauche |
1.4 |
case 'x': destreg = 0; dstgather = 0; dstpos = 0; break; |
574 |
cebix |
1.1 |
default: abort(); |
575 |
|
|
} |
576 |
gbeauche |
1.4 |
if (dstpos < 0 || dstpos >= 32) |
577 |
|
|
abort(); |
578 |
cebix |
1.1 |
switch (opcstr[pos]) { |
579 |
|
|
case 'p': destmode = Apdi; pos++; break; |
580 |
|
|
case 'P': destmode = Aipi; pos++; break; |
581 |
|
|
} |
582 |
|
|
break; |
583 |
gbeauche |
1.4 |
case 'L': |
584 |
|
|
destmode = absl; |
585 |
|
|
break; |
586 |
cebix |
1.1 |
case '#': |
587 |
|
|
switch (opcstr[pos++]) { |
588 |
|
|
case 'z': destmode = imm; break; |
589 |
|
|
case '0': destmode = imm0; break; |
590 |
|
|
case '1': destmode = imm1; break; |
591 |
|
|
case '2': destmode = imm2; break; |
592 |
|
|
case 'i': destmode = immi; destreg = (uae_s32)(uae_s8)bitval[biti]; break; |
593 |
|
|
case 'j': destmode = immi; destreg = bitval[bitj]; break; |
594 |
|
|
case 'J': destmode = immi; destreg = bitval[bitJ]; break; |
595 |
|
|
case 'k': destmode = immi; destreg = bitval[bitk]; break; |
596 |
|
|
case 'K': destmode = immi; destreg = bitval[bitK]; break; |
597 |
|
|
default: abort(); |
598 |
|
|
} |
599 |
|
|
break; |
600 |
|
|
case 'd': |
601 |
|
|
destreg = bitval[bitD]; |
602 |
|
|
destmode = mode_from_mr(bitval[bitd],bitval[bitD]); |
603 |
|
|
if (destmode == am_illg) |
604 |
|
|
continue; |
605 |
|
|
if (CPU_EMU_SIZE < 1 && |
606 |
|
|
(destmode == Areg || destmode == Dreg || destmode == Aind |
607 |
|
|
|| destmode == Ad16 || destmode == Ad8r || destmode == Aipi |
608 |
|
|
|| destmode == Apdi)) |
609 |
|
|
{ |
610 |
|
|
dstgather = 1; dstpos = bitpos[bitD]; |
611 |
|
|
} |
612 |
|
|
|
613 |
|
|
if (opcstr[pos] == '[') { |
614 |
|
|
pos++; |
615 |
|
|
if (opcstr[pos] == '!') { |
616 |
|
|
/* exclusion */ |
617 |
|
|
do { |
618 |
|
|
pos++; |
619 |
|
|
if (mode_from_str(opcstr+pos) == destmode) |
620 |
|
|
goto nomatch; |
621 |
|
|
pos += 4; |
622 |
|
|
} while (opcstr[pos] == ','); |
623 |
|
|
pos++; |
624 |
|
|
} else { |
625 |
|
|
if (opcstr[pos+4] == '-') { |
626 |
|
|
/* replacement */ |
627 |
|
|
if (mode_from_str(opcstr+pos) == destmode) |
628 |
|
|
destmode = mode_from_str(opcstr+pos+5); |
629 |
|
|
else |
630 |
|
|
goto nomatch; |
631 |
|
|
pos += 10; |
632 |
|
|
} else { |
633 |
|
|
/* normal */ |
634 |
|
|
while(mode_from_str(opcstr+pos) != destmode) { |
635 |
|
|
pos += 4; |
636 |
|
|
if (opcstr[pos] == ']') |
637 |
|
|
goto nomatch; |
638 |
|
|
pos++; |
639 |
|
|
} |
640 |
|
|
while(opcstr[pos] != ']') pos++; |
641 |
|
|
pos++; |
642 |
|
|
break; |
643 |
|
|
} |
644 |
|
|
} |
645 |
|
|
} |
646 |
|
|
/* Some addressing modes are invalid as destination */ |
647 |
|
|
if (destmode == imm || destmode == PC16 || destmode == PC8r) |
648 |
|
|
goto nomatch; |
649 |
|
|
break; |
650 |
|
|
case 's': |
651 |
|
|
destreg = bitval[bitS]; |
652 |
|
|
destmode = mode_from_mr(bitval[bits],bitval[bitS]); |
653 |
|
|
|
654 |
|
|
if (destmode == am_illg) |
655 |
|
|
continue; |
656 |
|
|
if (CPU_EMU_SIZE < 1 && |
657 |
|
|
(destmode == Areg || destmode == Dreg || destmode == Aind |
658 |
|
|
|| destmode == Ad16 || destmode == Ad8r || destmode == Aipi |
659 |
|
|
|| destmode == Apdi)) |
660 |
|
|
{ |
661 |
|
|
dstgather = 1; dstpos = bitpos[bitS]; |
662 |
|
|
} |
663 |
|
|
|
664 |
|
|
if (opcstr[pos] == '[') { |
665 |
|
|
pos++; |
666 |
|
|
if (opcstr[pos] == '!') { |
667 |
|
|
/* exclusion */ |
668 |
|
|
do { |
669 |
|
|
pos++; |
670 |
|
|
if (mode_from_str(opcstr+pos) == destmode) |
671 |
|
|
goto nomatch; |
672 |
|
|
pos += 4; |
673 |
|
|
} while (opcstr[pos] == ','); |
674 |
|
|
pos++; |
675 |
|
|
} else { |
676 |
|
|
if (opcstr[pos+4] == '-') { |
677 |
|
|
/* replacement */ |
678 |
|
|
if (mode_from_str(opcstr+pos) == destmode) |
679 |
|
|
destmode = mode_from_str(opcstr+pos+5); |
680 |
|
|
else |
681 |
|
|
goto nomatch; |
682 |
|
|
pos += 10; |
683 |
|
|
} else { |
684 |
|
|
/* normal */ |
685 |
|
|
while(mode_from_str(opcstr+pos) != destmode) { |
686 |
|
|
pos += 4; |
687 |
|
|
if (opcstr[pos] == ']') |
688 |
|
|
goto nomatch; |
689 |
|
|
pos++; |
690 |
|
|
} |
691 |
|
|
while(opcstr[pos] != ']') pos++; |
692 |
|
|
pos++; |
693 |
|
|
} |
694 |
|
|
} |
695 |
|
|
} |
696 |
|
|
break; |
697 |
|
|
default: abort(); |
698 |
|
|
} |
699 |
|
|
/* safety check - might have changed */ |
700 |
|
|
if (destmode != Areg && destmode != Dreg && destmode != Aind |
701 |
|
|
&& destmode != Ad16 && destmode != Ad8r && destmode != Aipi |
702 |
|
|
&& destmode != Apdi) |
703 |
|
|
{ |
704 |
|
|
dstgather = 0; |
705 |
|
|
} |
706 |
|
|
|
707 |
|
|
if (destmode == Areg && sz == sz_byte) |
708 |
|
|
goto nomatch; |
709 |
|
|
#if 0 |
710 |
|
|
if (sz == sz_byte && (destmode == Aipi || destmode == Apdi)) { |
711 |
|
|
dstgather = 0; |
712 |
|
|
} |
713 |
|
|
#endif |
714 |
|
|
endofline: |
715 |
|
|
/* now, we have a match */ |
716 |
|
|
if (table68k[opc].mnemo != i_ILLG) |
717 |
|
|
fprintf(stderr, "Double match: %x: %s\n", opc, opcstr); |
718 |
|
|
if (find == -1) { |
719 |
|
|
for (find = 0;; find++) { |
720 |
|
|
if (strcmp(mnemonic, lookuptab[find].name) == 0) { |
721 |
|
|
table68k[opc].mnemo = lookuptab[find].mnemo; |
722 |
|
|
break; |
723 |
|
|
} |
724 |
|
|
if (strlen(lookuptab[find].name) == 0) abort(); |
725 |
|
|
} |
726 |
|
|
} |
727 |
|
|
else { |
728 |
|
|
table68k[opc].mnemo = lookuptab[find].mnemo; |
729 |
|
|
} |
730 |
|
|
table68k[opc].cc = bitval[bitc]; |
731 |
|
|
if (table68k[opc].mnemo == i_BTST |
732 |
|
|
|| table68k[opc].mnemo == i_BSET |
733 |
|
|
|| table68k[opc].mnemo == i_BCLR |
734 |
|
|
|| table68k[opc].mnemo == i_BCHG) |
735 |
|
|
{ |
736 |
|
|
sz = destmode == Dreg ? sz_long : sz_byte; |
737 |
|
|
} |
738 |
|
|
table68k[opc].size = sz; |
739 |
|
|
table68k[opc].sreg = srcreg; |
740 |
|
|
table68k[opc].dreg = destreg; |
741 |
|
|
table68k[opc].smode = srcmode; |
742 |
|
|
table68k[opc].dmode = destmode; |
743 |
|
|
table68k[opc].spos = srcgather ? srcpos : -1; |
744 |
|
|
table68k[opc].dpos = dstgather ? dstpos : -1; |
745 |
|
|
table68k[opc].suse = usesrc; |
746 |
|
|
table68k[opc].duse = usedst; |
747 |
|
|
table68k[opc].stype = srctype; |
748 |
|
|
table68k[opc].plev = id.plevel; |
749 |
|
|
table68k[opc].clev = id.cpulevel; |
750 |
|
|
#if 0 |
751 |
|
|
for (i = 0; i < 5; i++) { |
752 |
|
|
table68k[opc].flaginfo[i].flagset = id.flaginfo[i].flagset; |
753 |
|
|
table68k[opc].flaginfo[i].flaguse = id.flaginfo[i].flaguse; |
754 |
|
|
} |
755 |
|
|
#endif |
756 |
gbeauche |
1.5 |
|
757 |
|
|
#if 1 |
758 |
|
|
/* gb-- flagdead and flaglive would not have correct information */ |
759 |
|
|
table68k[opc].flagdead = flags_set; |
760 |
|
|
table68k[opc].flaglive = flags_used; |
761 |
|
|
#else |
762 |
cebix |
1.1 |
table68k[opc].flagdead = flagdead; |
763 |
|
|
table68k[opc].flaglive = flaglive; |
764 |
gbeauche |
1.5 |
#endif |
765 |
|
|
table68k[opc].cflow = cflow; |
766 |
cebix |
1.1 |
nomatch: |
767 |
|
|
/* FOO! */; |
768 |
|
|
} |
769 |
|
|
} |
770 |
|
|
|
771 |
|
|
|
772 |
|
|
void read_table68k (void) |
773 |
|
|
{ |
774 |
|
|
int i; |
775 |
|
|
|
776 |
|
|
table68k = (struct instr *)malloc (65536 * sizeof (struct instr)); |
777 |
|
|
for (i = 0; i < 65536; i++) { |
778 |
|
|
table68k[i].mnemo = i_ILLG; |
779 |
|
|
table68k[i].handler = -1; |
780 |
|
|
} |
781 |
|
|
for (i = 0; i < n_defs68k; i++) { |
782 |
|
|
build_insn (i); |
783 |
|
|
} |
784 |
gbeauche |
1.5 |
|
785 |
|
|
/* Extra fixes in table68k for control flow information and flag usage */ |
786 |
|
|
for (i = 0; i < 65536; i++) { |
787 |
|
|
instrmnem mnemo = (instrmnem)(table68k[i].mnemo); |
788 |
|
|
|
789 |
|
|
#define IS_CONST_JUMP(opc) \ |
790 |
|
|
( ((table68k[opc].mnemo == i_Bcc) && (table68k[opc].cc < 2)) \ |
791 |
|
|
|| (table68k[opc].mnemo == i_BSR) \ |
792 |
|
|
) |
793 |
|
|
|
794 |
gbeauche |
1.7 |
// Precise const jumps as such. The JIT compiler will take |
795 |
|
|
// care to actually enable that optimization or not |
796 |
|
|
if (IS_CONST_JUMP(i)) |
797 |
|
|
table68k[i].cflow |= fl_const_jump; |
798 |
|
|
|
799 |
gbeauche |
1.5 |
// Fix flags used information for Scc, Bcc, TRAPcc, DBcc instructions |
800 |
|
|
int flags_used = table68k[i].flaglive; |
801 |
|
|
if ( (mnemo == i_Scc) |
802 |
|
|
|| (mnemo == i_Bcc) |
803 |
|
|
|| (mnemo == i_DBcc) |
804 |
|
|
|| (mnemo == i_TRAPcc) |
805 |
|
|
) { |
806 |
|
|
switch (table68k[i].cc) { |
807 |
|
|
// CC mask: XNZVC |
808 |
|
|
// 8421 |
809 |
|
|
case 0: flags_used = 0x00; break; /* T */ |
810 |
|
|
case 1: flags_used = 0x00; break; /* F */ |
811 |
|
|
case 2: flags_used = 0x05; break; /* HI */ |
812 |
|
|
case 3: flags_used = 0x05; break; /* LS */ |
813 |
|
|
case 4: flags_used = 0x01; break; /* CC */ |
814 |
|
|
case 5: flags_used = 0x01; break; /* CS */ |
815 |
|
|
case 6: flags_used = 0x04; break; /* NE */ |
816 |
|
|
case 7: flags_used = 0x04; break; /* EQ */ |
817 |
|
|
case 8: flags_used = 0x02; break; /* VC */ |
818 |
|
|
case 9: flags_used = 0x02; break; /* VS */ |
819 |
|
|
case 10:flags_used = 0x08; break; /* PL */ |
820 |
|
|
case 11:flags_used = 0x08; break; /* MI */ |
821 |
|
|
case 12:flags_used = 0x0A; break; /* GE */ |
822 |
|
|
case 13:flags_used = 0x0A; break; /* LT */ |
823 |
|
|
case 14:flags_used = 0x0E; break; /* GT */ |
824 |
|
|
case 15:flags_used = 0x0E; break; /* LE */ |
825 |
|
|
} |
826 |
|
|
} |
827 |
|
|
|
828 |
|
|
/* Unconditional jumps don't evaluate condition codes, so they |
829 |
|
|
don't actually use any flags themselves */ |
830 |
|
|
if (IS_CONST_JUMP(i)) |
831 |
|
|
flags_used = 0; |
832 |
|
|
|
833 |
|
|
table68k[i].flaglive = flags_used; |
834 |
|
|
} |
835 |
cebix |
1.1 |
} |
836 |
|
|
|
837 |
|
|
static int mismatch; |
838 |
|
|
|
839 |
|
|
static void handle_merges (long int opcode) |
840 |
|
|
{ |
841 |
|
|
uae_u16 smsk; |
842 |
|
|
uae_u16 dmsk; |
843 |
|
|
int sbitdst, dstend; |
844 |
|
|
int srcreg, dstreg; |
845 |
|
|
|
846 |
|
|
if (table68k[opcode].spos == -1) { |
847 |
|
|
sbitdst = 1; smsk = 0; |
848 |
|
|
} else { |
849 |
|
|
switch (table68k[opcode].stype) { |
850 |
|
|
case 0: |
851 |
|
|
smsk = 7; sbitdst = 8; break; |
852 |
|
|
case 1: |
853 |
|
|
smsk = 255; sbitdst = 256; break; |
854 |
|
|
case 2: |
855 |
|
|
smsk = 15; sbitdst = 16; break; |
856 |
|
|
case 3: |
857 |
|
|
smsk = 7; sbitdst = 8; break; |
858 |
|
|
case 4: |
859 |
|
|
smsk = 7; sbitdst = 8; break; |
860 |
|
|
case 5: |
861 |
|
|
smsk = 63; sbitdst = 64; break; |
862 |
gbeauche |
1.5 |
case 6: |
863 |
|
|
smsk = 255; sbitdst = 256; break; |
864 |
gbeauche |
1.3 |
case 7: |
865 |
|
|
smsk = 3; sbitdst = 4; break; |
866 |
cebix |
1.1 |
default: |
867 |
|
|
smsk = 0; sbitdst = 0; |
868 |
|
|
abort(); |
869 |
|
|
break; |
870 |
|
|
} |
871 |
|
|
smsk <<= table68k[opcode].spos; |
872 |
|
|
} |
873 |
|
|
if (table68k[opcode].dpos == -1) { |
874 |
|
|
dstend = 1; dmsk = 0; |
875 |
|
|
} else { |
876 |
|
|
dmsk = 7 << table68k[opcode].dpos; |
877 |
|
|
dstend = 8; |
878 |
|
|
} |
879 |
|
|
for (srcreg=0; srcreg < sbitdst; srcreg++) { |
880 |
|
|
for (dstreg=0; dstreg < dstend; dstreg++) { |
881 |
|
|
uae_u16 code = opcode; |
882 |
|
|
|
883 |
|
|
code = (code & ~smsk) | (srcreg << table68k[opcode].spos); |
884 |
|
|
code = (code & ~dmsk) | (dstreg << table68k[opcode].dpos); |
885 |
|
|
|
886 |
|
|
/* Check whether this is in fact the same instruction. |
887 |
|
|
* The instructions should never differ, except for the |
888 |
|
|
* Bcc.(BW) case. */ |
889 |
|
|
if (table68k[code].mnemo != table68k[opcode].mnemo |
890 |
|
|
|| table68k[code].size != table68k[opcode].size |
891 |
|
|
|| table68k[code].suse != table68k[opcode].suse |
892 |
|
|
|| table68k[code].duse != table68k[opcode].duse) |
893 |
|
|
{ |
894 |
|
|
mismatch++; continue; |
895 |
|
|
} |
896 |
|
|
if (table68k[opcode].suse |
897 |
|
|
&& (table68k[opcode].spos != table68k[code].spos |
898 |
|
|
|| table68k[opcode].smode != table68k[code].smode |
899 |
|
|
|| table68k[opcode].stype != table68k[code].stype)) |
900 |
|
|
{ |
901 |
|
|
mismatch++; continue; |
902 |
|
|
} |
903 |
|
|
if (table68k[opcode].duse |
904 |
|
|
&& (table68k[opcode].dpos != table68k[code].dpos |
905 |
|
|
|| table68k[opcode].dmode != table68k[code].dmode)) |
906 |
|
|
{ |
907 |
|
|
mismatch++; continue; |
908 |
|
|
} |
909 |
|
|
|
910 |
|
|
if (code != opcode) |
911 |
|
|
table68k[code].handler = opcode; |
912 |
|
|
} |
913 |
|
|
} |
914 |
|
|
} |
915 |
|
|
|
916 |
|
|
void do_merges (void) |
917 |
|
|
{ |
918 |
|
|
long int opcode; |
919 |
|
|
int nr = 0; |
920 |
|
|
mismatch = 0; |
921 |
|
|
for (opcode = 0; opcode < 65536; opcode++) { |
922 |
|
|
if (table68k[opcode].handler != -1 || table68k[opcode].mnemo == i_ILLG) |
923 |
|
|
continue; |
924 |
|
|
nr++; |
925 |
|
|
handle_merges (opcode); |
926 |
|
|
} |
927 |
|
|
nr_cpuop_funcs = nr; |
928 |
|
|
} |
929 |
|
|
|
930 |
|
|
int get_no_mismatches (void) |
931 |
|
|
{ |
932 |
|
|
return mismatch; |
933 |
|
|
} |