ViewVC Help
View File | Revision Log | Show Annotations | Revision Graph | Root Listing
root/cebix/BasiliskII/src/uae_cpu/newcpu.h
(Generate patch)

Comparing BasiliskII/src/uae_cpu/newcpu.h (file contents):
Revision 1.5 by gbeauche, 2001-03-20T17:35:46Z vs.
Revision 1.10 by gbeauche, 2002-09-17T16:05:39Z

# Line 9 | Line 9
9   #ifndef NEWCPU_H
10   #define NEWCPU_H
11  
12 < #define SPCFLAG_STOP 2
13 < #define SPCFLAG_DISK 4
14 < #define SPCFLAG_INT  8
15 < #define SPCFLAG_BRK  16
16 < #define SPCFLAG_EXTRA_CYCLES 32
17 < #define SPCFLAG_TRACE 64
18 < #define SPCFLAG_DOTRACE 128
19 < #define SPCFLAG_DOINT 256
20 < #define SPCFLAG_BLTNASTY 512
21 < #define SPCFLAG_EXEC 1024
22 < #define SPCFLAG_MODE_CHANGE 8192
23 <
24 < #ifndef SET_CFLG
25 <
26 < #define SET_CFLG(x) (CFLG = (x))
27 < #define SET_NFLG(x) (NFLG = (x))
28 < #define SET_VFLG(x) (VFLG = (x))
29 < #define SET_ZFLG(x) (ZFLG = (x))
30 < #define SET_XFLG(x) (XFLG = (x))
31 <
32 < #define GET_CFLG CFLG
33 < #define GET_NFLG NFLG
34 < #define GET_VFLG VFLG
35 < #define GET_ZFLG ZFLG
36 < #define GET_XFLG XFLG
37 <
38 < #define CLEAR_CZNV do { \
39 < SET_CFLG (0); \
40 < SET_ZFLG (0); \
41 < SET_NFLG (0); \
42 < SET_VFLG (0); \
43 < } while (0)
44 <
45 < #define COPY_CARRY (SET_XFLG (GET_CFLG))
12 > #ifndef FLIGHT_RECORDER
13 > #define FLIGHT_RECORDER 0
14   #endif
15  
16 + #include "m68k.h"
17 + #include "readcpu.h"
18 + #include "spcflags.h"
19 +
20   extern int areg_byteinc[];
21   extern int imm8_table[];
22  
# Line 52 | Line 24 | extern int movem_index1[256];
24   extern int movem_index2[256];
25   extern int movem_next[256];
26  
55 extern int fpp_movem_index1[256];
56 extern int fpp_movem_index2[256];
57 extern int fpp_movem_next[256];
58
27   extern int broken_in;
28  
29 < typedef void REGPARAM2 cpuop_func (uae_u32) REGPARAM;
29 > /* Control flow information */
30 > #define CFLOW_NORMAL            0
31 > #define CFLOW_BRANCH            1
32 > #define CFLOW_JUMP                      2
33 > #define CFLOW_RETURN            3
34 > #define CFLOW_TRAP                      4
35 > #define CFLOW_SPCFLAGS          32      /* some spcflags are set */
36 > #define CFLOW_EXEC_RETURN       64      /* must exit from the execution loop */
37 >
38 > #define cpuop_rettype           void
39 > #define cpuop_return(v)         do { (v); return; } while (0)
40 >
41 > #ifdef X86_ASSEMBLY
42 > /* This hack seems to force all register saves (pushl %reg) to be moved to the
43 >   begining of the function, thus making it possible to cpuopti to remove them
44 >   since m68k_run_1 will save those registers before calling the instruction
45 >   handler */
46 > # define cpuop_tag(tag)         __asm__ __volatile__ ( "#cpuop_" tag )
47 > #else
48 > # define cpuop_tag(tag)         ;
49 > #endif
50 >
51 > #define cpuop_begin()           do { cpuop_tag("begin"); } while (0)
52 > #define cpuop_end(cflow)        do { cpuop_tag("end"); cpuop_return(cflow); } while (0)
53  
54 + typedef cpuop_rettype REGPARAM2 cpuop_func (uae_u32) REGPARAM;
55 +
56   struct cputbl {
57      cpuop_func *handler;
58 <    int specific;
58 >    uae_u16 specific;
59      uae_u16 opcode;
60   };
61  
62 < extern void REGPARAM2 op_illg (uae_u32) REGPARAM;
62 > extern cpuop_func *cpufunctbl[65536] ASM_SYM_FOR_FUNC ("cpufunctbl");
63  
64 < typedef char flagtype;
64 > #if USE_JIT
65 > typedef void compop_func (uae_u32) REGPARAM;
66  
67 < extern struct regstruct
68 < {
69 <    uae_u32 regs[16];
70 <    uaecptr  usp,isp,msp;
71 <    uae_u16 sr;
72 <    flagtype t1;
79 <    flagtype t0;
80 <    flagtype s;
81 <    flagtype m;
82 <    flagtype x;
83 <    flagtype stopped;
84 <    int intmask;
85 <
86 <    uae_u32 pc;
87 <    uae_u8 *pc_p;
88 <    uae_u8 *pc_oldp;
67 > struct comptbl {
68 >    compop_func *handler;
69 >        uae_u32         specific;
70 >        uae_u32         opcode;
71 > };
72 > #endif
73  
74 <    uae_u32 vbr,sfc,dfc;
74 > extern cpuop_rettype REGPARAM2 op_illg (uae_u32) REGPARAM;
75  
76 <    double fp[8];
77 <    uae_u32 fpcr,fpsr,fpiar;
76 > typedef char flagtype;
77 >
78 > struct regstruct {
79 >    uae_u32             regs[16];
80  
81 <    uae_u32 spcflags;
82 <    uae_u32 kick_mask;
81 >    uae_u32             pc;
82 >    uae_u8 *    pc_p;
83 >    uae_u8 *    pc_oldp;
84 >
85 >        spcflags_t      spcflags;
86 >    int                 intmask;
87 >
88 >    uae_u32             vbr, sfc, dfc;
89 >    uaecptr             usp, isp, msp;
90 >    uae_u16             sr;
91 >    flagtype    t1;
92 >    flagtype    t0;
93 >    flagtype    s;
94 >    flagtype    m;
95 >    flagtype    x;
96 >    flagtype    stopped;
97  
98 + #if USE_PREFETCH_BUFFER
99      /* Fellow sources say this is 4 longwords. That's impossible. It needs
100       * to be at least a longword. The HRM has some cryptic comment about two
101       * instructions being on the same longword boundary.
102       * The way this is implemented now seems like a good compromise.
103       */
104      uae_u32 prefetch;
105 < } regs, lastint_regs;
105 > #endif
106 > };
107 >
108 > extern regstruct regs, lastint_regs;
109  
110   #define m68k_dreg(r,num) ((r).regs[(num)])
111   #define m68k_areg(r,num) (((r).regs + 8)[(num)])
# Line 116 | Line 120 | extern struct regstruct
120   #define GET_OPCODE (get_iword (0))
121   #endif
122  
123 + #if USE_PREFETCH_BUFFER
124   static __inline__ uae_u32 get_ibyte_prefetch (uae_s32 o)
125   {
126      if (o > 3 || o < 0)
# Line 138 | Line 143 | static __inline__ uae_u32 get_ilong_pref
143          return do_get_mem_long(&regs.prefetch);
144      return (do_get_mem_word (((uae_u16 *)&regs.prefetch) + 1) << 16) | do_get_mem_word ((uae_u16 *)(regs.pc_p + 4));
145   }
146 + #endif
147  
148   #define m68k_incpc(o) (regs.pc_p += (o))
149  
# Line 190 | Line 196 | static __inline__ uae_u32 next_ilong (vo
196      return r;
197   }
198  
193 #if !defined USE_COMPILER
199   static __inline__ void m68k_setpc (uaecptr newpc)
200   {
201   #if REAL_ADDRESSING || DIRECT_ADDRESSING
# Line 200 | Line 205 | static __inline__ void m68k_setpc (uaecp
205      regs.pc = newpc;
206   #endif
207   }
203 #else
204 extern void m68k_setpc (uaecptr newpc);
205 #endif
208  
209   static __inline__ uaecptr m68k_getpc (void)
210   {
# Line 213 | Line 215 | static __inline__ uaecptr m68k_getpc (vo
215   #endif
216   }
217  
216 #ifdef USE_COMPILER
217 extern void m68k_setpc_fast (uaecptr newpc);
218 extern void m68k_setpc_bcc (uaecptr newpc);
219 extern void m68k_setpc_rte (uaecptr newpc);
220 #else
218   #define m68k_setpc_fast m68k_setpc
219   #define m68k_setpc_bcc  m68k_setpc
220   #define m68k_setpc_rte  m68k_setpc
224 #endif
221  
222   static __inline__ void m68k_do_rts(void)
223   {
# Line 246 | Line 242 | static __inline__ void m68k_do_jsr(uaecp
242   static __inline__ void m68k_setstopped (int stop)
243   {
244      regs.stopped = stop;
245 <    if (stop)
246 <        regs.spcflags |= SPCFLAG_STOP;
245 >    /* A traced STOP instruction drops through immediately without
246 >       actually stopping.  */
247 >    if (stop && (regs.spcflags & SPCFLAG_DOTRACE) == 0)
248 >    SPCFLAGS_SET( SPCFLAG_STOP );
249   }
250  
251   extern uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp);
# Line 259 | Line 257 | extern void MakeSR (void);
257   extern void MakeFromSR (void);
258   extern void Exception (int, uaecptr);
259   extern void dump_counts (void);
260 < extern void m68k_move2c (int, uae_u32 *);
261 < extern void m68k_movec2 (int, uae_u32 *);
260 > extern int m68k_move2c (int, uae_u32 *);
261 > extern int m68k_movec2 (int, uae_u32 *);
262   extern void m68k_divl (uae_u32, uae_u32, uae_u16, uaecptr);
263   extern void m68k_mull (uae_u32, uae_u32, uae_u16);
264 + extern void m68k_emulop (uae_u32);
265 + extern void m68k_emulop_return (void);
266   extern void init_m68k (void);
267   extern void exit_m68k (void);
268 extern void m68k_go (int);
268   extern void m68k_dumpstate (uaecptr *);
269   extern void m68k_disasm (uaecptr, uaecptr *, int);
270   extern void m68k_reset (void);
271   extern void m68k_enter_debugger(void);
272 + extern int m68k_do_specialties(void);
273  
274   extern void mmu_op (uae_u32, uae_u16);
275  
276 extern void fpp_opp (uae_u32, uae_u16);
277 extern void fdbcc_opp (uae_u32, uae_u16);
278 extern void fscc_opp (uae_u32, uae_u16);
279 extern void ftrapcc_opp (uae_u32,uaecptr);
280 extern void fbcc_opp (uae_u32, uaecptr, uae_u32);
281 extern void fsave_opp (uae_u32);
282 extern void frestore_opp (uae_u32);
283
284 extern void fpu_set_integral_fpu (bool is_integral);
285 extern void fpu_init (void);
286 extern void fpu_exit (void);
287 extern void fpu_reset (void);
288
276   /* Opcode of faulting instruction */
277   extern uae_u16 last_op_for_exception_3;
278   /* PC at fault time */
# Line 296 | Line 283 | extern uaecptr last_fault_for_exception_
283   #define CPU_OP_NAME(a) op ## a
284  
285   /* 68020 + 68881 */
286 < extern struct cputbl op_smalltbl_0[];
286 > extern struct cputbl op_smalltbl_0_ff[];
287   /* 68020 */
288 < extern struct cputbl op_smalltbl_1[];
288 > extern struct cputbl op_smalltbl_1_ff[];
289   /* 68010 */
290 < extern struct cputbl op_smalltbl_2[];
290 > extern struct cputbl op_smalltbl_2_ff[];
291   /* 68000 */
292 < extern struct cputbl op_smalltbl_3[];
292 > extern struct cputbl op_smalltbl_3_ff[];
293   /* 68000 slow but compatible.  */
294 < extern struct cputbl op_smalltbl_4[];
308 <
309 < extern cpuop_func *cpufunctbl[65536] ASM_SYM_FOR_FUNC ("cpufunctbl");
294 > extern struct cputbl op_smalltbl_4_ff[];
295  
296 + #if FLIGHT_RECORDER
297 + extern void m68k_record_step(uaecptr);
298 + #endif
299 + extern void m68k_do_execute(void);
300 + extern void m68k_execute(void);
301 + #if USE_JIT
302 + extern void m68k_do_compile_execute(void);
303 + extern void m68k_compile_execute(void);
304 + #endif
305 +
306   #endif /* NEWCPU_H */

Diff Legend

Removed lines
+ Added lines
< Changed lines
> Changed lines