| 6 |
|
* Copyright 1995 Bernd Schmidt |
| 7 |
|
*/ |
| 8 |
|
|
| 9 |
< |
#define SPCFLAG_STOP 2 |
| 10 |
< |
#define SPCFLAG_DISK 4 |
| 11 |
< |
#define SPCFLAG_INT 8 |
| 12 |
< |
#define SPCFLAG_BRK 16 |
| 13 |
< |
#define SPCFLAG_EXTRA_CYCLES 32 |
| 14 |
< |
#define SPCFLAG_TRACE 64 |
| 15 |
< |
#define SPCFLAG_DOTRACE 128 |
| 16 |
< |
#define SPCFLAG_DOINT 256 |
| 17 |
< |
#define SPCFLAG_BLTNASTY 512 |
| 18 |
< |
#define SPCFLAG_EXEC 1024 |
| 19 |
< |
#define SPCFLAG_MODE_CHANGE 8192 |
| 20 |
< |
|
| 21 |
< |
#ifndef SET_CFLG |
| 22 |
< |
|
| 23 |
< |
#define SET_CFLG(x) (CFLG = (x)) |
| 24 |
< |
#define SET_NFLG(x) (NFLG = (x)) |
| 25 |
< |
#define SET_VFLG(x) (VFLG = (x)) |
| 26 |
< |
#define SET_ZFLG(x) (ZFLG = (x)) |
| 27 |
< |
#define SET_XFLG(x) (XFLG = (x)) |
| 28 |
< |
|
| 29 |
< |
#define GET_CFLG CFLG |
| 30 |
< |
#define GET_NFLG NFLG |
| 31 |
< |
#define GET_VFLG VFLG |
| 32 |
< |
#define GET_ZFLG ZFLG |
| 33 |
< |
#define GET_XFLG XFLG |
| 34 |
< |
|
| 35 |
< |
#define CLEAR_CZNV do { \ |
| 36 |
< |
SET_CFLG (0); \ |
| 37 |
< |
SET_ZFLG (0); \ |
| 38 |
< |
SET_NFLG (0); \ |
| 39 |
< |
SET_VFLG (0); \ |
| 40 |
< |
} while (0) |
| 9 |
> |
#ifndef NEWCPU_H |
| 10 |
> |
#define NEWCPU_H |
| 11 |
|
|
| 12 |
< |
#define COPY_CARRY (SET_XFLG (GET_CFLG)) |
| 12 |
> |
#ifndef FLIGHT_RECORDER |
| 13 |
> |
#define FLIGHT_RECORDER 0 |
| 14 |
|
#endif |
| 15 |
|
|
| 16 |
+ |
#include "m68k.h" |
| 17 |
+ |
#include "readcpu.h" |
| 18 |
+ |
#include "spcflags.h" |
| 19 |
+ |
|
| 20 |
|
extern int areg_byteinc[]; |
| 21 |
|
extern int imm8_table[]; |
| 22 |
|
|
| 24 |
|
extern int movem_index2[256]; |
| 25 |
|
extern int movem_next[256]; |
| 26 |
|
|
| 52 |
– |
extern int fpp_movem_index1[256]; |
| 53 |
– |
extern int fpp_movem_index2[256]; |
| 54 |
– |
extern int fpp_movem_next[256]; |
| 55 |
– |
|
| 27 |
|
extern int broken_in; |
| 28 |
|
|
| 29 |
< |
typedef unsigned long REGPARAM2 cpuop_func (uae_u32) REGPARAM; |
| 29 |
> |
/* Control flow information */ |
| 30 |
> |
#define CFLOW_NORMAL 0 |
| 31 |
> |
#define CFLOW_BRANCH 1 |
| 32 |
> |
#define CFLOW_JUMP 2 |
| 33 |
> |
#define CFLOW_RETURN 3 |
| 34 |
> |
#define CFLOW_TRAP 4 |
| 35 |
> |
#define CFLOW_SPCFLAGS 32 /* some spcflags are set */ |
| 36 |
> |
#define CFLOW_EXEC_RETURN 64 /* must exit from the execution loop */ |
| 37 |
> |
|
| 38 |
> |
#define cpuop_rettype void |
| 39 |
> |
#define cpuop_return(v) do { (v); return; } while (0) |
| 40 |
> |
|
| 41 |
> |
#ifdef X86_ASSEMBLY |
| 42 |
> |
/* This hack seems to force all register saves (pushl %reg) to be moved to the |
| 43 |
> |
begining of the function, thus making it possible to cpuopti to remove them |
| 44 |
> |
since m68k_run_1 will save those registers before calling the instruction |
| 45 |
> |
handler */ |
| 46 |
> |
# define cpuop_tag(tag) __asm__ __volatile__ ( "#cpuop_" tag ) |
| 47 |
> |
#else |
| 48 |
> |
# define cpuop_tag(tag) ; |
| 49 |
> |
#endif |
| 50 |
|
|
| 51 |
+ |
#define cpuop_begin() do { cpuop_tag("begin"); } while (0) |
| 52 |
+ |
#define cpuop_end(cflow) do { cpuop_tag("end"); cpuop_return(cflow); } while (0) |
| 53 |
+ |
|
| 54 |
+ |
typedef cpuop_rettype REGPARAM2 cpuop_func (uae_u32) REGPARAM; |
| 55 |
+ |
|
| 56 |
|
struct cputbl { |
| 57 |
|
cpuop_func *handler; |
| 58 |
< |
int specific; |
| 58 |
> |
uae_u16 specific; |
| 59 |
|
uae_u16 opcode; |
| 60 |
|
}; |
| 61 |
|
|
| 62 |
< |
extern unsigned long REGPARAM2 op_illg (uae_u32) REGPARAM; |
| 62 |
> |
extern cpuop_func *cpufunctbl[65536] ASM_SYM_FOR_FUNC ("cpufunctbl"); |
| 63 |
> |
|
| 64 |
> |
#if USE_JIT |
| 65 |
> |
typedef void compop_func (uae_u32) REGPARAM; |
| 66 |
|
|
| 67 |
< |
typedef char flagtype; |
| 67 |
> |
struct comptbl { |
| 68 |
> |
compop_func *handler; |
| 69 |
> |
uae_u32 specific; |
| 70 |
> |
uae_u32 opcode; |
| 71 |
> |
}; |
| 72 |
> |
#endif |
| 73 |
|
|
| 74 |
< |
extern struct regstruct |
| 71 |
< |
{ |
| 72 |
< |
uae_u32 regs[16]; |
| 73 |
< |
uaecptr usp,isp,msp; |
| 74 |
< |
uae_u16 sr; |
| 75 |
< |
flagtype t1; |
| 76 |
< |
flagtype t0; |
| 77 |
< |
flagtype s; |
| 78 |
< |
flagtype m; |
| 79 |
< |
flagtype x; |
| 80 |
< |
flagtype stopped; |
| 81 |
< |
int intmask; |
| 82 |
< |
|
| 83 |
< |
uae_u32 pc; |
| 84 |
< |
uae_u8 *pc_p; |
| 85 |
< |
uae_u8 *pc_oldp; |
| 74 |
> |
extern cpuop_rettype REGPARAM2 op_illg (uae_u32) REGPARAM; |
| 75 |
|
|
| 76 |
< |
uae_u32 vbr,sfc,dfc; |
| 76 |
> |
typedef char flagtype; |
| 77 |
|
|
| 78 |
< |
double fp[8]; |
| 79 |
< |
uae_u32 fpcr,fpsr,fpiar; |
| 78 |
> |
struct regstruct { |
| 79 |
> |
uae_u32 regs[16]; |
| 80 |
|
|
| 81 |
< |
uae_u32 spcflags; |
| 82 |
< |
uae_u32 kick_mask; |
| 81 |
> |
uae_u32 pc; |
| 82 |
> |
uae_u8 * pc_p; |
| 83 |
> |
uae_u8 * pc_oldp; |
| 84 |
> |
|
| 85 |
> |
spcflags_t spcflags; |
| 86 |
> |
int intmask; |
| 87 |
> |
|
| 88 |
> |
uae_u32 vbr, sfc, dfc; |
| 89 |
> |
uaecptr usp, isp, msp; |
| 90 |
> |
uae_u16 sr; |
| 91 |
> |
flagtype t1; |
| 92 |
> |
flagtype t0; |
| 93 |
> |
flagtype s; |
| 94 |
> |
flagtype m; |
| 95 |
> |
flagtype x; |
| 96 |
> |
flagtype stopped; |
| 97 |
|
|
| 98 |
+ |
#if USE_PREFETCH_BUFFER |
| 99 |
|
/* Fellow sources say this is 4 longwords. That's impossible. It needs |
| 100 |
|
* to be at least a longword. The HRM has some cryptic comment about two |
| 101 |
|
* instructions being on the same longword boundary. |
| 102 |
|
* The way this is implemented now seems like a good compromise. |
| 103 |
|
*/ |
| 104 |
|
uae_u32 prefetch; |
| 105 |
< |
} regs, lastint_regs; |
| 105 |
> |
#endif |
| 106 |
> |
}; |
| 107 |
> |
|
| 108 |
> |
extern regstruct regs, lastint_regs; |
| 109 |
|
|
| 110 |
|
#define m68k_dreg(r,num) ((r).regs[(num)]) |
| 111 |
|
#define m68k_areg(r,num) (((r).regs + 8)[(num)]) |
| 120 |
|
#define GET_OPCODE (get_iword (0)) |
| 121 |
|
#endif |
| 122 |
|
|
| 123 |
+ |
#if USE_PREFETCH_BUFFER |
| 124 |
|
static __inline__ uae_u32 get_ibyte_prefetch (uae_s32 o) |
| 125 |
|
{ |
| 126 |
|
if (o > 3 || o < 0) |
| 143 |
|
return do_get_mem_long(®s.prefetch); |
| 144 |
|
return (do_get_mem_word (((uae_u16 *)®s.prefetch) + 1) << 16) | do_get_mem_word ((uae_u16 *)(regs.pc_p + 4)); |
| 145 |
|
} |
| 146 |
+ |
#endif |
| 147 |
|
|
| 148 |
|
#define m68k_incpc(o) (regs.pc_p += (o)) |
| 149 |
|
|
| 150 |
|
static __inline__ void fill_prefetch_0 (void) |
| 151 |
|
{ |
| 152 |
+ |
#if USE_PREFETCH_BUFFER |
| 153 |
|
uae_u32 r; |
| 154 |
|
#ifdef UNALIGNED_PROFITABLE |
| 155 |
|
r = *(uae_u32 *)regs.pc_p; |
| 158 |
|
r = do_get_mem_long ((uae_u32 *)regs.pc_p); |
| 159 |
|
do_put_mem_long (®s.prefetch, r); |
| 160 |
|
#endif |
| 161 |
+ |
#endif |
| 162 |
|
} |
| 163 |
|
|
| 164 |
|
#if 0 |
| 196 |
|
return r; |
| 197 |
|
} |
| 198 |
|
|
| 188 |
– |
#if !defined USE_COMPILER |
| 199 |
|
static __inline__ void m68k_setpc (uaecptr newpc) |
| 200 |
|
{ |
| 201 |
+ |
#if REAL_ADDRESSING || DIRECT_ADDRESSING |
| 202 |
+ |
regs.pc_p = get_real_address(newpc); |
| 203 |
+ |
#else |
| 204 |
|
regs.pc_p = regs.pc_oldp = get_real_address(newpc); |
| 205 |
|
regs.pc = newpc; |
| 193 |
– |
} |
| 194 |
– |
#else |
| 195 |
– |
extern void m68k_setpc (uaecptr newpc); |
| 206 |
|
#endif |
| 207 |
+ |
} |
| 208 |
|
|
| 209 |
|
static __inline__ uaecptr m68k_getpc (void) |
| 210 |
|
{ |
| 211 |
+ |
#if REAL_ADDRESSING || DIRECT_ADDRESSING |
| 212 |
+ |
return get_virtual_address(regs.pc_p); |
| 213 |
+ |
#else |
| 214 |
|
return regs.pc + ((char *)regs.pc_p - (char *)regs.pc_oldp); |
| 215 |
+ |
#endif |
| 216 |
|
} |
| 217 |
|
|
| 203 |
– |
static __inline__ uaecptr m68k_getpc_p (uae_u8 *p) |
| 204 |
– |
{ |
| 205 |
– |
return regs.pc + ((char *)p - (char *)regs.pc_oldp); |
| 206 |
– |
} |
| 207 |
– |
|
| 208 |
– |
#ifdef USE_COMPILER |
| 209 |
– |
extern void m68k_setpc_fast (uaecptr newpc); |
| 210 |
– |
extern void m68k_setpc_bcc (uaecptr newpc); |
| 211 |
– |
extern void m68k_setpc_rte (uaecptr newpc); |
| 212 |
– |
#else |
| 218 |
|
#define m68k_setpc_fast m68k_setpc |
| 219 |
|
#define m68k_setpc_bcc m68k_setpc |
| 220 |
|
#define m68k_setpc_rte m68k_setpc |
| 221 |
< |
#endif |
| 221 |
> |
|
| 222 |
> |
static __inline__ void m68k_do_rts(void) |
| 223 |
> |
{ |
| 224 |
> |
m68k_setpc(get_long(m68k_areg(regs, 7))); |
| 225 |
> |
m68k_areg(regs, 7) += 4; |
| 226 |
> |
} |
| 227 |
> |
|
| 228 |
> |
static __inline__ void m68k_do_bsr(uaecptr oldpc, uae_s32 offset) |
| 229 |
> |
{ |
| 230 |
> |
m68k_areg(regs, 7) -= 4; |
| 231 |
> |
put_long(m68k_areg(regs, 7), oldpc); |
| 232 |
> |
m68k_incpc(offset); |
| 233 |
> |
} |
| 234 |
> |
|
| 235 |
> |
static __inline__ void m68k_do_jsr(uaecptr oldpc, uaecptr dest) |
| 236 |
> |
{ |
| 237 |
> |
m68k_areg(regs, 7) -= 4; |
| 238 |
> |
put_long(m68k_areg(regs, 7), oldpc); |
| 239 |
> |
m68k_setpc(dest); |
| 240 |
> |
} |
| 241 |
|
|
| 242 |
|
static __inline__ void m68k_setstopped (int stop) |
| 243 |
|
{ |
| 244 |
|
regs.stopped = stop; |
| 245 |
< |
if (stop) |
| 246 |
< |
regs.spcflags |= SPCFLAG_STOP; |
| 245 |
> |
/* A traced STOP instruction drops through immediately without |
| 246 |
> |
actually stopping. */ |
| 247 |
> |
if (stop && (regs.spcflags & SPCFLAG_DOTRACE) == 0) |
| 248 |
> |
SPCFLAGS_SET( SPCFLAG_STOP ); |
| 249 |
|
} |
| 250 |
|
|
| 251 |
|
extern uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp); |
| 257 |
|
extern void MakeFromSR (void); |
| 258 |
|
extern void Exception (int, uaecptr); |
| 259 |
|
extern void dump_counts (void); |
| 260 |
< |
extern void m68k_move2c (int, uae_u32 *); |
| 261 |
< |
extern void m68k_movec2 (int, uae_u32 *); |
| 260 |
> |
extern int m68k_move2c (int, uae_u32 *); |
| 261 |
> |
extern int m68k_movec2 (int, uae_u32 *); |
| 262 |
|
extern void m68k_divl (uae_u32, uae_u32, uae_u16, uaecptr); |
| 263 |
|
extern void m68k_mull (uae_u32, uae_u32, uae_u16); |
| 264 |
+ |
extern void m68k_emulop (uae_u32); |
| 265 |
+ |
extern void m68k_emulop_return (void); |
| 266 |
|
extern void init_m68k (void); |
| 267 |
< |
extern void m68k_go (int); |
| 267 |
> |
extern void exit_m68k (void); |
| 268 |
|
extern void m68k_dumpstate (uaecptr *); |
| 269 |
|
extern void m68k_disasm (uaecptr, uaecptr *, int); |
| 270 |
|
extern void m68k_reset (void); |
| 271 |
|
extern void m68k_enter_debugger(void); |
| 272 |
+ |
extern int m68k_do_specialties(void); |
| 273 |
|
|
| 274 |
|
extern void mmu_op (uae_u32, uae_u16); |
| 275 |
|
|
| 247 |
– |
extern void fpp_opp (uae_u32, uae_u16); |
| 248 |
– |
extern void fdbcc_opp (uae_u32, uae_u16); |
| 249 |
– |
extern void fscc_opp (uae_u32, uae_u16); |
| 250 |
– |
extern void ftrapcc_opp (uae_u32,uaecptr); |
| 251 |
– |
extern void fbcc_opp (uae_u32, uaecptr, uae_u32); |
| 252 |
– |
extern void fsave_opp (uae_u32); |
| 253 |
– |
extern void frestore_opp (uae_u32); |
| 254 |
– |
|
| 276 |
|
/* Opcode of faulting instruction */ |
| 277 |
|
extern uae_u16 last_op_for_exception_3; |
| 278 |
|
/* PC at fault time */ |
| 283 |
|
#define CPU_OP_NAME(a) op ## a |
| 284 |
|
|
| 285 |
|
/* 68020 + 68881 */ |
| 286 |
< |
extern struct cputbl op_smalltbl_0[]; |
| 286 |
> |
extern struct cputbl op_smalltbl_0_ff[]; |
| 287 |
|
/* 68020 */ |
| 288 |
< |
extern struct cputbl op_smalltbl_1[]; |
| 288 |
> |
extern struct cputbl op_smalltbl_1_ff[]; |
| 289 |
|
/* 68010 */ |
| 290 |
< |
extern struct cputbl op_smalltbl_2[]; |
| 290 |
> |
extern struct cputbl op_smalltbl_2_ff[]; |
| 291 |
|
/* 68000 */ |
| 292 |
< |
extern struct cputbl op_smalltbl_3[]; |
| 292 |
> |
extern struct cputbl op_smalltbl_3_ff[]; |
| 293 |
|
/* 68000 slow but compatible. */ |
| 294 |
< |
extern struct cputbl op_smalltbl_4[]; |
| 274 |
< |
|
| 275 |
< |
extern cpuop_func *cpufunctbl[65536] ASM_SYM_FOR_FUNC ("cpufunctbl"); |
| 294 |
> |
extern struct cputbl op_smalltbl_4_ff[]; |
| 295 |
|
|
| 296 |
+ |
#if FLIGHT_RECORDER |
| 297 |
+ |
extern void m68k_record_step(uaecptr); |
| 298 |
+ |
#endif |
| 299 |
+ |
extern void m68k_do_execute(void); |
| 300 |
+ |
extern void m68k_execute(void); |
| 301 |
+ |
#if USE_JIT |
| 302 |
+ |
extern void m68k_do_compile_execute(void); |
| 303 |
+ |
extern void m68k_compile_execute(void); |
| 304 |
+ |
#endif |
| 305 |
+ |
|
| 306 |
+ |
#endif /* NEWCPU_H */ |
