183 |
|
for (j = 7 ; j >= 0 ; j--) { |
184 |
|
if (i & (1 << j)) break; |
185 |
|
} |
186 |
< |
fpp_movem_index1[i] = j; |
187 |
< |
fpp_movem_index2[i] = 7-j; |
186 |
> |
fpp_movem_index1[i] = 7-j; |
187 |
> |
fpp_movem_index2[i] = j; |
188 |
|
fpp_movem_next[i] = i & (~(1 << j)); |
189 |
|
} |
190 |
|
#if COUNT_INSTRS |
207 |
|
do_merges (); |
208 |
|
|
209 |
|
build_cpufunctbl (); |
210 |
+ |
|
211 |
+ |
fpu_init (); |
212 |
+ |
fpu_set_integral_fpu (CPUType == 4); |
213 |
+ |
} |
214 |
+ |
|
215 |
+ |
void exit_m68k (void) |
216 |
+ |
{ |
217 |
+ |
fpu_exit (); |
218 |
|
} |
219 |
|
|
220 |
|
struct regstruct regs, lastint_regs; |
258 |
|
disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; |
259 |
|
addr = m68k_areg(regs,reg) + (uae_s16)disp16; |
260 |
|
sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff, |
261 |
< |
(long unsigned int)addr); |
261 |
> |
(unsigned long)addr); |
262 |
|
break; |
263 |
|
case Ad8r: |
264 |
|
dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; |
291 |
|
dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', |
292 |
|
1 << ((dp >> 9) & 3), |
293 |
|
disp,outer, |
294 |
< |
(long unsigned int)addr); |
294 |
> |
(unsigned long)addr); |
295 |
|
} else { |
296 |
|
addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg; |
297 |
|
sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg, |
298 |
|
dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', |
299 |
|
1 << ((dp >> 9) & 3), disp8, |
300 |
< |
(long unsigned int)addr); |
300 |
> |
(unsigned long)addr); |
301 |
|
} |
302 |
|
break; |
303 |
|
case PC16: |
304 |
|
addr = m68k_getpc () + m68kpc_offset; |
305 |
|
disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; |
306 |
|
addr += (uae_s16)disp16; |
307 |
< |
sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(long unsigned int)addr); |
307 |
> |
sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr); |
308 |
|
break; |
309 |
|
case PC8r: |
310 |
|
addr = m68k_getpc () + m68kpc_offset; |
338 |
|
dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', |
339 |
|
1 << ((dp >> 9) & 3), |
340 |
|
disp,outer, |
341 |
< |
(long unsigned int)addr); |
341 |
> |
(unsigned long)addr); |
342 |
|
} else { |
343 |
|
addr += (uae_s32)((uae_s8)disp8) + dispreg; |
344 |
|
sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D', |
345 |
|
(int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3), |
346 |
< |
disp8, (long unsigned int)addr); |
346 |
> |
disp8, (unsigned long)addr); |
347 |
|
} |
348 |
|
break; |
349 |
|
case absw: |
350 |
< |
sprintf (buffer,"$%08lx", (long unsigned int)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset)); |
350 |
> |
sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset)); |
351 |
|
m68kpc_offset += 2; |
352 |
|
break; |
353 |
|
case absl: |
354 |
< |
sprintf (buffer,"$%08lx", (long unsigned int)get_ilong_1 (m68kpc_offset)); |
354 |
> |
sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset)); |
355 |
|
m68kpc_offset += 4; |
356 |
|
break; |
357 |
|
case imm: |
365 |
|
m68kpc_offset += 2; |
366 |
|
break; |
367 |
|
case sz_long: |
368 |
< |
sprintf (buffer,"#$%08lx", (long unsigned int)(get_ilong_1 (m68kpc_offset))); |
368 |
> |
sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset))); |
369 |
|
m68kpc_offset += 4; |
370 |
|
break; |
371 |
|
default: |
385 |
|
case imm2: |
386 |
|
offset = (uae_s32)get_ilong_1 (m68kpc_offset); |
387 |
|
m68kpc_offset += 4; |
388 |
< |
sprintf (buffer,"#$%08lx", (long unsigned int)offset); |
388 |
> |
sprintf (buffer,"#$%08lx", (unsigned long)offset); |
389 |
|
break; |
390 |
|
case immi: |
391 |
|
offset = (uae_s32)(uae_s8)(reg & 0xff); |
392 |
< |
sprintf (buffer,"#$%08lx", (long unsigned int)offset); |
392 |
> |
sprintf (buffer,"#$%08lx", (unsigned long)offset); |
393 |
|
break; |
394 |
|
default: |
395 |
|
break; |
1055 |
|
regs.spcflags = 0; |
1056 |
|
regs.intmask = 7; |
1057 |
|
regs.vbr = regs.sfc = regs.dfc = 0; |
1058 |
< |
regs.fpcr = regs.fpsr = regs.fpiar = 0; |
1058 |
> |
/* gb-- moved into {fpp,fpu_x86}.cpp::fpu_init() |
1059 |
> |
regs.fpcr = regs.fpsr = regs.fpiar = 0; */ |
1060 |
> |
fpu_reset(); |
1061 |
|
} |
1062 |
|
|
1063 |
|
void REGPARAM2 op_illg (uae_u32 opcode) |