[ViewVC] Diff of: cebix/BasiliskII/src/uae

Comparing BasiliskII/src/uae_cpu/newcpu.cpp (file contents):
Revision 1.1 by cebix, 1999-10-03T14:16:26Z vs.
Revision 1.8 by gbeauche, 2001-03-20T17:35:46Z

#	Line 22 \| Line 22 \| extern int intlev(void); // From baisili
22		#include "memory.h"
23		#include "readcpu.h"
24		#include "newcpu.h"
25	–	#include "compiler.h"
25
26		int quit_program = 0;
27		int debugging = 0;
#	Line 111 \| Line 110 \| static __inline__ unsigned int cft_map (
110		#endif
111		}
112
113	<	static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM;
113	>	static void REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM;
114
115	<	static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
115	>	static void REGPARAM2 op_illg_1 (uae_u32 opcode)
116		{
117		op_illg (cft_map (opcode));
119	–	return 4;
118		}
119
120		static void build_cpufunctbl (void)
121		{
122		int i;
123		unsigned long opcode;
124	<	int cpu_level = (FPUType ? 3 : CPUType >= 2 ? 2 : CPUType == 1 ? 1 : 0);
125	<	struct cputbl *tbl = (cpu_level == 3 ? op_smalltbl_0
126	<	: cpu_level == 2 ? op_smalltbl_1
127	<	: cpu_level == 1 ? op_smalltbl_2
128	<	: op_smalltbl_3);
124	>	int cpu_level = 0; // 68000 (default)
125	>	if (CPUType == 4)
126	>	cpu_level = 4; // 68040 with FPU
127	>	else {
128	>	if (FPUType)
129	>	cpu_level = 3; // 68020 with FPU
130	>	else if (CPUType >= 2)
131	>	cpu_level = 2; // 68020
132	>	else if (CPUType == 1)
133	>	cpu_level = 1;
134	>	}
135	>	struct cputbl *tbl = (
136	>	cpu_level == 4 ? op_smalltbl_0
137	>	: cpu_level == 3 ? op_smalltbl_1
138	>	: cpu_level == 2 ? op_smalltbl_2
139	>	: cpu_level == 1 ? op_smalltbl_3
140	>	: op_smalltbl_4);
141
142		for (opcode = 0; opcode < 65536; opcode++)
143		cpufunctbl[cft_map (opcode)] = op_illg_1;
#	Line 172 \| Line 182 \| void init_m68k (void)
182		for (j = 7 ; j >= 0 ; j--) {
183		if (i & (1 << j)) break;
184		}
185	<	fpp_movem_index1[i] = j;
186	<	fpp_movem_index2[i] = 7-j;
185	>	fpp_movem_index1[i] = 7-j;
186	>	fpp_movem_index2[i] = j;
187		fpp_movem_next[i] = i & (~(1 << j));
188		}
189		#if COUNT_INSTRS
#	Line 196 \| Line 206 \| void init_m68k (void)
206		do_merges ();
207
208		build_cpufunctbl ();
209	+
210	+	fpu_init ();
211	+	fpu_set_integral_fpu (CPUType == 4);
212	+	}
213	+
214	+	void exit_m68k (void)
215	+	{
216	+	fpu_exit ();
217		}
218
219		struct regstruct regs, lastint_regs;
#	Line 204 \| Line 222 \| static int backup_pointer = 0;
222		static long int m68kpc_offset;
223		int lastint_no;
224
225	+	#if REAL_ADDRESSING \|\| DIRECT_ADDRESSING
226	+	#define get_ibyte_1(o) get_byte(get_virtual_address(regs.pc_p) + (o) + 1)
227	+	#define get_iword_1(o) get_word(get_virtual_address(regs.pc_p) + (o))
228	+	#define get_ilong_1(o) get_long(get_virtual_address(regs.pc_p) + (o))
229	+	#else
230		#define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
231		#define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
232		#define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
233	+	#endif
234
235		uae_s32 ShowEA (int reg, amodes mode, wordsizes size, char *buf)
236		{
#	Line 239 \| Line 263 \| uae_s32 ShowEA (int reg, amodes mode, wo
263		disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
264		addr = m68k_areg(regs,reg) + (uae_s16)disp16;
265		sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
266	<	(long unsigned int)addr);
266	>	(unsigned long)addr);
267		break;
268		case Ad8r:
269		dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
#	Line 272 \| Line 296 \| uae_s32 ShowEA (int reg, amodes mode, wo
296		dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
297		1 << ((dp >> 9) & 3),
298		disp,outer,
299	<	(long unsigned int)addr);
299	>	(unsigned long)addr);
300		} else {
301		addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
302		sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
303		dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
304		1 << ((dp >> 9) & 3), disp8,
305	<	(long unsigned int)addr);
305	>	(unsigned long)addr);
306		}
307		break;
308		case PC16:
309		addr = m68k_getpc () + m68kpc_offset;
310		disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
311		addr += (uae_s16)disp16;
312	<	sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(long unsigned int)addr);
312	>	sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
313		break;
314		case PC8r:
315		addr = m68k_getpc () + m68kpc_offset;
#	Line 319 \| Line 343 \| uae_s32 ShowEA (int reg, amodes mode, wo
343		dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
344		1 << ((dp >> 9) & 3),
345		disp,outer,
346	<	(long unsigned int)addr);
346	>	(unsigned long)addr);
347		} else {
348		addr += (uae_s32)((uae_s8)disp8) + dispreg;
349		sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
350		(int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
351	<	disp8, (long unsigned int)addr);
351	>	disp8, (unsigned long)addr);
352		}
353		break;
354		case absw:
355	<	sprintf (buffer,"$%08lx", (long unsigned int)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
355	>	sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
356		m68kpc_offset += 2;
357		break;
358		case absl:
359	<	sprintf (buffer,"$%08lx", (long unsigned int)get_ilong_1 (m68kpc_offset));
359	>	sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
360		m68kpc_offset += 4;
361		break;
362		case imm:
#	Line 346 \| Line 370 \| uae_s32 ShowEA (int reg, amodes mode, wo
370		m68kpc_offset += 2;
371		break;
372		case sz_long:
373	<	sprintf (buffer,"#$%08lx", (long unsigned int)(get_ilong_1 (m68kpc_offset)));
373	>	sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
374		m68kpc_offset += 4;
375		break;
376		default:
#	Line 366 \| Line 390 \| uae_s32 ShowEA (int reg, amodes mode, wo
390		case imm2:
391		offset = (uae_s32)get_ilong_1 (m68kpc_offset);
392		m68kpc_offset += 4;
393	<	sprintf (buffer,"#$%08lx", (long unsigned int)offset);
393	>	sprintf (buffer,"#$%08lx", (unsigned long)offset);
394		break;
395		case immi:
396		offset = (uae_s32)(uae_s8)(reg & 0xff);
397	<	sprintf (buffer,"#$%08lx", (long unsigned int)offset);
397	>	sprintf (buffer,"#$%08lx", (unsigned long)offset);
398		break;
399		default:
400		break;
#	Line 634 \| Line 658 \| void MakeFromSR (void)
658
659		void Exception(int nr, uaecptr oldpc)
660		{
637	–	compiler_flush_jsr_stack();
661		MakeSR();
662		if (!regs.s) {
663		regs.usp = m68k_areg(regs, 7);
#	Line 710 \| Line 733 \| static void Interrupt(int nr)
733		regs.spcflags \|= SPCFLAG_INT;
734		}
735
736	<	static int caar, cacr;
736	>	static int caar, cacr, tc, itt0, itt1, dtt0, dtt1;
737
738		void m68k_move2c (int regno, uae_u32 *regp)
739		{
#	Line 721 \| Line 744 \| *void m68k_move2c (int regno, uae_u32 re**
744		case 0: regs.sfc = *regp & 7; break;
745		case 1: regs.dfc = *regp & 7; break;
746		case 2: cacr = regp & 0x3; break; / ignore C and CE */
747	+	case 3: tc = *regp & 0xc000; break;
748	+	case 4: itt0 = *regp & 0xffffe364; break;
749	+	case 5: itt1 = *regp & 0xffffe364; break;
750	+	case 6: dtt0 = *regp & 0xffffe364; break;
751	+	case 7: dtt1 = *regp & 0xffffe364; break;
752		case 0x800: regs.usp = *regp; break;
753		case 0x801: regs.vbr = *regp; break;
754		case 0x802: caar = *regp &0xfc; break;
#	Line 741 \| Line 769 \| *void m68k_movec2 (int regno, uae_u32 re**
769		case 0: *regp = regs.sfc; break;
770		case 1: *regp = regs.dfc; break;
771		case 2: *regp = cacr; break;
772	+	case 3: *regp = tc; break;
773	+	case 4: *regp = itt0; break;
774	+	case 5: *regp = itt1; break;
775	+	case 6: *regp = dtt0; break;
776	+	case 7: *regp = dtt1; break;
777		case 0x800: *regp = regs.usp; break;
778		case 0x801: *regp = regs.vbr; break;
779		case 0x802: *regp = caar; break;
#	Line 1026 \| Line 1059 \| void m68k_reset (void)
1059		regs.spcflags = 0;
1060		regs.intmask = 7;
1061		regs.vbr = regs.sfc = regs.dfc = 0;
1062	<	regs.fpcr = regs.fpsr = regs.fpiar = 0;
1062	>	/* gb-- moved into {fpp,fpu_x86}.cpp::fpu_init()
1063	>	regs.fpcr = regs.fpsr = regs.fpiar = 0; */
1064	>	fpu_reset();
1065		}
1066
1067	<	unsigned long REGPARAM2 op_illg (uae_u32 opcode)
1067	>	void REGPARAM2 op_illg (uae_u32 opcode)
1068		{
1069		uaecptr pc = m68k_getpc ();
1070
1036	–	compiler_flush_jsr_stack ();
1037	–
1071		if ((opcode & 0xFF00) == 0x7100) {
1072		struct M68kRegisters r;
1073		int i;
#	Line 1043 \| Line 1076 \| unsigned long REGPARAM2 op_illg (uae_u32
1076		if (opcode == M68K_EXEC_RETURN) {
1077		regs.spcflags \|= SPCFLAG_BRK;
1078		quit_program = 1;
1079	<	return 4;
1079	>	return;
1080		}
1081
1082		// Call EMUL_OP opcode
#	Line 1062 \| Line 1095 \| unsigned long REGPARAM2 op_illg (uae_u32
1095		MakeFromSR();
1096		m68k_incpc(2);
1097		fill_prefetch_0 ();
1098	<	return 4;
1098	>	return;
1099		}
1100
1101		if ((opcode & 0xF000) == 0xA000) {
1102		Exception(0xA,0);
1103	<	return 4;
1103	>	return;
1104		}
1105
1106	+	// write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc);
1107	+
1108		if ((opcode & 0xF000) == 0xF000) {
1109		Exception(0xB,0);
1110	<	return 4;
1110	>	return;
1111		}
1112
1113		write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc);
1114	+
1115		Exception (4,0);
1080	–	return 4;
1116		}
1117
1118		void mmu_op(uae_u32 opcode, uae_u16 extra)
#	Line 1133 \| Line 1168 \| static void do_trace (void)
1168		static int do_specialties (void)
1169		{
1170		/n_spcinsns++;/
1136	–	run_compiled_code();
1171		if (regs.spcflags & SPCFLAG_DOTRACE) {
1172		Exception (9,last_trace_ad);
1173		}
#	Line 1172 \| Line 1206 \| static int do_specialties (void)
1206
1207		static void m68k_run_1 (void)
1208		{
1209	<	for (;;) {
1210	<	int cycles;
1211	<	uae_u32 opcode = GET_OPCODE;
1212	<	#if 0
1213	<	if (get_ilong (0) != do_get_mem_long (&regs.prefetch)) {
1214	<	debugging = 1;
1215	<	return;
1182	<	}
1183	<	#endif
1184	<	/* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1185	<	/* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1186	<	#if COUNT_INSTRS == 2
1187	<	if (table68k[cft_map (opcode)].handler != -1)
1188	<	instrcount[table68k[cft_map (opcode)].handler]++;
1189	<	#elif COUNT_INSTRS == 1
1190	<	instrcount[opcode]++;
1191	<	#endif
1192	<	#if defined(X86_ASSEMBLYxxx)
1193	<	__asm__ __volatile__("\tcall *%%ebx"
1194	<	: "=&a" (cycles) : "b" (cpufunctbl[opcode]), "0" (opcode)
1195	<	: "%edx", "%ecx",
1196	<	"%esi", "%edi", "%ebp", "memory", "cc");
1197	<	#else
1198	<	cycles = (*cpufunctbl[opcode])(opcode);
1199	<	#endif
1200	<	/n_insns++;/
1201	<	if (regs.spcflags) {
1202	<	if (do_specialties ())
1203	<	return;
1209	>	for (;;) {
1210	>	uae_u32 opcode = GET_OPCODE;
1211	>	(*cpufunctbl[opcode])(opcode);
1212	>	if (regs.spcflags) {
1213	>	if (do_specialties())
1214	>	return;
1215	>	}
1216		}
1205	–	}
1217		}
1218
1208	–	#ifdef X86_ASSEMBLYxxx
1209	–	static __inline__ void m68k_run1 (void)
1210	–	{
1211	–	/* Work around compiler bug: GCC doesn't push %ebp in m68k_run_1. */
1212	–	__asm__ __volatile__ ("pushl %%ebp\n\tcall *%0\n\tpopl %%ebp" : : "r" (m68k_run_1) : "%eax", "%edx", "%ecx", "memory", "cc");
1213	–	}
1214	–	#else
1219		#define m68k_run1 m68k_run_1
1216	–	#endif
1220
1221		int in_m68k_go = 0;
1222

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Comparing BasiliskII/src/uae_cpu/newcpu.cpp (file contents): Revision 1.1 by cebix, 1999-10-03T14:16:26Z vs. Revision 1.8 by gbeauche, 2001-03-20T17:35:46Z

Diff Legend

Comparing BasiliskII/src/uae_cpu/newcpu.cpp (file contents):
Revision 1.1 by cebix, 1999-10-03T14:16:26Z vs.
Revision 1.8 by gbeauche, 2001-03-20T17:35:46Z