111 |
|
#endif |
112 |
|
} |
113 |
|
|
114 |
< |
static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM; |
114 |
> |
static void REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM; |
115 |
|
|
116 |
< |
static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode) |
116 |
> |
static void REGPARAM2 op_illg_1 (uae_u32 opcode) |
117 |
|
{ |
118 |
|
op_illg (cft_map (opcode)); |
119 |
– |
return 4; |
119 |
|
} |
120 |
|
|
121 |
|
static void build_cpufunctbl (void) |
122 |
|
{ |
123 |
|
int i; |
124 |
|
unsigned long opcode; |
125 |
< |
int cpu_level = (FPUType ? 3 : CPUType >= 2 ? 2 : CPUType == 1 ? 1 : 0); |
126 |
< |
struct cputbl *tbl = (cpu_level == 3 ? op_smalltbl_0 |
127 |
< |
: cpu_level == 2 ? op_smalltbl_1 |
128 |
< |
: cpu_level == 1 ? op_smalltbl_2 |
129 |
< |
: op_smalltbl_3); |
125 |
> |
int cpu_level = 0; // 68000 (default) |
126 |
> |
if (CPUType == 4) |
127 |
> |
cpu_level = 4; // 68040 with FPU |
128 |
> |
else { |
129 |
> |
if (FPUType) |
130 |
> |
cpu_level = 3; // 68020 with FPU |
131 |
> |
else if (CPUType >= 2) |
132 |
> |
cpu_level = 2; // 68020 |
133 |
> |
else if (CPUType == 1) |
134 |
> |
cpu_level = 1; |
135 |
> |
} |
136 |
> |
struct cputbl *tbl = ( |
137 |
> |
cpu_level == 4 ? op_smalltbl_0 |
138 |
> |
: cpu_level == 3 ? op_smalltbl_1 |
139 |
> |
: cpu_level == 2 ? op_smalltbl_2 |
140 |
> |
: cpu_level == 1 ? op_smalltbl_3 |
141 |
> |
: op_smalltbl_4); |
142 |
|
|
143 |
|
for (opcode = 0; opcode < 65536; opcode++) |
144 |
|
cpufunctbl[cft_map (opcode)] = op_illg_1; |
183 |
|
for (j = 7 ; j >= 0 ; j--) { |
184 |
|
if (i & (1 << j)) break; |
185 |
|
} |
186 |
< |
fpp_movem_index1[i] = j; |
187 |
< |
fpp_movem_index2[i] = 7-j; |
186 |
> |
fpp_movem_index1[i] = 7-j; |
187 |
> |
fpp_movem_index2[i] = j; |
188 |
|
fpp_movem_next[i] = i & (~(1 << j)); |
189 |
|
} |
190 |
|
#if COUNT_INSTRS |
207 |
|
do_merges (); |
208 |
|
|
209 |
|
build_cpufunctbl (); |
210 |
+ |
|
211 |
+ |
fpu_init (); |
212 |
+ |
fpu_set_integral_fpu (CPUType == 4); |
213 |
+ |
} |
214 |
+ |
|
215 |
+ |
void exit_m68k (void) |
216 |
+ |
{ |
217 |
+ |
fpu_exit (); |
218 |
|
} |
219 |
|
|
220 |
|
struct regstruct regs, lastint_regs; |
223 |
|
static long int m68kpc_offset; |
224 |
|
int lastint_no; |
225 |
|
|
226 |
+ |
#if REAL_ADDRESSING || DIRECT_ADDRESSING |
227 |
+ |
#define get_ibyte_1(o) get_byte(get_virtual_address(regs.pc_p) + (o) + 1) |
228 |
+ |
#define get_iword_1(o) get_word(get_virtual_address(regs.pc_p) + (o)) |
229 |
+ |
#define get_ilong_1(o) get_long(get_virtual_address(regs.pc_p) + (o)) |
230 |
+ |
#else |
231 |
|
#define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1) |
232 |
|
#define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o)) |
233 |
|
#define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o)) |
234 |
+ |
#endif |
235 |
|
|
236 |
|
uae_s32 ShowEA (int reg, amodes mode, wordsizes size, char *buf) |
237 |
|
{ |
264 |
|
disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; |
265 |
|
addr = m68k_areg(regs,reg) + (uae_s16)disp16; |
266 |
|
sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff, |
267 |
< |
(long unsigned int)addr); |
267 |
> |
(unsigned long)addr); |
268 |
|
break; |
269 |
|
case Ad8r: |
270 |
|
dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; |
297 |
|
dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', |
298 |
|
1 << ((dp >> 9) & 3), |
299 |
|
disp,outer, |
300 |
< |
(long unsigned int)addr); |
300 |
> |
(unsigned long)addr); |
301 |
|
} else { |
302 |
|
addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg; |
303 |
|
sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg, |
304 |
|
dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', |
305 |
|
1 << ((dp >> 9) & 3), disp8, |
306 |
< |
(long unsigned int)addr); |
306 |
> |
(unsigned long)addr); |
307 |
|
} |
308 |
|
break; |
309 |
|
case PC16: |
310 |
|
addr = m68k_getpc () + m68kpc_offset; |
311 |
|
disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; |
312 |
|
addr += (uae_s16)disp16; |
313 |
< |
sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(long unsigned int)addr); |
313 |
> |
sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr); |
314 |
|
break; |
315 |
|
case PC8r: |
316 |
|
addr = m68k_getpc () + m68kpc_offset; |
344 |
|
dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', |
345 |
|
1 << ((dp >> 9) & 3), |
346 |
|
disp,outer, |
347 |
< |
(long unsigned int)addr); |
347 |
> |
(unsigned long)addr); |
348 |
|
} else { |
349 |
|
addr += (uae_s32)((uae_s8)disp8) + dispreg; |
350 |
|
sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D', |
351 |
|
(int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3), |
352 |
< |
disp8, (long unsigned int)addr); |
352 |
> |
disp8, (unsigned long)addr); |
353 |
|
} |
354 |
|
break; |
355 |
|
case absw: |
356 |
< |
sprintf (buffer,"$%08lx", (long unsigned int)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset)); |
356 |
> |
sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset)); |
357 |
|
m68kpc_offset += 2; |
358 |
|
break; |
359 |
|
case absl: |
360 |
< |
sprintf (buffer,"$%08lx", (long unsigned int)get_ilong_1 (m68kpc_offset)); |
360 |
> |
sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset)); |
361 |
|
m68kpc_offset += 4; |
362 |
|
break; |
363 |
|
case imm: |
371 |
|
m68kpc_offset += 2; |
372 |
|
break; |
373 |
|
case sz_long: |
374 |
< |
sprintf (buffer,"#$%08lx", (long unsigned int)(get_ilong_1 (m68kpc_offset))); |
374 |
> |
sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset))); |
375 |
|
m68kpc_offset += 4; |
376 |
|
break; |
377 |
|
default: |
391 |
|
case imm2: |
392 |
|
offset = (uae_s32)get_ilong_1 (m68kpc_offset); |
393 |
|
m68kpc_offset += 4; |
394 |
< |
sprintf (buffer,"#$%08lx", (long unsigned int)offset); |
394 |
> |
sprintf (buffer,"#$%08lx", (unsigned long)offset); |
395 |
|
break; |
396 |
|
case immi: |
397 |
|
offset = (uae_s32)(uae_s8)(reg & 0xff); |
398 |
< |
sprintf (buffer,"#$%08lx", (long unsigned int)offset); |
398 |
> |
sprintf (buffer,"#$%08lx", (unsigned long)offset); |
399 |
|
break; |
400 |
|
default: |
401 |
|
break; |
735 |
|
regs.spcflags |= SPCFLAG_INT; |
736 |
|
} |
737 |
|
|
738 |
< |
static int caar, cacr; |
738 |
> |
static int caar, cacr, tc, itt0, itt1, dtt0, dtt1; |
739 |
|
|
740 |
|
void m68k_move2c (int regno, uae_u32 *regp) |
741 |
|
{ |
746 |
|
case 0: regs.sfc = *regp & 7; break; |
747 |
|
case 1: regs.dfc = *regp & 7; break; |
748 |
|
case 2: cacr = *regp & 0x3; break; /* ignore C and CE */ |
749 |
+ |
case 3: tc = *regp & 0xc000; break; |
750 |
+ |
case 4: itt0 = *regp & 0xffffe364; break; |
751 |
+ |
case 5: itt1 = *regp & 0xffffe364; break; |
752 |
+ |
case 6: dtt0 = *regp & 0xffffe364; break; |
753 |
+ |
case 7: dtt1 = *regp & 0xffffe364; break; |
754 |
|
case 0x800: regs.usp = *regp; break; |
755 |
|
case 0x801: regs.vbr = *regp; break; |
756 |
|
case 0x802: caar = *regp &0xfc; break; |
771 |
|
case 0: *regp = regs.sfc; break; |
772 |
|
case 1: *regp = regs.dfc; break; |
773 |
|
case 2: *regp = cacr; break; |
774 |
+ |
case 3: *regp = tc; break; |
775 |
+ |
case 4: *regp = itt0; break; |
776 |
+ |
case 5: *regp = itt1; break; |
777 |
+ |
case 6: *regp = dtt0; break; |
778 |
+ |
case 7: *regp = dtt1; break; |
779 |
|
case 0x800: *regp = regs.usp; break; |
780 |
|
case 0x801: *regp = regs.vbr; break; |
781 |
|
case 0x802: *regp = caar; break; |
1061 |
|
regs.spcflags = 0; |
1062 |
|
regs.intmask = 7; |
1063 |
|
regs.vbr = regs.sfc = regs.dfc = 0; |
1064 |
< |
regs.fpcr = regs.fpsr = regs.fpiar = 0; |
1064 |
> |
/* gb-- moved into {fpp,fpu_x86}.cpp::fpu_init() |
1065 |
> |
regs.fpcr = regs.fpsr = regs.fpiar = 0; */ |
1066 |
> |
fpu_reset(); |
1067 |
|
} |
1068 |
|
|
1069 |
< |
unsigned long REGPARAM2 op_illg (uae_u32 opcode) |
1069 |
> |
void REGPARAM2 op_illg (uae_u32 opcode) |
1070 |
|
{ |
1071 |
|
uaecptr pc = m68k_getpc (); |
1072 |
|
|
1080 |
|
if (opcode == M68K_EXEC_RETURN) { |
1081 |
|
regs.spcflags |= SPCFLAG_BRK; |
1082 |
|
quit_program = 1; |
1083 |
< |
return 4; |
1083 |
> |
return; |
1084 |
|
} |
1085 |
|
|
1086 |
|
// Call EMUL_OP opcode |
1099 |
|
MakeFromSR(); |
1100 |
|
m68k_incpc(2); |
1101 |
|
fill_prefetch_0 (); |
1102 |
< |
return 4; |
1102 |
> |
return; |
1103 |
|
} |
1104 |
|
|
1105 |
|
if ((opcode & 0xF000) == 0xA000) { |
1106 |
|
Exception(0xA,0); |
1107 |
< |
return 4; |
1107 |
> |
return; |
1108 |
|
} |
1109 |
|
|
1110 |
+ |
// write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc); |
1111 |
+ |
|
1112 |
|
if ((opcode & 0xF000) == 0xF000) { |
1113 |
|
Exception(0xB,0); |
1114 |
< |
return 4; |
1114 |
> |
return; |
1115 |
|
} |
1116 |
|
|
1117 |
|
write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc); |
1118 |
+ |
|
1119 |
|
Exception (4,0); |
1080 |
– |
return 4; |
1120 |
|
} |
1121 |
|
|
1122 |
|
void mmu_op(uae_u32 opcode, uae_u16 extra) |
1211 |
|
|
1212 |
|
static void m68k_run_1 (void) |
1213 |
|
{ |
1214 |
< |
for (;;) { |
1215 |
< |
int cycles; |
1216 |
< |
uae_u32 opcode = GET_OPCODE; |
1217 |
< |
#if 0 |
1218 |
< |
if (get_ilong (0) != do_get_mem_long (®s.prefetch)) { |
1219 |
< |
debugging = 1; |
1220 |
< |
return; |
1182 |
< |
} |
1183 |
< |
#endif |
1184 |
< |
/* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */ |
1185 |
< |
/* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/ |
1186 |
< |
#if COUNT_INSTRS == 2 |
1187 |
< |
if (table68k[cft_map (opcode)].handler != -1) |
1188 |
< |
instrcount[table68k[cft_map (opcode)].handler]++; |
1189 |
< |
#elif COUNT_INSTRS == 1 |
1190 |
< |
instrcount[opcode]++; |
1191 |
< |
#endif |
1192 |
< |
#if defined(X86_ASSEMBLYxxx) |
1193 |
< |
__asm__ __volatile__("\tcall *%%ebx" |
1194 |
< |
: "=&a" (cycles) : "b" (cpufunctbl[opcode]), "0" (opcode) |
1195 |
< |
: "%edx", "%ecx", |
1196 |
< |
"%esi", "%edi", "%ebp", "memory", "cc"); |
1197 |
< |
#else |
1198 |
< |
cycles = (*cpufunctbl[opcode])(opcode); |
1199 |
< |
#endif |
1200 |
< |
/*n_insns++;*/ |
1201 |
< |
if (regs.spcflags) { |
1202 |
< |
if (do_specialties ()) |
1203 |
< |
return; |
1214 |
> |
for (;;) { |
1215 |
> |
uae_u32 opcode = GET_OPCODE; |
1216 |
> |
(*cpufunctbl[opcode])(opcode); |
1217 |
> |
if (regs.spcflags) { |
1218 |
> |
if (do_specialties()) |
1219 |
> |
return; |
1220 |
> |
} |
1221 |
|
} |
1205 |
– |
} |
1222 |
|
} |
1223 |
|
|
1208 |
– |
#ifdef X86_ASSEMBLYxxx |
1209 |
– |
static __inline__ void m68k_run1 (void) |
1210 |
– |
{ |
1211 |
– |
/* Work around compiler bug: GCC doesn't push %ebp in m68k_run_1. */ |
1212 |
– |
__asm__ __volatile__ ("pushl %%ebp\n\tcall *%0\n\tpopl %%ebp" : : "r" (m68k_run_1) : "%eax", "%edx", "%ecx", "memory", "cc"); |
1213 |
– |
} |
1214 |
– |
#else |
1224 |
|
#define m68k_run1 m68k_run_1 |
1216 |
– |
#endif |
1225 |
|
|
1226 |
|
int in_m68k_go = 0; |
1227 |
|
|