22 |
|
#include "memory.h" |
23 |
|
#include "readcpu.h" |
24 |
|
#include "newcpu.h" |
25 |
< |
#include "compiler.h" |
25 |
> |
|
26 |
> |
#if defined(ENABLE_EXCLUSIVE_SPCFLAGS) && !defined(HAVE_HARDWARE_LOCKS) |
27 |
> |
B2_mutex *spcflags_lock = NULL; |
28 |
> |
#endif |
29 |
> |
|
30 |
> |
#if ENABLE_MON |
31 |
> |
#include "mon.h" |
32 |
> |
#include "mon_disass.h" |
33 |
> |
#endif |
34 |
|
|
35 |
|
int quit_program = 0; |
36 |
< |
int debugging = 0; |
36 |
> |
const int debugging = 0; |
37 |
|
struct flag_struct regflags; |
38 |
|
|
39 |
|
/* Opcode of faulting instruction */ |
56 |
|
|
57 |
|
cpuop_func *cpufunctbl[65536]; |
58 |
|
|
59 |
+ |
#define FLIGHT_RECORDER 0 |
60 |
+ |
|
61 |
+ |
#if FLIGHT_RECORDER |
62 |
+ |
struct rec_step { |
63 |
+ |
uae_u32 d[8]; |
64 |
+ |
uae_u32 a[8]; |
65 |
+ |
uae_u32 pc; |
66 |
+ |
}; |
67 |
+ |
|
68 |
+ |
const int LOG_SIZE = 8192; |
69 |
+ |
static rec_step log[LOG_SIZE]; |
70 |
+ |
static int log_ptr = -1; // First time initialization |
71 |
+ |
|
72 |
+ |
static const char *log_filename(void) |
73 |
+ |
{ |
74 |
+ |
const char *name = getenv("M68K_LOG_FILE"); |
75 |
+ |
return name ? name : "log.68k"; |
76 |
+ |
} |
77 |
+ |
|
78 |
+ |
static void record_step(uaecptr pc) |
79 |
+ |
{ |
80 |
+ |
for (int i = 0; i < 8; i++) { |
81 |
+ |
log[log_ptr].d[i] = m68k_dreg(regs, i); |
82 |
+ |
log[log_ptr].a[i] = m68k_areg(regs, i); |
83 |
+ |
} |
84 |
+ |
log[log_ptr].pc = pc; |
85 |
+ |
log_ptr = (log_ptr + 1) % LOG_SIZE; |
86 |
+ |
} |
87 |
+ |
|
88 |
+ |
static void dump_log(void) |
89 |
+ |
{ |
90 |
+ |
FILE *f = fopen(log_filename(), "w"); |
91 |
+ |
if (f == NULL) |
92 |
+ |
return; |
93 |
+ |
for (int i = 0; i < LOG_SIZE; i++) { |
94 |
+ |
int j = (i + log_ptr) % LOG_SIZE; |
95 |
+ |
fprintf(f, "pc %08x\n", log[j].pc); |
96 |
+ |
fprintf(f, "d0 %08x d1 %08x d2 %08x d3 %08x\n", log[j].d[0], log[j].d[1], log[j].d[2], log[j].d[3]); |
97 |
+ |
fprintf(f, "d4 %08x d5 %08x d6 %08x d7 %08x\n", log[j].d[4], log[j].d[5], log[j].d[6], log[j].d[7]); |
98 |
+ |
fprintf(f, "a0 %08x a1 %08x a2 %08x a3 %08x\n", log[j].a[0], log[j].a[1], log[j].a[2], log[j].a[3]); |
99 |
+ |
fprintf(f, "a4 %08x a5 %08x a6 %08x a7 %08x\n", log[j].a[4], log[j].a[5], log[j].a[6], log[j].a[7]); |
100 |
+ |
#if ENABLE_MON |
101 |
+ |
disass_68k(f, log[j].pc); |
102 |
+ |
#endif |
103 |
+ |
} |
104 |
+ |
fclose(f); |
105 |
+ |
} |
106 |
+ |
#endif |
107 |
+ |
|
108 |
|
#define COUNT_INSTRS 0 |
109 |
|
|
110 |
|
#if COUNT_INSTRS |
168 |
|
#endif |
169 |
|
} |
170 |
|
|
171 |
< |
static void REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM; |
171 |
> |
cpuop_rettype REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM; |
172 |
|
|
173 |
< |
static void REGPARAM2 op_illg_1 (uae_u32 opcode) |
173 |
> |
cpuop_rettype REGPARAM2 op_illg_1 (uae_u32 opcode) |
174 |
|
{ |
175 |
< |
op_illg (cft_map (opcode)); |
175 |
> |
cpuop_return( op_illg (cft_map (opcode)) ); |
176 |
|
} |
177 |
|
|
178 |
|
static void build_cpufunctbl (void) |
191 |
|
cpu_level = 1; |
192 |
|
} |
193 |
|
struct cputbl *tbl = ( |
194 |
< |
cpu_level == 4 ? op_smalltbl_0 |
195 |
< |
: cpu_level == 3 ? op_smalltbl_1 |
196 |
< |
: cpu_level == 2 ? op_smalltbl_2 |
197 |
< |
: cpu_level == 1 ? op_smalltbl_3 |
198 |
< |
: op_smalltbl_4); |
194 |
> |
cpu_level == 4 ? op_smalltbl_0_ff |
195 |
> |
: cpu_level == 3 ? op_smalltbl_1_ff |
196 |
> |
: cpu_level == 2 ? op_smalltbl_2_ff |
197 |
> |
: cpu_level == 1 ? op_smalltbl_3_ff |
198 |
> |
: op_smalltbl_4_ff); |
199 |
|
|
200 |
|
for (opcode = 0; opcode < 65536; opcode++) |
201 |
|
cpufunctbl[cft_map (opcode)] = op_illg_1; |
240 |
|
for (j = 7 ; j >= 0 ; j--) { |
241 |
|
if (i & (1 << j)) break; |
242 |
|
} |
243 |
< |
fpp_movem_index1[i] = j; |
244 |
< |
fpp_movem_index2[i] = 7-j; |
243 |
> |
fpp_movem_index1[i] = 7-j; |
244 |
> |
fpp_movem_index2[i] = j; |
245 |
|
fpp_movem_next[i] = i & (~(1 << j)); |
246 |
|
} |
247 |
|
#if COUNT_INSTRS |
264 |
|
do_merges (); |
265 |
|
|
266 |
|
build_cpufunctbl (); |
267 |
+ |
|
268 |
+ |
#if defined(ENABLE_EXCLUSIVE_SPCFLAGS) && !defined(HAVE_HARDWARE_LOCKS) |
269 |
+ |
spcflags_lock = B2_create_mutex(); |
270 |
+ |
#endif |
271 |
+ |
|
272 |
+ |
fpu_init (); |
273 |
+ |
fpu_set_integral_fpu (CPUType == 4); |
274 |
+ |
} |
275 |
+ |
|
276 |
+ |
void exit_m68k (void) |
277 |
+ |
{ |
278 |
+ |
fpu_exit (); |
279 |
+ |
#if defined(ENABLE_EXCLUSIVE_SPCFLAGS) && !defined(HAVE_HARDWARE_LOCKS) |
280 |
+ |
B2_delete_mutex(spcflags_lock); |
281 |
+ |
#endif |
282 |
|
} |
283 |
|
|
284 |
|
struct regstruct regs, lastint_regs; |
287 |
|
static long int m68kpc_offset; |
288 |
|
int lastint_no; |
289 |
|
|
290 |
+ |
#if REAL_ADDRESSING || DIRECT_ADDRESSING |
291 |
+ |
#define get_ibyte_1(o) get_byte(get_virtual_address(regs.pc_p) + (o) + 1) |
292 |
+ |
#define get_iword_1(o) get_word(get_virtual_address(regs.pc_p) + (o)) |
293 |
+ |
#define get_ilong_1(o) get_long(get_virtual_address(regs.pc_p) + (o)) |
294 |
+ |
#else |
295 |
|
#define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1) |
296 |
|
#define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o)) |
297 |
|
#define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o)) |
298 |
+ |
#endif |
299 |
|
|
300 |
|
uae_s32 ShowEA (int reg, amodes mode, wordsizes size, char *buf) |
301 |
|
{ |
328 |
|
disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; |
329 |
|
addr = m68k_areg(regs,reg) + (uae_s16)disp16; |
330 |
|
sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff, |
331 |
< |
(long unsigned int)addr); |
331 |
> |
(unsigned long)addr); |
332 |
|
break; |
333 |
|
case Ad8r: |
334 |
|
dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; |
361 |
|
dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', |
362 |
|
1 << ((dp >> 9) & 3), |
363 |
|
disp,outer, |
364 |
< |
(long unsigned int)addr); |
364 |
> |
(unsigned long)addr); |
365 |
|
} else { |
366 |
|
addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg; |
367 |
|
sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg, |
368 |
|
dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', |
369 |
|
1 << ((dp >> 9) & 3), disp8, |
370 |
< |
(long unsigned int)addr); |
370 |
> |
(unsigned long)addr); |
371 |
|
} |
372 |
|
break; |
373 |
|
case PC16: |
374 |
|
addr = m68k_getpc () + m68kpc_offset; |
375 |
|
disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; |
376 |
|
addr += (uae_s16)disp16; |
377 |
< |
sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(long unsigned int)addr); |
377 |
> |
sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr); |
378 |
|
break; |
379 |
|
case PC8r: |
380 |
|
addr = m68k_getpc () + m68kpc_offset; |
408 |
|
dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', |
409 |
|
1 << ((dp >> 9) & 3), |
410 |
|
disp,outer, |
411 |
< |
(long unsigned int)addr); |
411 |
> |
(unsigned long)addr); |
412 |
|
} else { |
413 |
|
addr += (uae_s32)((uae_s8)disp8) + dispreg; |
414 |
|
sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D', |
415 |
|
(int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3), |
416 |
< |
disp8, (long unsigned int)addr); |
416 |
> |
disp8, (unsigned long)addr); |
417 |
|
} |
418 |
|
break; |
419 |
|
case absw: |
420 |
< |
sprintf (buffer,"$%08lx", (long unsigned int)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset)); |
420 |
> |
sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset)); |
421 |
|
m68kpc_offset += 2; |
422 |
|
break; |
423 |
|
case absl: |
424 |
< |
sprintf (buffer,"$%08lx", (long unsigned int)get_ilong_1 (m68kpc_offset)); |
424 |
> |
sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset)); |
425 |
|
m68kpc_offset += 4; |
426 |
|
break; |
427 |
|
case imm: |
435 |
|
m68kpc_offset += 2; |
436 |
|
break; |
437 |
|
case sz_long: |
438 |
< |
sprintf (buffer,"#$%08lx", (long unsigned int)(get_ilong_1 (m68kpc_offset))); |
438 |
> |
sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset))); |
439 |
|
m68kpc_offset += 4; |
440 |
|
break; |
441 |
|
default: |
455 |
|
case imm2: |
456 |
|
offset = (uae_s32)get_ilong_1 (m68kpc_offset); |
457 |
|
m68kpc_offset += 4; |
458 |
< |
sprintf (buffer,"#$%08lx", (long unsigned int)offset); |
458 |
> |
sprintf (buffer,"#$%08lx", (unsigned long)offset); |
459 |
|
break; |
460 |
|
case immi: |
461 |
|
offset = (uae_s32)(uae_s8)(reg & 0xff); |
462 |
< |
sprintf (buffer,"#$%08lx", (long unsigned int)offset); |
462 |
> |
sprintf (buffer,"#$%08lx", (unsigned long)offset); |
463 |
|
break; |
464 |
|
default: |
465 |
|
break; |
714 |
|
} |
715 |
|
} |
716 |
|
|
717 |
< |
regs.spcflags |= SPCFLAG_INT; |
717 |
> |
SPCFLAGS_SET( SPCFLAG_INT ); |
718 |
|
if (regs.t1 || regs.t0) |
719 |
< |
regs.spcflags |= SPCFLAG_TRACE; |
719 |
> |
SPCFLAGS_SET( SPCFLAG_TRACE ); |
720 |
|
else |
721 |
< |
regs.spcflags &= ~(SPCFLAG_TRACE | SPCFLAG_DOTRACE); |
721 |
> |
/* Keep SPCFLAG_DOTRACE, we still want a trace exception for |
722 |
> |
SR-modifying instructions (including STOP). */ |
723 |
> |
SPCFLAGS_CLEAR( SPCFLAG_TRACE ); |
724 |
|
} |
725 |
|
|
726 |
|
void Exception(int nr, uaecptr oldpc) |
727 |
|
{ |
728 |
< |
compiler_flush_jsr_stack(); |
728 |
> |
uae_u32 currpc = m68k_getpc (); |
729 |
|
MakeSR(); |
730 |
|
if (!regs.s) { |
731 |
|
regs.usp = m68k_areg(regs, 7); |
754 |
|
m68k_areg(regs, 7) -= 2; |
755 |
|
put_word (m68k_areg(regs, 7), nr * 4); |
756 |
|
m68k_areg(regs, 7) -= 4; |
757 |
< |
put_long (m68k_areg(regs, 7), m68k_getpc ()); |
757 |
> |
put_long (m68k_areg(regs, 7), currpc); |
758 |
|
m68k_areg(regs, 7) -= 2; |
759 |
|
put_word (m68k_areg(regs, 7), regs.sr); |
760 |
|
regs.sr |= (1 << 13); |
780 |
|
} |
781 |
|
} |
782 |
|
m68k_areg(regs, 7) -= 4; |
783 |
< |
put_long (m68k_areg(regs, 7), m68k_getpc ()); |
783 |
> |
put_long (m68k_areg(regs, 7), currpc); |
784 |
|
kludge_me_do: |
785 |
|
m68k_areg(regs, 7) -= 2; |
786 |
|
put_word (m68k_areg(regs, 7), regs.sr); |
787 |
|
m68k_setpc (get_long (regs.vbr + 4*nr)); |
788 |
+ |
SPCFLAGS_SET( SPCFLAG_JIT_END_COMPILE ); |
789 |
|
fill_prefetch_0 (); |
790 |
|
regs.t1 = regs.t0 = regs.m = 0; |
791 |
< |
regs.spcflags &= ~(SPCFLAG_TRACE | SPCFLAG_DOTRACE); |
791 |
> |
SPCFLAGS_CLEAR( SPCFLAG_TRACE | SPCFLAG_DOTRACE ); |
792 |
|
} |
793 |
|
|
794 |
|
static void Interrupt(int nr) |
799 |
|
Exception(nr+24, 0); |
800 |
|
|
801 |
|
regs.intmask = nr; |
802 |
< |
regs.spcflags |= SPCFLAG_INT; |
802 |
> |
SPCFLAGS_SET( SPCFLAG_INT ); |
803 |
|
} |
804 |
|
|
805 |
< |
static int caar, cacr, tc, itt0, itt1, dtt0, dtt1; |
805 |
> |
static int caar, cacr, tc, itt0, itt1, dtt0, dtt1, mmusr, urp, srp; |
806 |
|
|
807 |
< |
void m68k_move2c (int regno, uae_u32 *regp) |
807 |
> |
int m68k_move2c (int regno, uae_u32 *regp) |
808 |
|
{ |
809 |
< |
if (CPUType == 1 && (regno & 0x7FF) > 1) |
809 |
> |
if ((CPUType == 1 && (regno & 0x7FF) > 1) |
810 |
> |
|| (CPUType < 4 && (regno & 0x7FF) > 2) |
811 |
> |
|| (CPUType == 4 && regno == 0x802)) |
812 |
> |
{ |
813 |
|
op_illg (0x4E7B); |
814 |
< |
else |
814 |
> |
return 0; |
815 |
> |
} else { |
816 |
|
switch (regno) { |
817 |
|
case 0: regs.sfc = *regp & 7; break; |
818 |
|
case 1: regs.dfc = *regp & 7; break; |
819 |
< |
case 2: cacr = *regp & 0x3; break; /* ignore C and CE */ |
819 |
> |
case 2: cacr = *regp & (CPUType < 4 ? 0x3 : 0x80008000); break; |
820 |
|
case 3: tc = *regp & 0xc000; break; |
821 |
|
case 4: itt0 = *regp & 0xffffe364; break; |
822 |
|
case 5: itt1 = *regp & 0xffffe364; break; |
827 |
|
case 0x802: caar = *regp &0xfc; break; |
828 |
|
case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break; |
829 |
|
case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break; |
830 |
+ |
case 0x805: mmusr = *regp; break; |
831 |
+ |
case 0x806: urp = *regp; break; |
832 |
+ |
case 0x807: srp = *regp; break; |
833 |
|
default: |
834 |
|
op_illg (0x4E7B); |
835 |
< |
break; |
835 |
> |
return 0; |
836 |
|
} |
837 |
+ |
} |
838 |
+ |
return 1; |
839 |
|
} |
840 |
|
|
841 |
< |
void m68k_movec2 (int regno, uae_u32 *regp) |
841 |
> |
int m68k_movec2 (int regno, uae_u32 *regp) |
842 |
|
{ |
843 |
< |
if (CPUType == 1 && (regno & 0x7FF) > 1) |
843 |
> |
if ((CPUType == 1 && (regno & 0x7FF) > 1) |
844 |
> |
|| (CPUType < 4 && (regno & 0x7FF) > 2) |
845 |
> |
|| (CPUType == 4 && regno == 0x802)) |
846 |
> |
{ |
847 |
|
op_illg (0x4E7A); |
848 |
< |
else |
848 |
> |
return 0; |
849 |
> |
} else { |
850 |
|
switch (regno) { |
851 |
|
case 0: *regp = regs.sfc; break; |
852 |
|
case 1: *regp = regs.dfc; break; |
861 |
|
case 0x802: *regp = caar; break; |
862 |
|
case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break; |
863 |
|
case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break; |
864 |
+ |
case 0x805: *regp = mmusr; break; |
865 |
+ |
case 0x806: *regp = urp; break; |
866 |
+ |
case 0x807: *regp = srp; break; |
867 |
|
default: |
868 |
|
op_illg (0x4E7A); |
869 |
< |
break; |
869 |
> |
return 0; |
870 |
> |
} |
871 |
|
} |
872 |
+ |
return 1; |
873 |
|
} |
874 |
|
|
875 |
|
static __inline__ int |
1127 |
|
{ "T ","F ","HI","LS","CC","CS","NE","EQ", |
1128 |
|
"VC","VS","PL","MI","GE","LT","GT","LE" }; |
1129 |
|
|
1130 |
+ |
// If value is greater than zero, this means we are still processing an EmulOp |
1131 |
+ |
// because the counter is incremented only in m68k_execute(), i.e. interpretive |
1132 |
+ |
// execution only |
1133 |
+ |
static int m68k_execute_depth = 0; |
1134 |
+ |
|
1135 |
|
void m68k_reset (void) |
1136 |
|
{ |
1137 |
|
m68k_areg (regs, 7) = 0x2000; |
1138 |
|
m68k_setpc (ROMBaseMac + 0x2a); |
1139 |
|
fill_prefetch_0 (); |
1036 |
– |
regs.kick_mask = 0xF80000; |
1140 |
|
regs.s = 1; |
1141 |
|
regs.m = 0; |
1142 |
|
regs.stopped = 0; |
1147 |
|
SET_CFLG (0); |
1148 |
|
SET_VFLG (0); |
1149 |
|
SET_NFLG (0); |
1150 |
< |
regs.spcflags = 0; |
1150 |
> |
SPCFLAGS_INIT( 0 ); |
1151 |
|
regs.intmask = 7; |
1152 |
|
regs.vbr = regs.sfc = regs.dfc = 0; |
1153 |
< |
regs.fpcr = regs.fpsr = regs.fpiar = 0; |
1153 |
> |
fpu_reset(); |
1154 |
> |
|
1155 |
> |
#if FLIGHT_RECORDER |
1156 |
> |
#if ENABLE_MON |
1157 |
> |
if (log_ptr == -1) { |
1158 |
> |
// Install "log" command in mon |
1159 |
> |
mon_add_command("log", dump_log, "log Dump m68k emulation log\n"); |
1160 |
> |
} |
1161 |
> |
#endif |
1162 |
> |
log_ptr = 0; |
1163 |
> |
memset(log, 0, sizeof(log)); |
1164 |
> |
#endif |
1165 |
|
} |
1166 |
|
|
1167 |
< |
void REGPARAM2 op_illg (uae_u32 opcode) |
1167 |
> |
void m68k_emulop_return(void) |
1168 |
|
{ |
1169 |
< |
uaecptr pc = m68k_getpc (); |
1170 |
< |
|
1171 |
< |
compiler_flush_jsr_stack (); |
1169 |
> |
SPCFLAGS_SET( SPCFLAG_BRK ); |
1170 |
> |
quit_program = 1; |
1171 |
> |
} |
1172 |
|
|
1173 |
< |
if ((opcode & 0xFF00) == 0x7100) { |
1173 |
> |
void m68k_emulop(uae_u32 opcode) |
1174 |
> |
{ |
1175 |
|
struct M68kRegisters r; |
1176 |
|
int i; |
1177 |
|
|
1063 |
– |
// Return from Execute68k()? |
1064 |
– |
if (opcode == M68K_EXEC_RETURN) { |
1065 |
– |
regs.spcflags |= SPCFLAG_BRK; |
1066 |
– |
quit_program = 1; |
1067 |
– |
return; |
1068 |
– |
} |
1069 |
– |
|
1070 |
– |
// Call EMUL_OP opcode |
1178 |
|
for (i=0; i<8; i++) { |
1179 |
|
r.d[i] = m68k_dreg(regs, i); |
1180 |
|
r.a[i] = m68k_areg(regs, i); |
1188 |
|
} |
1189 |
|
regs.sr = r.sr; |
1190 |
|
MakeFromSR(); |
1191 |
< |
m68k_incpc(2); |
1192 |
< |
fill_prefetch_0 (); |
1193 |
< |
return; |
1194 |
< |
} |
1191 |
> |
} |
1192 |
> |
|
1193 |
> |
cpuop_rettype REGPARAM2 op_illg (uae_u32 opcode) |
1194 |
> |
{ |
1195 |
> |
uaecptr pc = m68k_getpc (); |
1196 |
|
|
1197 |
|
if ((opcode & 0xF000) == 0xA000) { |
1198 |
|
Exception(0xA,0); |
1199 |
< |
return; |
1199 |
> |
cpuop_return(CFLOW_TRAP); |
1200 |
|
} |
1201 |
|
|
1094 |
– |
// write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc); |
1095 |
– |
|
1202 |
|
if ((opcode & 0xF000) == 0xF000) { |
1203 |
|
Exception(0xB,0); |
1204 |
< |
return; |
1204 |
> |
cpuop_return(CFLOW_TRAP); |
1205 |
|
} |
1206 |
|
|
1207 |
|
write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc); |
1208 |
|
|
1209 |
|
Exception (4,0); |
1210 |
+ |
cpuop_return(CFLOW_TRAP); |
1211 |
|
} |
1212 |
|
|
1213 |
|
void mmu_op(uae_u32 opcode, uae_u16 extra) |
1214 |
|
{ |
1215 |
< |
if ((extra & 0xB000) == 0) { /* PMOVE instruction */ |
1216 |
< |
|
1217 |
< |
} else if ((extra & 0xF000) == 0x2000) { /* PLOAD instruction */ |
1218 |
< |
} else if ((extra & 0xF000) == 0x8000) { /* PTEST instruction */ |
1215 |
> |
if ((opcode & 0xFE0) == 0x0500) { |
1216 |
> |
/* PFLUSH */ |
1217 |
> |
mmusr = 0; |
1218 |
> |
} else if ((opcode & 0x0FD8) == 0x548) { |
1219 |
> |
/* PTEST */ |
1220 |
|
} else |
1221 |
< |
op_illg (opcode); |
1221 |
> |
op_illg (opcode); |
1222 |
|
} |
1223 |
|
|
1224 |
|
static int n_insns = 0, n_spcinsns = 0; |
1227 |
|
|
1228 |
|
static void do_trace (void) |
1229 |
|
{ |
1230 |
< |
if (regs.t0) { |
1230 |
> |
if (regs.t0 && CPUType >= 2) { |
1231 |
|
uae_u16 opcode; |
1232 |
|
/* should also include TRAP, CHK, SR modification FPcc */ |
1233 |
|
/* probably never used so why bother */ |
1234 |
|
/* We can afford this to be inefficient... */ |
1235 |
|
m68k_setpc (m68k_getpc ()); |
1236 |
|
fill_prefetch_0 (); |
1237 |
< |
opcode = get_word (regs.pc); |
1237 |
> |
opcode = get_word(m68k_getpc()); |
1238 |
|
if (opcode == 0x4e72 /* RTE */ |
1239 |
|
|| opcode == 0x4e74 /* RTD */ |
1240 |
|
|| opcode == 0x4e75 /* RTS */ |
1250 |
|
&& (uae_s16)m68k_dreg(regs, opcode & 7) != 0)) |
1251 |
|
{ |
1252 |
|
last_trace_ad = m68k_getpc (); |
1253 |
< |
regs.spcflags &= ~SPCFLAG_TRACE; |
1254 |
< |
regs.spcflags |= SPCFLAG_DOTRACE; |
1253 |
> |
SPCFLAGS_CLEAR( SPCFLAG_TRACE ); |
1254 |
> |
SPCFLAGS_SET( SPCFLAG_DOTRACE ); |
1255 |
|
} |
1256 |
|
} else if (regs.t1) { |
1257 |
|
last_trace_ad = m68k_getpc (); |
1258 |
< |
regs.spcflags &= ~SPCFLAG_TRACE; |
1259 |
< |
regs.spcflags |= SPCFLAG_DOTRACE; |
1258 |
> |
SPCFLAGS_CLEAR( SPCFLAG_TRACE ); |
1259 |
> |
SPCFLAGS_SET( SPCFLAG_DOTRACE ); |
1260 |
|
} |
1261 |
|
} |
1262 |
|
|
1263 |
< |
|
1156 |
< |
static int do_specialties (void) |
1263 |
> |
int m68k_do_specialties (void) |
1264 |
|
{ |
1265 |
< |
/*n_spcinsns++;*/ |
1159 |
< |
run_compiled_code(); |
1160 |
< |
if (regs.spcflags & SPCFLAG_DOTRACE) { |
1265 |
> |
if (SPCFLAGS_TEST( SPCFLAG_DOTRACE )) { |
1266 |
|
Exception (9,last_trace_ad); |
1267 |
|
} |
1268 |
< |
while (regs.spcflags & SPCFLAG_STOP) { |
1269 |
< |
if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)){ |
1268 |
> |
while (SPCFLAGS_TEST( SPCFLAG_STOP )) { |
1269 |
> |
if (SPCFLAGS_TEST( SPCFLAG_INT | SPCFLAG_DOINT )){ |
1270 |
> |
SPCFLAGS_CLEAR( SPCFLAG_INT | SPCFLAG_DOINT ); |
1271 |
|
int intr = intlev (); |
1166 |
– |
regs.spcflags &= ~(SPCFLAG_INT | SPCFLAG_DOINT); |
1272 |
|
if (intr != -1 && intr > regs.intmask) { |
1273 |
|
Interrupt (intr); |
1274 |
|
regs.stopped = 0; |
1275 |
< |
regs.spcflags &= ~SPCFLAG_STOP; |
1275 |
> |
SPCFLAGS_CLEAR( SPCFLAG_STOP ); |
1276 |
|
} |
1277 |
|
} |
1278 |
|
} |
1279 |
< |
if (regs.spcflags & SPCFLAG_TRACE) |
1279 |
> |
if (SPCFLAGS_TEST( SPCFLAG_TRACE )) |
1280 |
|
do_trace (); |
1281 |
|
|
1282 |
< |
if (regs.spcflags & SPCFLAG_DOINT) { |
1282 |
> |
if (SPCFLAGS_TEST( SPCFLAG_DOINT )) { |
1283 |
> |
SPCFLAGS_CLEAR( SPCFLAG_DOINT ); |
1284 |
|
int intr = intlev (); |
1179 |
– |
regs.spcflags &= ~SPCFLAG_DOINT; |
1285 |
|
if (intr != -1 && intr > regs.intmask) { |
1286 |
|
Interrupt (intr); |
1287 |
|
regs.stopped = 0; |
1288 |
|
} |
1289 |
|
} |
1290 |
< |
if (regs.spcflags & SPCFLAG_INT) { |
1291 |
< |
regs.spcflags &= ~SPCFLAG_INT; |
1292 |
< |
regs.spcflags |= SPCFLAG_DOINT; |
1293 |
< |
} |
1294 |
< |
if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) { |
1295 |
< |
regs.spcflags &= ~(SPCFLAG_BRK | SPCFLAG_MODE_CHANGE); |
1296 |
< |
return 1; |
1290 |
> |
if (SPCFLAGS_TEST( SPCFLAG_INT )) { |
1291 |
> |
SPCFLAGS_CLEAR( SPCFLAG_INT ); |
1292 |
> |
SPCFLAGS_SET( SPCFLAG_DOINT ); |
1293 |
> |
} |
1294 |
> |
if (SPCFLAGS_TEST( SPCFLAG_BRK )) { |
1295 |
> |
SPCFLAGS_CLEAR( SPCFLAG_BRK ); |
1296 |
> |
return CFLOW_EXEC_RETURN; |
1297 |
|
} |
1298 |
|
return 0; |
1299 |
|
} |
1300 |
|
|
1301 |
< |
static void m68k_run_1 (void) |
1301 |
> |
void m68k_do_execute (void) |
1302 |
|
{ |
1303 |
|
for (;;) { |
1304 |
|
uae_u32 opcode = GET_OPCODE; |
1305 |
+ |
#if FLIGHT_RECORDER |
1306 |
+ |
record_step(m68k_getpc()); |
1307 |
+ |
#endif |
1308 |
+ |
#ifdef X86_ASSEMBLY |
1309 |
+ |
__asm__ __volatile__("\tpushl %%ebp\n\tcall *%%ebx\n\tpopl %%ebp" /* FIXME */ |
1310 |
+ |
: : "b" (cpufunctbl[opcode]), "a" (opcode) |
1311 |
+ |
: "%edx", "%ecx", "%esi", "%edi", "%ebp", "memory", "cc"); |
1312 |
+ |
#else |
1313 |
|
(*cpufunctbl[opcode])(opcode); |
1314 |
< |
if (regs.spcflags) { |
1315 |
< |
if (do_specialties()) |
1314 |
> |
#endif |
1315 |
> |
if (SPCFLAGS_TEST(SPCFLAG_ALL_BUT_EXEC_RETURN)) { |
1316 |
> |
if (m68k_do_specialties()) |
1317 |
|
return; |
1318 |
|
} |
1319 |
|
} |
1320 |
|
} |
1321 |
|
|
1322 |
< |
#define m68k_run1 m68k_run_1 |
1209 |
< |
|
1210 |
< |
int in_m68k_go = 0; |
1211 |
< |
|
1212 |
< |
void m68k_go (int may_quit) |
1322 |
> |
void m68k_execute (void) |
1323 |
|
{ |
1214 |
– |
// m68k_go() must be reentrant for Execute68k() and Execute68kTrap() to work |
1215 |
– |
/* |
1216 |
– |
if (in_m68k_go || !may_quit) { |
1217 |
– |
write_log("Bug! m68k_go is not reentrant.\n"); |
1218 |
– |
abort(); |
1219 |
– |
} |
1220 |
– |
*/ |
1221 |
– |
in_m68k_go++; |
1324 |
|
for (;;) { |
1325 |
|
if (quit_program > 0) { |
1326 |
|
if (quit_program == 1) |
1328 |
|
quit_program = 0; |
1329 |
|
m68k_reset (); |
1330 |
|
} |
1331 |
< |
m68k_run1(); |
1331 |
> |
m68k_do_execute(); |
1332 |
|
} |
1333 |
|
if (debugging) { |
1334 |
|
uaecptr nextpc; |
1335 |
|
m68k_dumpstate(&nextpc); |
1336 |
|
exit(1); |
1337 |
|
} |
1236 |
– |
in_m68k_go--; |
1338 |
|
} |
1339 |
|
|
1340 |
|
static void m68k_verify (uaecptr addr, uaecptr *nextpc) |