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root/cebix/BasiliskII/src/uae_cpu/newcpu.cpp

Comparing BasiliskII/src/uae_cpu/newcpu.cpp (file contents):
Revision 1.4 by cebix, 1999-10-31T23:18:42Z vs.
Revision 1.13 by gbeauche, 2002-09-01T15:17:13Z

#	Line 22 | Line 22 | extern int intlev(void);       // From baisili
22		#include "memory.h"
23		#include "readcpu.h"
24		#include "newcpu.h"
25	<	#include "compiler.h"
25	>
26	>	#if defined(ENABLE_EXCLUSIVE_SPCFLAGS) && !defined(HAVE_HARDWARE_LOCKS) && defined(HAVE_PTHREADS)
27	>	#include <pthread.h>
28	>	pthread_mutex_t spcflags_lock = PTHREAD_MUTEX_INITIALIZER;
29	>	#endif
30	>
31	>	#if ENABLE_MON
32	>	#include "mon.h"
33	>	#include "mon_disass.h"
34	>	#endif
35
36		int quit_program = 0;
37	<	int debugging = 0;
37	>	const int debugging = 0;
38		struct flag_struct regflags;
39
40		/* Opcode of faulting instruction */
#	Line 48 | Line 57 | int fpp_movem_next[256];
57
58		cpuop_func *cpufunctbl[65536];
59
60	+	#define FLIGHT_RECORDER 0
61	+
62	+	#if FLIGHT_RECORDER
63	+	struct rec_step {
64	+	uae_u32 d[8];
65	+	uae_u32 a[8];
66	+	uae_u32 pc;
67	+	};
68	+
69	+	const int LOG_SIZE = 8192;
70	+	static rec_step log[LOG_SIZE];
71	+	static int log_ptr = -1; // First time initialization
72	+
73	+	static const char *log_filename(void)
74	+	{
75	+	const char *name = getenv("M68K_LOG_FILE");
76	+	return name ? name : "log.68k";
77	+	}
78	+
79	+	static void record_step(uaecptr pc)
80	+	{
81	+	for (int i = 0; i < 8; i++) {
82	+	log[log_ptr].d[i] = m68k_dreg(regs, i);
83	+	log[log_ptr].a[i] = m68k_areg(regs, i);
84	+	}
85	+	log[log_ptr].pc = pc;
86	+	log_ptr = (log_ptr + 1) % LOG_SIZE;
87	+	}
88	+
89	+	static void dump_log(void)
90	+	{
91	+	FILE *f = fopen(log_filename(), "w");
92	+	if (f == NULL)
93	+	return;
94	+	for (int i = 0; i < LOG_SIZE; i++) {
95	+	int j = (i + log_ptr) % LOG_SIZE;
96	+	fprintf(f, "pc %08x\n", log[j].pc);
97	+	fprintf(f, "d0 %08x d1 %08x d2 %08x d3 %08x\n", log[j].d[0], log[j].d[1], log[j].d[2], log[j].d[3]);
98	+	fprintf(f, "d4 %08x d5 %08x d6 %08x d7 %08x\n", log[j].d[4], log[j].d[5], log[j].d[6], log[j].d[7]);
99	+	fprintf(f, "a0 %08x a1 %08x a2 %08x a3 %08x\n", log[j].a[0], log[j].a[1], log[j].a[2], log[j].a[3]);
100	+	fprintf(f, "a4 %08x a5 %08x a6 %08x a7 %08x\n", log[j].a[4], log[j].a[5], log[j].a[6], log[j].a[7]);
101	+	#if ENABLE_MON
102	+	disass_68k(f, log[j].pc);
103	+	#endif
104	+	}
105	+	fclose(f);
106	+	}
107	+	#endif
108	+
109		#define COUNT_INSTRS 0
110
111		#if COUNT_INSTRS
#	Line 111 | Line 169 | static __inline__ unsigned int cft_map (
169		#endif
170		}
171
172	<	static void REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM;
172	>	cpuop_rettype REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM;
173
174	<	static void REGPARAM2 op_illg_1 (uae_u32 opcode)
174	>	cpuop_rettype REGPARAM2 op_illg_1 (uae_u32 opcode)
175		{
176	<	op_illg (cft_map (opcode));
176	>	cpuop_return( op_illg (cft_map (opcode)) );
177		}
178
179		static void build_cpufunctbl (void)
#	Line 134 | Line 192 | static void build_cpufunctbl (void)
192		cpu_level = 1;
193		}
194		struct cputbl *tbl = (
195	<	cpu_level == 4 ? op_smalltbl_0
196	<	: cpu_level == 3 ? op_smalltbl_1
197	<	: cpu_level == 2 ? op_smalltbl_2
198	<	: cpu_level == 1 ? op_smalltbl_3
199	<	: op_smalltbl_4);
195	>	cpu_level == 4 ? op_smalltbl_0_ff
196	>	: cpu_level == 3 ? op_smalltbl_1_ff
197	>	: cpu_level == 2 ? op_smalltbl_2_ff
198	>	: cpu_level == 1 ? op_smalltbl_3_ff
199	>	: op_smalltbl_4_ff);
200
201		for (opcode = 0; opcode < 65536; opcode++)
202		cpufunctbl[cft_map (opcode)] = op_illg_1;
#	Line 183 | Line 241 | void init_m68k (void)
241		for (j = 7 ; j >= 0 ; j--) {
242		if (i & (1 << j)) break;
243		}
244	<	fpp_movem_index1[i] = j;
245	<	fpp_movem_index2[i] = 7-j;
244	>	fpp_movem_index1[i] = 7-j;
245	>	fpp_movem_index2[i] = j;
246		fpp_movem_next[i] = i & (~(1 << j));
247		}
248		#if COUNT_INSTRS
#	Line 207 | Line 265 | void init_m68k (void)
265		do_merges ();
266
267		build_cpufunctbl ();
268	+
269	+	fpu_init ();
270	+	fpu_set_integral_fpu (CPUType == 4);
271	+	}
272	+
273	+	void exit_m68k (void)
274	+	{
275	+	fpu_exit ();
276		}
277
278		struct regstruct regs, lastint_regs;
#	Line 215 | Line 281 | static int backup_pointer = 0;
281		static long int m68kpc_offset;
282		int lastint_no;
283
284	+	#if REAL_ADDRESSING || DIRECT_ADDRESSING
285	+	#define get_ibyte_1(o) get_byte(get_virtual_address(regs.pc_p) + (o) + 1)
286	+	#define get_iword_1(o) get_word(get_virtual_address(regs.pc_p) + (o))
287	+	#define get_ilong_1(o) get_long(get_virtual_address(regs.pc_p) + (o))
288	+	#else
289		#define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
290		#define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
291		#define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
292	+	#endif
293
294		uae_s32 ShowEA (int reg, amodes mode, wordsizes size, char *buf)
295		{
#	Line 250 | Line 322 | uae_s32 ShowEA (int reg, amodes mode, wo
322		disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
323		addr = m68k_areg(regs,reg) + (uae_s16)disp16;
324		sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
325	<	(long unsigned int)addr);
325	>	(unsigned long)addr);
326		break;
327		case Ad8r:
328		dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
#	Line 283 | Line 355 | uae_s32 ShowEA (int reg, amodes mode, wo
355		dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
356		1 << ((dp >> 9) & 3),
357		disp,outer,
358	<	(long unsigned int)addr);
358	>	(unsigned long)addr);
359		} else {
360		addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
361		sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
362		dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
363		1 << ((dp >> 9) & 3), disp8,
364	<	(long unsigned int)addr);
364	>	(unsigned long)addr);
365		}
366		break;
367		case PC16:
368		addr = m68k_getpc () + m68kpc_offset;
369		disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
370		addr += (uae_s16)disp16;
371	<	sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(long unsigned int)addr);
371	>	sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
372		break;
373		case PC8r:
374		addr = m68k_getpc () + m68kpc_offset;
#	Line 330 | Line 402 | uae_s32 ShowEA (int reg, amodes mode, wo
402		dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
403		1 << ((dp >> 9) & 3),
404		disp,outer,
405	<	(long unsigned int)addr);
405	>	(unsigned long)addr);
406		} else {
407		addr += (uae_s32)((uae_s8)disp8) + dispreg;
408		sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
409		(int)r, dp & 0x800 ? 'L' : 'W',  1 << ((dp >> 9) & 3),
410	<	disp8, (long unsigned int)addr);
410	>	disp8, (unsigned long)addr);
411		}
412		break;
413		case absw:
414	<	sprintf (buffer,"$%08lx", (long unsigned int)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
414	>	sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
415		m68kpc_offset += 2;
416		break;
417		case absl:
418	<	sprintf (buffer,"$%08lx", (long unsigned int)get_ilong_1 (m68kpc_offset));
418	>	sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
419		m68kpc_offset += 4;
420		break;
421		case imm:
#	Line 357 | Line 429 | uae_s32 ShowEA (int reg, amodes mode, wo
429		m68kpc_offset += 2;
430		break;
431		case sz_long:
432	<	sprintf (buffer,"#$%08lx", (long unsigned int)(get_ilong_1 (m68kpc_offset)));
432	>	sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
433		m68kpc_offset += 4;
434		break;
435		default:
#	Line 377 | Line 449 | uae_s32 ShowEA (int reg, amodes mode, wo
449		case imm2:
450		offset = (uae_s32)get_ilong_1 (m68kpc_offset);
451		m68kpc_offset += 4;
452	<	sprintf (buffer,"#$%08lx", (long unsigned int)offset);
452	>	sprintf (buffer,"#$%08lx", (unsigned long)offset);
453		break;
454		case immi:
455		offset = (uae_s32)(uae_s8)(reg & 0xff);
456	<	sprintf (buffer,"#$%08lx", (long unsigned int)offset);
456	>	sprintf (buffer,"#$%08lx", (unsigned long)offset);
457		break;
458		default:
459		break;
#	Line 636 | Line 708 | void MakeFromSR (void)
708		}
709		}
710
711	<	regs.spcflags |= SPCFLAG_INT;
711	>	SPCFLAGS_SET( SPCFLAG_INT );
712		if (regs.t1 || regs.t0)
713	<	regs.spcflags |= SPCFLAG_TRACE;
713	>	SPCFLAGS_SET( SPCFLAG_TRACE );
714		else
715	<	regs.spcflags &= ~(SPCFLAG_TRACE | SPCFLAG_DOTRACE);
715	>	/* Keep SPCFLAG_DOTRACE, we still want a trace exception for
716	>	SR-modifying instructions (including STOP).  */
717	>	SPCFLAGS_CLEAR( SPCFLAG_TRACE );
718		}
719
720		void Exception(int nr, uaecptr oldpc)
721		{
722	<	compiler_flush_jsr_stack();
722	>	uae_u32 currpc = m68k_getpc ();
723		MakeSR();
724		if (!regs.s) {
725		regs.usp = m68k_areg(regs, 7);
#	Line 674 | Line 748 | void Exception(int nr, uaecptr oldpc)
748		m68k_areg(regs, 7) -= 2;
749		put_word (m68k_areg(regs, 7), nr * 4);
750		m68k_areg(regs, 7) -= 4;
751	<	put_long (m68k_areg(regs, 7), m68k_getpc ());
751	>	put_long (m68k_areg(regs, 7), currpc);
752		m68k_areg(regs, 7) -= 2;
753		put_word (m68k_areg(regs, 7), regs.sr);
754		regs.sr |= (1 << 13);
#	Line 700 | Line 774 | void Exception(int nr, uaecptr oldpc)
774		}
775		}
776		m68k_areg(regs, 7) -= 4;
777	<	put_long (m68k_areg(regs, 7), m68k_getpc ());
777	>	put_long (m68k_areg(regs, 7), currpc);
778		kludge_me_do:
779		m68k_areg(regs, 7) -= 2;
780		put_word (m68k_areg(regs, 7), regs.sr);
781		m68k_setpc (get_long (regs.vbr + 4*nr));
782	+	SPCFLAGS_SET( SPCFLAG_JIT_END_COMPILE );
783		fill_prefetch_0 ();
784		regs.t1 = regs.t0 = regs.m = 0;
785	<	regs.spcflags &= ~(SPCFLAG_TRACE | SPCFLAG_DOTRACE);
785	>	SPCFLAGS_CLEAR( SPCFLAG_TRACE | SPCFLAG_DOTRACE );
786		}
787
788		static void Interrupt(int nr)
#	Line 718 | Line 793 | static void Interrupt(int nr)
793		Exception(nr+24, 0);
794
795		regs.intmask = nr;
796	<	regs.spcflags |= SPCFLAG_INT;
796	>	SPCFLAGS_SET( SPCFLAG_INT );
797		}
798
799	<	static int caar, cacr, tc, itt0, itt1, dtt0, dtt1;
799	>	static int caar, cacr, tc, itt0, itt1, dtt0, dtt1, mmusr, urp, srp;
800
801	<	void m68k_move2c (int regno, uae_u32 *regp)
801	>	int m68k_move2c (int regno, uae_u32 *regp)
802		{
803	<	if (CPUType == 1 && (regno & 0x7FF) > 1)
803	>	if ((CPUType == 1 && (regno & 0x7FF) > 1)
804	>	|| (CPUType < 4 && (regno & 0x7FF) > 2)
805	>	|| (CPUType == 4 && regno == 0x802))
806	>	{
807		op_illg (0x4E7B);
808	<	else
808	>	return 0;
809	>	} else {
810		switch (regno) {
811		case 0: regs.sfc = *regp & 7; break;
812		case 1: regs.dfc = *regp & 7; break;
813	<	case 2: cacr = *regp & 0x3; break;     /* ignore C and CE */
813	>	case 2: cacr = *regp & (CPUType < 4 ? 0x3 : 0x80008000); break;
814		case 3: tc = *regp & 0xc000; break;
815		case 4: itt0 = *regp & 0xffffe364; break;
816		case 5: itt1 = *regp & 0xffffe364; break;
#	Line 742 | Line 821 | void m68k_move2c (int regno, uae_u32 *re
821		case 0x802: caar = *regp &0xfc; break;
822		case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
823		case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
824	+	case 0x805: mmusr = *regp; break;
825	+	case 0x806: urp = *regp; break;
826	+	case 0x807: srp = *regp; break;
827		default:
828		op_illg (0x4E7B);
829	<	break;
829	>	return 0;
830		}
831	+	}
832	+	return 1;
833		}
834
835	<	void m68k_movec2 (int regno, uae_u32 *regp)
835	>	int m68k_movec2 (int regno, uae_u32 *regp)
836		{
837	<	if (CPUType == 1 && (regno & 0x7FF) > 1)
837	>	if ((CPUType == 1 && (regno & 0x7FF) > 1)
838	>	|| (CPUType < 4 && (regno & 0x7FF) > 2)
839	>	|| (CPUType == 4 && regno == 0x802))
840	>	{
841		op_illg (0x4E7A);
842	<	else
842	>	return 0;
843	>	} else {
844		switch (regno) {
845		case 0: *regp = regs.sfc; break;
846		case 1: *regp = regs.dfc; break;
#	Line 767 | Line 855 | void m68k_movec2 (int regno, uae_u32 *re
855		case 0x802: *regp = caar; break;
856		case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
857		case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
858	+	case 0x805: *regp = mmusr; break;
859	+	case 0x806: *regp = urp; break;
860	+	case 0x807: *regp = srp; break;
861		default:
862		op_illg (0x4E7A);
863	<	break;
863	>	return 0;
864		}
865	+	}
866	+	return 1;
867		}
868
869		static __inline__ int
#	Line 1028 | Line 1121 | static char* ccnames[] =
1121		{ "T ","F ","HI","LS","CC","CS","NE","EQ",
1122		"VC","VS","PL","MI","GE","LT","GT","LE" };
1123
1124	+	// If value is greater than zero, this means we are still processing an EmulOp
1125	+	// because the counter is incremented only in m68k_execute(), i.e. interpretive
1126	+	// execution only
1127	+	static int m68k_execute_depth = 0;
1128	+
1129		void m68k_reset (void)
1130		{
1131		m68k_areg (regs, 7) = 0x2000;
1132		m68k_setpc (ROMBaseMac + 0x2a);
1133		fill_prefetch_0 ();
1036	–	regs.kick_mask = 0xF80000;
1134		regs.s = 1;
1135		regs.m = 0;
1136		regs.stopped = 0;
#	Line 1044 | Line 1141 | void m68k_reset (void)
1141		SET_CFLG (0);
1142		SET_VFLG (0);
1143		SET_NFLG (0);
1144	<	regs.spcflags = 0;
1144	>	SPCFLAGS_INIT( 0 );
1145		regs.intmask = 7;
1146		regs.vbr = regs.sfc = regs.dfc = 0;
1147	<	regs.fpcr = regs.fpsr = regs.fpiar = 0;
1147	>	fpu_reset();
1148	>
1149	>	#if FLIGHT_RECORDER
1150	>	#if ENABLE_MON
1151	>	if (log_ptr == -1) {
1152	>	// Install "log" command in mon
1153	>	mon_add_command("log", dump_log, "log                      Dump m68k emulation log\n");
1154	>	}
1155	>	#endif
1156	>	log_ptr = 0;
1157	>	memset(log, 0, sizeof(log));
1158	>	#endif
1159		}
1160
1161	<	void REGPARAM2 op_illg (uae_u32 opcode)
1161	>	void m68k_emulop_return(void)
1162		{
1163	<	uaecptr pc = m68k_getpc ();
1164	<
1165	<	compiler_flush_jsr_stack ();
1163	>	SPCFLAGS_SET( SPCFLAG_BRK );
1164	>	quit_program = 1;
1165	>	}
1166
1167	<	if ((opcode & 0xFF00) == 0x7100) {
1167	>	void m68k_emulop(uae_u32 opcode)
1168	>	{
1169		struct M68kRegisters r;
1170		int i;
1171
1063	–	// Return from Execute68k()?
1064	–	if (opcode == M68K_EXEC_RETURN) {
1065	–	regs.spcflags |= SPCFLAG_BRK;
1066	–	quit_program = 1;
1067	–	return;
1068	–	}
1069	–
1070	–	// Call EMUL_OP opcode
1172		for (i=0; i<8; i++) {
1173		r.d[i] = m68k_dreg(regs, i);
1174		r.a[i] = m68k_areg(regs, i);
#	Line 1081 | Line 1182 | void REGPARAM2 op_illg (uae_u32 opcode)
1182		}
1183		regs.sr = r.sr;
1184		MakeFromSR();
1185	<	m68k_incpc(2);
1186	<	fill_prefetch_0 ();
1187	<	return;
1188	<	}
1185	>	}
1186	>
1187	>	cpuop_rettype REGPARAM2 op_illg (uae_u32 opcode)
1188	>	{
1189	>	uaecptr pc = m68k_getpc ();
1190
1191		if ((opcode & 0xF000) == 0xA000) {
1192		Exception(0xA,0);
1193	<	return;
1193	>	cpuop_return(CFLOW_TRAP);
1194		}
1195
1094	–	//    write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc);
1095	–
1196		if ((opcode & 0xF000) == 0xF000) {
1197		Exception(0xB,0);
1198	<	return;
1198	>	cpuop_return(CFLOW_TRAP);
1199		}
1200
1201		write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc);
1202
1203		Exception (4,0);
1204	+	cpuop_return(CFLOW_TRAP);
1205		}
1206
1207		void mmu_op(uae_u32 opcode, uae_u16 extra)
1208		{
1209	<	if ((extra & 0xB000) == 0) { /* PMOVE instruction */
1210	<
1211	<	} else if ((extra & 0xF000) == 0x2000) { /* PLOAD instruction */
1212	<	} else if ((extra & 0xF000) == 0x8000) { /* PTEST instruction */
1209	>	if ((opcode & 0xFE0) == 0x0500) {
1210	>	/* PFLUSH */
1211	>	mmusr = 0;
1212	>	} else if ((opcode & 0x0FD8) == 0x548) {
1213	>	/* PTEST */
1214		} else
1215	<	op_illg (opcode);
1215	>	op_illg (opcode);
1216		}
1217
1218		static int n_insns = 0, n_spcinsns = 0;
#	Line 1119 | Line 1221 | static uaecptr last_trace_ad = 0;
1221
1222		static void do_trace (void)
1223		{
1224	<	if (regs.t0) {
1224	>	if (regs.t0 && CPUType >= 2) {
1225		uae_u16 opcode;
1226		/* should also include TRAP, CHK, SR modification FPcc */
1227		/* probably never used so why bother */
1228		/* We can afford this to be inefficient... */
1229		m68k_setpc (m68k_getpc ());
1230		fill_prefetch_0 ();
1231	<	opcode = get_word (regs.pc);
1231	>	opcode = get_word(m68k_getpc());
1232		if (opcode == 0x4e72            /* RTE */
1233		|| opcode == 0x4e74                 /* RTD */
1234		|| opcode == 0x4e75                 /* RTS */
#	Line 1142 | Line 1244 | static void do_trace (void)
1244		&& (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1245		{
1246		last_trace_ad = m68k_getpc ();
1247	<	regs.spcflags &= ~SPCFLAG_TRACE;
1248	<	regs.spcflags |= SPCFLAG_DOTRACE;
1247	>	SPCFLAGS_CLEAR( SPCFLAG_TRACE );
1248	>	SPCFLAGS_SET( SPCFLAG_DOTRACE );
1249		}
1250		} else if (regs.t1) {
1251		last_trace_ad = m68k_getpc ();
1252	<	regs.spcflags &= ~SPCFLAG_TRACE;
1253	<	regs.spcflags |= SPCFLAG_DOTRACE;
1252	>	SPCFLAGS_CLEAR( SPCFLAG_TRACE );
1253	>	SPCFLAGS_SET( SPCFLAG_DOTRACE );
1254		}
1255		}
1256
1257	<
1156	<	static int do_specialties (void)
1257	>	int m68k_do_specialties (void)
1258		{
1259	<	/*n_spcinsns++;*/
1159	<	run_compiled_code();
1160	<	if (regs.spcflags & SPCFLAG_DOTRACE) {
1259	>	if (SPCFLAGS_TEST( SPCFLAG_DOTRACE )) {
1260		Exception (9,last_trace_ad);
1261		}
1262	<	while (regs.spcflags & SPCFLAG_STOP) {
1263	<	if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)){
1262	>	while (SPCFLAGS_TEST( SPCFLAG_STOP )) {
1263	>	if (SPCFLAGS_TEST( SPCFLAG_INT | SPCFLAG_DOINT )){
1264	>	SPCFLAGS_CLEAR( SPCFLAG_INT | SPCFLAG_DOINT );
1265		int intr = intlev ();
1166	–	regs.spcflags &= ~(SPCFLAG_INT | SPCFLAG_DOINT);
1266		if (intr != -1 && intr > regs.intmask) {
1267		Interrupt (intr);
1268		regs.stopped = 0;
1269	<	regs.spcflags &= ~SPCFLAG_STOP;
1269	>	SPCFLAGS_CLEAR( SPCFLAG_STOP );
1270		}
1271		}
1272		}
1273	<	if (regs.spcflags & SPCFLAG_TRACE)
1273	>	if (SPCFLAGS_TEST( SPCFLAG_TRACE ))
1274		do_trace ();
1275
1276	<	if (regs.spcflags & SPCFLAG_DOINT) {
1276	>	if (SPCFLAGS_TEST( SPCFLAG_DOINT )) {
1277	>	SPCFLAGS_CLEAR( SPCFLAG_DOINT );
1278		int intr = intlev ();
1179	–	regs.spcflags &= ~SPCFLAG_DOINT;
1279		if (intr != -1 && intr > regs.intmask) {
1280		Interrupt (intr);
1281		regs.stopped = 0;
1282		}
1283		}
1284	<	if (regs.spcflags & SPCFLAG_INT) {
1285	<	regs.spcflags &= ~SPCFLAG_INT;
1286	<	regs.spcflags |= SPCFLAG_DOINT;
1287	<	}
1288	<	if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1289	<	regs.spcflags &= ~(SPCFLAG_BRK | SPCFLAG_MODE_CHANGE);
1290	<	return 1;
1284	>	if (SPCFLAGS_TEST( SPCFLAG_INT )) {
1285	>	SPCFLAGS_CLEAR( SPCFLAG_INT );
1286	>	SPCFLAGS_SET( SPCFLAG_DOINT );
1287	>	}
1288	>	if (SPCFLAGS_TEST( SPCFLAG_BRK )) {
1289	>	SPCFLAGS_CLEAR( SPCFLAG_BRK );
1290	>	return CFLOW_EXEC_RETURN;
1291		}
1292		return 0;
1293		}
1294
1295	<	static void m68k_run_1 (void)
1295	>	void m68k_do_execute (void)
1296		{
1297		for (;;) {
1298		uae_u32 opcode = GET_OPCODE;
1299	+	#if FLIGHT_RECORDER
1300	+	record_step(m68k_getpc());
1301	+	#endif
1302	+	#ifdef X86_ASSEMBLY
1303	+	__asm__ __volatile__("\tpushl %%ebp\n\tcall *%%ebx\n\tpopl %%ebp" /* FIXME */
1304	+	: : "b" (cpufunctbl[opcode]), "a" (opcode)
1305	+	: "%edx", "%ecx", "%esi", "%edi",  "%ebp", "memory", "cc");
1306	+	#else
1307		(*cpufunctbl[opcode])(opcode);
1308	<	if (regs.spcflags) {
1309	<	if (do_specialties())
1308	>	#endif
1309	>	if (SPCFLAGS_TEST(SPCFLAG_ALL_BUT_EXEC_RETURN)) {
1310	>	if (m68k_do_specialties())
1311		return;
1312		}
1313		}
1314		}
1315
1316	<	#define m68k_run1 m68k_run_1
1209	<
1210	<	int in_m68k_go = 0;
1211	<
1212	<	void m68k_go (int may_quit)
1316	>	void m68k_execute (void)
1317		{
1214	–	// m68k_go() must be reentrant for Execute68k() and Execute68kTrap() to work
1215	–	/*
1216	–	if (in_m68k_go || !may_quit) {
1217	–	write_log("Bug! m68k_go is not reentrant.\n");
1218	–	abort();
1219	–	}
1220	–	*/
1221	–	in_m68k_go++;
1318		for (;;) {
1319		if (quit_program > 0) {
1320		if (quit_program == 1)
#	Line 1226 | Line 1322 | void m68k_go (int may_quit)
1322		quit_program = 0;
1323		m68k_reset ();
1324		}
1325	<	m68k_run1();
1325	>	m68k_do_execute();
1326		}
1327		if (debugging) {
1328		uaecptr nextpc;
1329		m68k_dumpstate(&nextpc);
1330		exit(1);
1331		}
1236	–	in_m68k_go--;
1332		}
1333
1334		static void m68k_verify (uaecptr addr, uaecptr *nextpc)

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