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root/cebix/BasiliskII/src/uae_cpu/newcpu.cpp

Comparing BasiliskII/src/uae_cpu/newcpu.cpp (file contents):
Revision 1.17 by gbeauche, 2002-10-01T09:39:55Z vs.
Revision 1.20 by gbeauche, 2005-06-04T16:47:14Z

#	Line 55 | Line 55 | cpuop_func *cpufunctbl[65536];
55
56		#if FLIGHT_RECORDER
57		struct rec_step {
58	+	uae_u32 pc;
59	+	#if FLIGHT_RECORDER >= 2
60		uae_u32 d[8];
61		uae_u32 a[8];
62	<	uae_u32 pc;
62	>	#endif
63		};
64
65	<	const int LOG_SIZE = 8192;
65	>	const int LOG_SIZE = 32768;
66		static rec_step log[LOG_SIZE];
67		static int log_ptr = -1; // First time initialization
68
#	Line 72 | Line 74 | static const char *log_filename(void)
74
75		void m68k_record_step(uaecptr pc)
76		{
77	<	for (int i = 0; i < 8; i++) {
78	<	log[log_ptr].d[i] = m68k_dreg(regs, i);
79	<	log[log_ptr].a[i] = m68k_areg(regs, i);
77	>	#if FLIGHT_RECORDER >= 2
78	>	/* XXX: if LSB is set, we are recording from generated code and we
79	>	don't support registers recording yet.  */
80	>	if ((pc & 1) == 0) {
81	>	for (int i = 0; i < 8; i++) {
82	>	log[log_ptr].d[i] = m68k_dreg(regs, i);
83	>	log[log_ptr].a[i] = m68k_areg(regs, i);
84	>	}
85		}
86	+	#endif
87		log[log_ptr].pc = pc;
88		log_ptr = (log_ptr + 1) % LOG_SIZE;
89		}
#	Line 87 | Line 95 | static void dump_log(void)
95		return;
96		for (int i = 0; i < LOG_SIZE; i++) {
97		int j = (i + log_ptr) % LOG_SIZE;
98	<	fprintf(f, "pc %08x\n", log[j].pc);
99	<	fprintf(f, "d0 %08x d1 %08x d2 %08x d3 %08x\n", log[j].d[0], log[j].d[1], log[j].d[2], log[j].d[3]);
100	<	fprintf(f, "d4 %08x d5 %08x d6 %08x d7 %08x\n", log[j].d[4], log[j].d[5], log[j].d[6], log[j].d[7]);
101	<	fprintf(f, "a0 %08x a1 %08x a2 %08x a3 %08x\n", log[j].a[0], log[j].a[1], log[j].a[2], log[j].a[3]);
102	<	fprintf(f, "a4 %08x a5 %08x a6 %08x a7 %08x\n", log[j].a[4], log[j].a[5], log[j].a[6], log[j].a[7]);
98	>	uae_u32 pc = log[j].pc & ~1;
99	>	fprintf(f, "pc %08x", pc);
100	>	#if FLIGHT_RECORDER >= 2
101	>	fprintf(f, "\n");
102	>	if ((log[j].pc & 1) == 0) {
103	>	fprintf(f, "d0 %08x d1 %08x d2 %08x d3 %08x\n", log[j].d[0], log[j].d[1], log[j].d[2], log[j].d[3]);
104	>	fprintf(f, "d4 %08x d5 %08x d6 %08x d7 %08x\n", log[j].d[4], log[j].d[5], log[j].d[6], log[j].d[7]);
105	>	fprintf(f, "a0 %08x a1 %08x a2 %08x a3 %08x\n", log[j].a[0], log[j].a[1], log[j].a[2], log[j].a[3]);
106	>	fprintf(f, "a4 %08x a5 %08x a6 %08x a7 %08x\n", log[j].a[4], log[j].a[5], log[j].a[6], log[j].a[7]);
107	>	}
108	>	#else
109	>	fprintf(f, " | ");
110	>	#endif
111		#if ENABLE_MON
112	<	disass_68k(f, log[j].pc);
112	>	disass_68k(f, pc);
113		#endif
114		}
115		fclose(f);
116		}
117		#endif
118
119	+	#if ENABLE_MON
120	+	static void dump_regs(void)
121	+	{
122	+	m68k_dumpstate(NULL);
123	+	}
124	+	#endif
125	+
126		#define COUNT_INSTRS 0
127
128		#if COUNT_INSTRS
#	Line 163 | Line 186 | static __inline__ unsigned int cft_map (
186		#endif
187		}
188
189	<	cpuop_rettype REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM;
189	>	void REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM;
190
191	<	cpuop_rettype REGPARAM2 op_illg_1 (uae_u32 opcode)
191	>	void REGPARAM2 op_illg_1 (uae_u32 opcode)
192		{
193	<	cpuop_return( op_illg (cft_map (opcode)) );
193	>	op_illg (cft_map (opcode));
194		}
195
196		static void build_cpufunctbl (void)
#	Line 1152 | Line 1175 | void m68k_reset (void)
1175		fpu_reset();
1176
1177		#if FLIGHT_RECORDER
1178	+	log_ptr = 0;
1179	+	memset(log, 0, sizeof(log));
1180	+	#endif
1181	+
1182		#if ENABLE_MON
1183	<	if (log_ptr == -1) {
1183	>	static bool first_time = true;
1184	>	if (first_time) {
1185	>	first_time = false;
1186	>	mon_add_command("regs", dump_regs, "regs                    Dump m68k emulator registers\n");
1187	>	#if FLIGHT_RECORDER
1188		// Install "log" command in mon
1189		mon_add_command("log", dump_log, "log                      Dump m68k emulation log\n");
1159	–	}
1190		#endif
1191	<	log_ptr = 0;
1162	<	memset(log, 0, sizeof(log));
1191	>	}
1192		#endif
1193		}
1194
#	Line 1189 | Line 1218 | void m68k_emulop(uae_u32 opcode)
1218		MakeFromSR();
1219		}
1220
1221	<	cpuop_rettype REGPARAM2 op_illg (uae_u32 opcode)
1221	>	void REGPARAM2 op_illg (uae_u32 opcode)
1222		{
1223		uaecptr pc = m68k_getpc ();
1224
1225		if ((opcode & 0xF000) == 0xA000) {
1226		Exception(0xA,0);
1227	<	cpuop_return(CFLOW_TRAP);
1227	>	return;
1228		}
1229
1230		if ((opcode & 0xF000) == 0xF000) {
1231		Exception(0xB,0);
1232	<	cpuop_return(CFLOW_TRAP);
1232	>	return;
1233		}
1234
1235		write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc);
#	Line 1209 | Line 1238 | cpuop_rettype REGPARAM2 op_illg (uae_u32
1238		#endif
1239
1240		Exception (4,0);
1241	<	cpuop_return(CFLOW_TRAP);
1241	>	return;
1242		}
1243
1244		void mmu_op(uae_u32 opcode, uae_u16 extra)
#	Line 1307 | Line 1336 | int m68k_do_specialties (void)
1336		}
1337		if (SPCFLAGS_TEST( SPCFLAG_BRK )) {
1338		SPCFLAGS_CLEAR( SPCFLAG_BRK );
1339	<	return CFLOW_EXEC_RETURN;
1339	>	return 1;
1340		}
1341		return 0;
1342		}
#	Line 1327 | Line 1356 | void m68k_do_execute (void)
1356		}
1357		}
1358
1359	<	#if USE_JIT && !defined(X86_ASSEMBLY)
1359	>	#if USE_JIT && !(defined(X86_ASSEMBLY) || defined(X86_64_ASSEMBLY))
1360		void m68k_compile_execute (void)
1361		{
1362		for (;;) {

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