| 658 |
|
|
| 659 |
|
void Exception(int nr, uaecptr oldpc) |
| 660 |
|
{ |
| 661 |
+ |
uae_u32 currpc = m68k_getpc (); |
| 662 |
|
MakeSR(); |
| 663 |
|
if (!regs.s) { |
| 664 |
|
regs.usp = m68k_areg(regs, 7); |
| 687 |
|
m68k_areg(regs, 7) -= 2; |
| 688 |
|
put_word (m68k_areg(regs, 7), nr * 4); |
| 689 |
|
m68k_areg(regs, 7) -= 4; |
| 690 |
< |
put_long (m68k_areg(regs, 7), m68k_getpc ()); |
| 690 |
> |
put_long (m68k_areg(regs, 7), currpc); |
| 691 |
|
m68k_areg(regs, 7) -= 2; |
| 692 |
|
put_word (m68k_areg(regs, 7), regs.sr); |
| 693 |
|
regs.sr |= (1 << 13); |
| 713 |
|
} |
| 714 |
|
} |
| 715 |
|
m68k_areg(regs, 7) -= 4; |
| 716 |
< |
put_long (m68k_areg(regs, 7), m68k_getpc ()); |
| 716 |
> |
put_long (m68k_areg(regs, 7), currpc); |
| 717 |
|
kludge_me_do: |
| 718 |
|
m68k_areg(regs, 7) -= 2; |
| 719 |
|
put_word (m68k_areg(regs, 7), regs.sr); |
| 736 |
|
|
| 737 |
|
static int caar, cacr, tc, itt0, itt1, dtt0, dtt1; |
| 738 |
|
|
| 739 |
< |
void m68k_move2c (int regno, uae_u32 *regp) |
| 739 |
> |
int m68k_move2c (int regno, uae_u32 *regp) |
| 740 |
|
{ |
| 741 |
< |
if (CPUType == 1 && (regno & 0x7FF) > 1) |
| 741 |
> |
if ((CPUType == 1 && (regno & 0x7FF) > 1) |
| 742 |
> |
|| (CPUType < 4 && (regno & 0x7FF) > 2) |
| 743 |
> |
|| (CPUType == 4 && regno == 0x802)) |
| 744 |
> |
{ |
| 745 |
|
op_illg (0x4E7B); |
| 746 |
< |
else |
| 746 |
> |
return 0; |
| 747 |
> |
} else { |
| 748 |
|
switch (regno) { |
| 749 |
|
case 0: regs.sfc = *regp & 7; break; |
| 750 |
|
case 1: regs.dfc = *regp & 7; break; |
| 751 |
< |
case 2: cacr = *regp & 0x3; break; /* ignore C and CE */ |
| 751 |
> |
case 2: cacr = *regp & (CPUType < 4 ? 0x3 : 0x80008000); break; |
| 752 |
|
case 3: tc = *regp & 0xc000; break; |
| 753 |
|
case 4: itt0 = *regp & 0xffffe364; break; |
| 754 |
|
case 5: itt1 = *regp & 0xffffe364; break; |
| 761 |
|
case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break; |
| 762 |
|
default: |
| 763 |
|
op_illg (0x4E7B); |
| 764 |
< |
break; |
| 764 |
> |
return 0; |
| 765 |
|
} |
| 766 |
+ |
} |
| 767 |
+ |
return 1; |
| 768 |
|
} |
| 769 |
|
|
| 770 |
< |
void m68k_movec2 (int regno, uae_u32 *regp) |
| 770 |
> |
int m68k_movec2 (int regno, uae_u32 *regp) |
| 771 |
|
{ |
| 772 |
< |
if (CPUType == 1 && (regno & 0x7FF) > 1) |
| 772 |
> |
if ((CPUType == 1 && (regno & 0x7FF) > 1) |
| 773 |
> |
|| (CPUType < 4 && (regno & 0x7FF) > 2) |
| 774 |
> |
|| (CPUType == 4 && regno == 0x802)) |
| 775 |
> |
{ |
| 776 |
|
op_illg (0x4E7A); |
| 777 |
< |
else |
| 777 |
> |
return 0; |
| 778 |
> |
} else { |
| 779 |
|
switch (regno) { |
| 780 |
|
case 0: *regp = regs.sfc; break; |
| 781 |
|
case 1: *regp = regs.dfc; break; |
| 792 |
|
case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break; |
| 793 |
|
default: |
| 794 |
|
op_illg (0x4E7A); |
| 795 |
< |
break; |
| 795 |
> |
return 0; |
| 796 |
> |
} |
| 797 |
|
} |
| 798 |
+ |
return 1; |
| 799 |
|
} |
| 800 |
|
|
| 801 |
|
static __inline__ int |
| 1085 |
|
struct M68kRegisters r; |
| 1086 |
|
int i; |
| 1087 |
|
|
| 1088 |
< |
// Return from Execute68k()? |
| 1088 |
> |
// Return from Exectue68k()? |
| 1089 |
|
if (opcode == M68K_EXEC_RETURN) { |
| 1090 |
|
regs.spcflags |= SPCFLAG_BRK; |
| 1091 |
|
quit_program = 1; |
| 1144 |
|
|
| 1145 |
|
static void do_trace (void) |
| 1146 |
|
{ |
| 1147 |
< |
if (regs.t0) { |
| 1147 |
> |
if (regs.t0 && CPUType >= 2) { |
| 1148 |
|
uae_u16 opcode; |
| 1149 |
|
/* should also include TRAP, CHK, SR modification FPcc */ |
| 1150 |
|
/* probably never used so why bother */ |
