| 707 |
|
if (regs.t1 || regs.t0) |
| 708 |
|
regs.spcflags |= SPCFLAG_TRACE; |
| 709 |
|
else |
| 710 |
< |
regs.spcflags &= ~(SPCFLAG_TRACE | SPCFLAG_DOTRACE); |
| 710 |
> |
/* Keep SPCFLAG_DOTRACE, we still want a trace exception for |
| 711 |
> |
SR-modifying instructions (including STOP). */ |
| 712 |
> |
regs.spcflags &= ~SPCFLAG_TRACE; |
| 713 |
|
} |
| 714 |
|
|
| 715 |
|
void Exception(int nr, uaecptr oldpc) |
| 790 |
|
regs.spcflags |= SPCFLAG_INT; |
| 791 |
|
} |
| 792 |
|
|
| 793 |
< |
static int caar, cacr, tc, itt0, itt1, dtt0, dtt1; |
| 793 |
> |
static int caar, cacr, tc, itt0, itt1, dtt0, dtt1, mmusr, urp, srp; |
| 794 |
|
|
| 795 |
|
int m68k_move2c (int regno, uae_u32 *regp) |
| 796 |
|
{ |
| 797 |
|
if ((CPUType == 1 && (regno & 0x7FF) > 1) |
| 798 |
< |
|| (CPUType < 4 && (regno & 0x7FF) > 2) |
| 799 |
< |
|| (CPUType == 4 && regno == 0x802)) |
| 798 |
> |
|| (CPUType < 4 && (regno & 0x7FF) > 2) |
| 799 |
> |
|| (CPUType == 4 && regno == 0x802)) |
| 800 |
|
{ |
| 801 |
|
op_illg (0x4E7B); |
| 802 |
|
return 0; |
| 815 |
|
case 0x802: caar = *regp &0xfc; break; |
| 816 |
|
case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break; |
| 817 |
|
case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break; |
| 818 |
+ |
case 0x805: mmusr = *regp; break; |
| 819 |
+ |
case 0x806: urp = *regp; break; |
| 820 |
+ |
case 0x807: srp = *regp; break; |
| 821 |
|
default: |
| 822 |
|
op_illg (0x4E7B); |
| 823 |
|
return 0; |
| 829 |
|
int m68k_movec2 (int regno, uae_u32 *regp) |
| 830 |
|
{ |
| 831 |
|
if ((CPUType == 1 && (regno & 0x7FF) > 1) |
| 832 |
< |
|| (CPUType < 4 && (regno & 0x7FF) > 2) |
| 833 |
< |
|| (CPUType == 4 && regno == 0x802)) |
| 832 |
> |
|| (CPUType < 4 && (regno & 0x7FF) > 2) |
| 833 |
> |
|| (CPUType == 4 && regno == 0x802)) |
| 834 |
|
{ |
| 835 |
|
op_illg (0x4E7A); |
| 836 |
|
return 0; |
| 849 |
|
case 0x802: *regp = caar; break; |
| 850 |
|
case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break; |
| 851 |
|
case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break; |
| 852 |
+ |
case 0x805: *regp = mmusr; break; |
| 853 |
+ |
case 0x806: *regp = urp; break; |
| 854 |
+ |
case 0x807: *regp = srp; break; |
| 855 |
|
default: |
| 856 |
|
op_illg (0x4E7A); |
| 857 |
|
return 0; |
| 1203 |
|
|
| 1204 |
|
void mmu_op(uae_u32 opcode, uae_u16 extra) |
| 1205 |
|
{ |
| 1206 |
< |
if ((extra & 0xB000) == 0) { /* PMOVE instruction */ |
| 1207 |
< |
|
| 1208 |
< |
} else if ((extra & 0xF000) == 0x2000) { /* PLOAD instruction */ |
| 1209 |
< |
} else if ((extra & 0xF000) == 0x8000) { /* PTEST instruction */ |
| 1206 |
> |
if ((opcode & 0xFE0) == 0x0500) { |
| 1207 |
> |
/* PFLUSH */ |
| 1208 |
> |
mmusr = 0; |
| 1209 |
> |
} else if ((opcode & 0x0FD8) == 0x548) { |
| 1210 |
> |
/* PTEST */ |
| 1211 |
|
} else |
| 1212 |
< |
op_illg (opcode); |
| 1212 |
> |
op_illg (opcode); |
| 1213 |
|
} |
| 1214 |
|
|
| 1215 |
|
static int n_insns = 0, n_spcinsns = 0; |
| 1298 |
|
#if FLIGHT_RECORDER |
| 1299 |
|
record_step(m68k_getpc()); |
| 1300 |
|
#endif |
| 1301 |
+ |
#ifdef X86_ASSEMBLY |
| 1302 |
+ |
__asm__ __volatile__("\tpushl %%ebp\n\tcall *%%ebx\n\tpopl %%ebp" /* FIXME */ |
| 1303 |
+ |
: : "b" (cpufunctbl[opcode]), "a" (opcode) |
| 1304 |
+ |
: "%edx", "%ecx", "%esi", "%edi", "%ebp", "memory", "cc"); |
| 1305 |
+ |
#else |
| 1306 |
|
(*cpufunctbl[opcode])(opcode); |
| 1307 |
+ |
#endif |
| 1308 |
|
if (regs.spcflags) { |
| 1309 |
|
if (do_specialties()) |
| 1310 |
|
return; |
