| 1 |
cebix |
1.1 |
/* |
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* UAE - The Un*x Amiga Emulator |
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* |
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* MC68000 emulation |
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* |
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* (c) 1995 Bernd Schmidt |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include "sysdeps.h" |
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#include "cpu_emulation.h" |
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#include "main.h" |
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#include "emul_op.h" |
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extern int intlev(void); // From baisilisk_glue.cpp |
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#include "m68k.h" |
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#include "memory.h" |
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#include "readcpu.h" |
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#include "newcpu.h" |
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int quit_program = 0; |
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int debugging = 0; |
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struct flag_struct regflags; |
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/* Opcode of faulting instruction */ |
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uae_u16 last_op_for_exception_3; |
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/* PC at fault time */ |
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uaecptr last_addr_for_exception_3; |
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/* Address that generated the exception */ |
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uaecptr last_fault_for_exception_3; |
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int areg_byteinc[] = { 1,1,1,1,1,1,1,2 }; |
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int imm8_table[] = { 8,1,2,3,4,5,6,7 }; |
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int movem_index1[256]; |
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int movem_index2[256]; |
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int movem_next[256]; |
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int fpp_movem_index1[256]; |
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int fpp_movem_index2[256]; |
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int fpp_movem_next[256]; |
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cpuop_func *cpufunctbl[65536]; |
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#define COUNT_INSTRS 0 |
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#if COUNT_INSTRS |
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static unsigned long int instrcount[65536]; |
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static uae_u16 opcodenums[65536]; |
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static int compfn (const void *el1, const void *el2) |
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{ |
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return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2]; |
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} |
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static char *icountfilename (void) |
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{ |
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char *name = getenv ("INSNCOUNT"); |
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if (name) |
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return name; |
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return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount"; |
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} |
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void dump_counts (void) |
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{ |
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FILE *f = fopen (icountfilename (), "w"); |
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unsigned long int total; |
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int i; |
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write_log ("Writing instruction count file...\n"); |
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for (i = 0; i < 65536; i++) { |
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opcodenums[i] = i; |
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total += instrcount[i]; |
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} |
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qsort (opcodenums, 65536, sizeof(uae_u16), compfn); |
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fprintf (f, "Total: %lu\n", total); |
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for (i=0; i < 65536; i++) { |
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unsigned long int cnt = instrcount[opcodenums[i]]; |
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struct instr *dp; |
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struct mnemolookup *lookup; |
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if (!cnt) |
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break; |
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dp = table68k + opcodenums[i]; |
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for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++) |
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; |
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fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name); |
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} |
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fclose (f); |
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} |
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#else |
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void dump_counts (void) |
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{ |
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} |
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#endif |
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int broken_in; |
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static __inline__ unsigned int cft_map (unsigned int f) |
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{ |
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#ifndef HAVE_GET_WORD_UNSWAPPED |
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return f; |
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#else |
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return ((f >> 8) & 255) | ((f & 255) << 8); |
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#endif |
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} |
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cebix |
1.4 |
static void REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM; |
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cebix |
1.1 |
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cebix |
1.4 |
static void REGPARAM2 op_illg_1 (uae_u32 opcode) |
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cebix |
1.1 |
{ |
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op_illg (cft_map (opcode)); |
| 118 |
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} |
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| 120 |
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static void build_cpufunctbl (void) |
| 121 |
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{ |
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int i; |
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unsigned long opcode; |
| 124 |
cebix |
1.2 |
int cpu_level = 0; // 68000 (default) |
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if (CPUType == 4) |
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cpu_level = 4; // 68040 with FPU |
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else { |
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if (FPUType) |
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cpu_level = 3; // 68020 with FPU |
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else if (CPUType >= 2) |
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cpu_level = 2; // 68020 |
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else if (CPUType == 1) |
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cpu_level = 1; |
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} |
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struct cputbl *tbl = ( |
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cpu_level == 4 ? op_smalltbl_0 |
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: cpu_level == 3 ? op_smalltbl_1 |
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: cpu_level == 2 ? op_smalltbl_2 |
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: cpu_level == 1 ? op_smalltbl_3 |
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: op_smalltbl_4); |
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cebix |
1.1 |
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for (opcode = 0; opcode < 65536; opcode++) |
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cpufunctbl[cft_map (opcode)] = op_illg_1; |
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for (i = 0; tbl[i].handler != NULL; i++) { |
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if (! tbl[i].specific) |
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cpufunctbl[cft_map (tbl[i].opcode)] = tbl[i].handler; |
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} |
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for (opcode = 0; opcode < 65536; opcode++) { |
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cpuop_func *f; |
| 150 |
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| 151 |
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if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > cpu_level) |
| 152 |
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continue; |
| 153 |
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| 154 |
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if (table68k[opcode].handler != -1) { |
| 155 |
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f = cpufunctbl[cft_map (table68k[opcode].handler)]; |
| 156 |
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if (f == op_illg_1) |
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abort(); |
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cpufunctbl[cft_map (opcode)] = f; |
| 159 |
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} |
| 160 |
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} |
| 161 |
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for (i = 0; tbl[i].handler != NULL; i++) { |
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if (tbl[i].specific) |
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cpufunctbl[cft_map (tbl[i].opcode)] = tbl[i].handler; |
| 164 |
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} |
| 165 |
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} |
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| 167 |
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void init_m68k (void) |
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{ |
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int i; |
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for (i = 0 ; i < 256 ; i++) { |
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int j; |
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for (j = 0 ; j < 8 ; j++) { |
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if (i & (1 << j)) break; |
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} |
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movem_index1[i] = j; |
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movem_index2[i] = 7-j; |
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movem_next[i] = i & (~(1 << j)); |
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} |
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for (i = 0 ; i < 256 ; i++) { |
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int j; |
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for (j = 7 ; j >= 0 ; j--) { |
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if (i & (1 << j)) break; |
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} |
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cebix |
1.5 |
fpp_movem_index1[i] = 7-j; |
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fpp_movem_index2[i] = j; |
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cebix |
1.1 |
fpp_movem_next[i] = i & (~(1 << j)); |
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} |
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#if COUNT_INSTRS |
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{ |
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FILE *f = fopen (icountfilename (), "r"); |
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memset (instrcount, 0, sizeof instrcount); |
| 193 |
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if (f) { |
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uae_u32 opcode, count, total; |
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char name[20]; |
| 196 |
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write_log ("Reading instruction count file...\n"); |
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fscanf (f, "Total: %lu\n", &total); |
| 198 |
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while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) { |
| 199 |
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instrcount[opcode] = count; |
| 200 |
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} |
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fclose(f); |
| 202 |
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} |
| 203 |
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} |
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#endif |
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read_table68k (); |
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do_merges (); |
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build_cpufunctbl (); |
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gbeauche |
1.6 |
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| 210 |
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fpu_init (); |
| 211 |
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fpu_set_integral_fpu (CPUType == 4); |
| 212 |
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} |
| 213 |
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| 214 |
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void exit_m68k (void) |
| 215 |
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{ |
| 216 |
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fpu_exit (); |
| 217 |
cebix |
1.1 |
} |
| 218 |
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| 219 |
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struct regstruct regs, lastint_regs; |
| 220 |
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static struct regstruct regs_backup[16]; |
| 221 |
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static int backup_pointer = 0; |
| 222 |
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static long int m68kpc_offset; |
| 223 |
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int lastint_no; |
| 224 |
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| 225 |
gbeauche |
1.7 |
#if REAL_ADDRESSING || DIRECT_ADDRESSING |
| 226 |
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#define get_ibyte_1(o) get_byte(get_virtual_address(regs.pc_p) + (o) + 1) |
| 227 |
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#define get_iword_1(o) get_word(get_virtual_address(regs.pc_p) + (o)) |
| 228 |
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#define get_ilong_1(o) get_long(get_virtual_address(regs.pc_p) + (o)) |
| 229 |
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#else |
| 230 |
cebix |
1.1 |
#define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1) |
| 231 |
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#define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o)) |
| 232 |
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#define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o)) |
| 233 |
gbeauche |
1.7 |
#endif |
| 234 |
cebix |
1.1 |
|
| 235 |
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uae_s32 ShowEA (int reg, amodes mode, wordsizes size, char *buf) |
| 236 |
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{ |
| 237 |
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uae_u16 dp; |
| 238 |
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uae_s8 disp8; |
| 239 |
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uae_s16 disp16; |
| 240 |
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int r; |
| 241 |
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uae_u32 dispreg; |
| 242 |
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uaecptr addr; |
| 243 |
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uae_s32 offset = 0; |
| 244 |
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char buffer[80]; |
| 245 |
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| 246 |
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switch (mode){ |
| 247 |
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case Dreg: |
| 248 |
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sprintf (buffer,"D%d", reg); |
| 249 |
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break; |
| 250 |
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case Areg: |
| 251 |
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sprintf (buffer,"A%d", reg); |
| 252 |
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break; |
| 253 |
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case Aind: |
| 254 |
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sprintf (buffer,"(A%d)", reg); |
| 255 |
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break; |
| 256 |
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case Aipi: |
| 257 |
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sprintf (buffer,"(A%d)+", reg); |
| 258 |
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break; |
| 259 |
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case Apdi: |
| 260 |
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sprintf (buffer,"-(A%d)", reg); |
| 261 |
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break; |
| 262 |
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case Ad16: |
| 263 |
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disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; |
| 264 |
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addr = m68k_areg(regs,reg) + (uae_s16)disp16; |
| 265 |
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sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff, |
| 266 |
cebix |
1.5 |
(unsigned long)addr); |
| 267 |
cebix |
1.1 |
break; |
| 268 |
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case Ad8r: |
| 269 |
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dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; |
| 270 |
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disp8 = dp & 0xFF; |
| 271 |
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r = (dp & 0x7000) >> 12; |
| 272 |
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dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r); |
| 273 |
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if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg); |
| 274 |
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dispreg <<= (dp >> 9) & 3; |
| 275 |
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| 276 |
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if (dp & 0x100) { |
| 277 |
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uae_s32 outer = 0, disp = 0; |
| 278 |
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uae_s32 base = m68k_areg(regs,reg); |
| 279 |
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char name[10]; |
| 280 |
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sprintf (name,"A%d, ",reg); |
| 281 |
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if (dp & 0x80) { base = 0; name[0] = 0; } |
| 282 |
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if (dp & 0x40) dispreg = 0; |
| 283 |
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if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; } |
| 284 |
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if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; } |
| 285 |
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base += disp; |
| 286 |
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| 287 |
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if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; } |
| 288 |
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if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; } |
| 289 |
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| 290 |
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if (!(dp & 4)) base += dispreg; |
| 291 |
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if (dp & 3) base = get_long (base); |
| 292 |
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if (dp & 4) base += dispreg; |
| 293 |
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| 294 |
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addr = base + outer; |
| 295 |
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sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name, |
| 296 |
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dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', |
| 297 |
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1 << ((dp >> 9) & 3), |
| 298 |
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disp,outer, |
| 299 |
cebix |
1.5 |
(unsigned long)addr); |
| 300 |
cebix |
1.1 |
} else { |
| 301 |
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addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg; |
| 302 |
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sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg, |
| 303 |
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dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', |
| 304 |
|
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1 << ((dp >> 9) & 3), disp8, |
| 305 |
cebix |
1.5 |
(unsigned long)addr); |
| 306 |
cebix |
1.1 |
} |
| 307 |
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break; |
| 308 |
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case PC16: |
| 309 |
|
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addr = m68k_getpc () + m68kpc_offset; |
| 310 |
|
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disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; |
| 311 |
|
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addr += (uae_s16)disp16; |
| 312 |
cebix |
1.5 |
sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr); |
| 313 |
cebix |
1.1 |
break; |
| 314 |
|
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case PC8r: |
| 315 |
|
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addr = m68k_getpc () + m68kpc_offset; |
| 316 |
|
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dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; |
| 317 |
|
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disp8 = dp & 0xFF; |
| 318 |
|
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r = (dp & 0x7000) >> 12; |
| 319 |
|
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dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r); |
| 320 |
|
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if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg); |
| 321 |
|
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dispreg <<= (dp >> 9) & 3; |
| 322 |
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| 323 |
|
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if (dp & 0x100) { |
| 324 |
|
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uae_s32 outer = 0,disp = 0; |
| 325 |
|
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uae_s32 base = addr; |
| 326 |
|
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char name[10]; |
| 327 |
|
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sprintf (name,"PC, "); |
| 328 |
|
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if (dp & 0x80) { base = 0; name[0] = 0; } |
| 329 |
|
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if (dp & 0x40) dispreg = 0; |
| 330 |
|
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if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; } |
| 331 |
|
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if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; } |
| 332 |
|
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base += disp; |
| 333 |
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| 334 |
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if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; } |
| 335 |
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if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; } |
| 336 |
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| 337 |
|
|
if (!(dp & 4)) base += dispreg; |
| 338 |
|
|
if (dp & 3) base = get_long (base); |
| 339 |
|
|
if (dp & 4) base += dispreg; |
| 340 |
|
|
|
| 341 |
|
|
addr = base + outer; |
| 342 |
|
|
sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name, |
| 343 |
|
|
dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', |
| 344 |
|
|
1 << ((dp >> 9) & 3), |
| 345 |
|
|
disp,outer, |
| 346 |
cebix |
1.5 |
(unsigned long)addr); |
| 347 |
cebix |
1.1 |
} else { |
| 348 |
|
|
addr += (uae_s32)((uae_s8)disp8) + dispreg; |
| 349 |
|
|
sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D', |
| 350 |
|
|
(int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3), |
| 351 |
cebix |
1.5 |
disp8, (unsigned long)addr); |
| 352 |
cebix |
1.1 |
} |
| 353 |
|
|
break; |
| 354 |
|
|
case absw: |
| 355 |
cebix |
1.5 |
sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset)); |
| 356 |
cebix |
1.1 |
m68kpc_offset += 2; |
| 357 |
|
|
break; |
| 358 |
|
|
case absl: |
| 359 |
cebix |
1.5 |
sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset)); |
| 360 |
cebix |
1.1 |
m68kpc_offset += 4; |
| 361 |
|
|
break; |
| 362 |
|
|
case imm: |
| 363 |
|
|
switch (size){ |
| 364 |
|
|
case sz_byte: |
| 365 |
|
|
sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff)); |
| 366 |
|
|
m68kpc_offset += 2; |
| 367 |
|
|
break; |
| 368 |
|
|
case sz_word: |
| 369 |
|
|
sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff)); |
| 370 |
|
|
m68kpc_offset += 2; |
| 371 |
|
|
break; |
| 372 |
|
|
case sz_long: |
| 373 |
cebix |
1.5 |
sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset))); |
| 374 |
cebix |
1.1 |
m68kpc_offset += 4; |
| 375 |
|
|
break; |
| 376 |
|
|
default: |
| 377 |
|
|
break; |
| 378 |
|
|
} |
| 379 |
|
|
break; |
| 380 |
|
|
case imm0: |
| 381 |
|
|
offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset); |
| 382 |
|
|
m68kpc_offset += 2; |
| 383 |
|
|
sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff)); |
| 384 |
|
|
break; |
| 385 |
|
|
case imm1: |
| 386 |
|
|
offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); |
| 387 |
|
|
m68kpc_offset += 2; |
| 388 |
|
|
sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff)); |
| 389 |
|
|
break; |
| 390 |
|
|
case imm2: |
| 391 |
|
|
offset = (uae_s32)get_ilong_1 (m68kpc_offset); |
| 392 |
|
|
m68kpc_offset += 4; |
| 393 |
cebix |
1.5 |
sprintf (buffer,"#$%08lx", (unsigned long)offset); |
| 394 |
cebix |
1.1 |
break; |
| 395 |
|
|
case immi: |
| 396 |
|
|
offset = (uae_s32)(uae_s8)(reg & 0xff); |
| 397 |
cebix |
1.5 |
sprintf (buffer,"#$%08lx", (unsigned long)offset); |
| 398 |
cebix |
1.1 |
break; |
| 399 |
|
|
default: |
| 400 |
|
|
break; |
| 401 |
|
|
} |
| 402 |
|
|
if (buf == 0) |
| 403 |
|
|
printf ("%s", buffer); |
| 404 |
|
|
else |
| 405 |
|
|
strcat (buf, buffer); |
| 406 |
|
|
return offset; |
| 407 |
|
|
} |
| 408 |
|
|
|
| 409 |
|
|
/* The plan is that this will take over the job of exception 3 handling - |
| 410 |
|
|
* the CPU emulation functions will just do a longjmp to m68k_go whenever |
| 411 |
|
|
* they hit an odd address. */ |
| 412 |
|
|
static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val) |
| 413 |
|
|
{ |
| 414 |
|
|
uae_u16 dp; |
| 415 |
|
|
uae_s8 disp8; |
| 416 |
|
|
uae_s16 disp16; |
| 417 |
|
|
int r; |
| 418 |
|
|
uae_u32 dispreg; |
| 419 |
|
|
uaecptr addr; |
| 420 |
|
|
uae_s32 offset = 0; |
| 421 |
|
|
|
| 422 |
|
|
switch (mode){ |
| 423 |
|
|
case Dreg: |
| 424 |
|
|
*val = m68k_dreg (regs, reg); |
| 425 |
|
|
return 1; |
| 426 |
|
|
case Areg: |
| 427 |
|
|
*val = m68k_areg (regs, reg); |
| 428 |
|
|
return 1; |
| 429 |
|
|
|
| 430 |
|
|
case Aind: |
| 431 |
|
|
case Aipi: |
| 432 |
|
|
addr = m68k_areg (regs, reg); |
| 433 |
|
|
break; |
| 434 |
|
|
case Apdi: |
| 435 |
|
|
addr = m68k_areg (regs, reg); |
| 436 |
|
|
break; |
| 437 |
|
|
case Ad16: |
| 438 |
|
|
disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; |
| 439 |
|
|
addr = m68k_areg(regs,reg) + (uae_s16)disp16; |
| 440 |
|
|
break; |
| 441 |
|
|
case Ad8r: |
| 442 |
|
|
addr = m68k_areg (regs, reg); |
| 443 |
|
|
d8r_common: |
| 444 |
|
|
dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; |
| 445 |
|
|
disp8 = dp & 0xFF; |
| 446 |
|
|
r = (dp & 0x7000) >> 12; |
| 447 |
|
|
dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r); |
| 448 |
|
|
if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg); |
| 449 |
|
|
dispreg <<= (dp >> 9) & 3; |
| 450 |
|
|
|
| 451 |
|
|
if (dp & 0x100) { |
| 452 |
|
|
uae_s32 outer = 0, disp = 0; |
| 453 |
|
|
uae_s32 base = addr; |
| 454 |
|
|
if (dp & 0x80) base = 0; |
| 455 |
|
|
if (dp & 0x40) dispreg = 0; |
| 456 |
|
|
if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; } |
| 457 |
|
|
if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; } |
| 458 |
|
|
base += disp; |
| 459 |
|
|
|
| 460 |
|
|
if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; } |
| 461 |
|
|
if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; } |
| 462 |
|
|
|
| 463 |
|
|
if (!(dp & 4)) base += dispreg; |
| 464 |
|
|
if (dp & 3) base = get_long (base); |
| 465 |
|
|
if (dp & 4) base += dispreg; |
| 466 |
|
|
|
| 467 |
|
|
addr = base + outer; |
| 468 |
|
|
} else { |
| 469 |
|
|
addr += (uae_s32)((uae_s8)disp8) + dispreg; |
| 470 |
|
|
} |
| 471 |
|
|
break; |
| 472 |
|
|
case PC16: |
| 473 |
|
|
addr = m68k_getpc () + m68kpc_offset; |
| 474 |
|
|
disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; |
| 475 |
|
|
addr += (uae_s16)disp16; |
| 476 |
|
|
break; |
| 477 |
|
|
case PC8r: |
| 478 |
|
|
addr = m68k_getpc () + m68kpc_offset; |
| 479 |
|
|
goto d8r_common; |
| 480 |
|
|
case absw: |
| 481 |
|
|
addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); |
| 482 |
|
|
m68kpc_offset += 2; |
| 483 |
|
|
break; |
| 484 |
|
|
case absl: |
| 485 |
|
|
addr = get_ilong_1 (m68kpc_offset); |
| 486 |
|
|
m68kpc_offset += 4; |
| 487 |
|
|
break; |
| 488 |
|
|
case imm: |
| 489 |
|
|
switch (size){ |
| 490 |
|
|
case sz_byte: |
| 491 |
|
|
*val = get_iword_1 (m68kpc_offset) & 0xff; |
| 492 |
|
|
m68kpc_offset += 2; |
| 493 |
|
|
break; |
| 494 |
|
|
case sz_word: |
| 495 |
|
|
*val = get_iword_1 (m68kpc_offset) & 0xffff; |
| 496 |
|
|
m68kpc_offset += 2; |
| 497 |
|
|
break; |
| 498 |
|
|
case sz_long: |
| 499 |
|
|
*val = get_ilong_1 (m68kpc_offset); |
| 500 |
|
|
m68kpc_offset += 4; |
| 501 |
|
|
break; |
| 502 |
|
|
default: |
| 503 |
|
|
break; |
| 504 |
|
|
} |
| 505 |
|
|
return 1; |
| 506 |
|
|
case imm0: |
| 507 |
|
|
*val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset); |
| 508 |
|
|
m68kpc_offset += 2; |
| 509 |
|
|
return 1; |
| 510 |
|
|
case imm1: |
| 511 |
|
|
*val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); |
| 512 |
|
|
m68kpc_offset += 2; |
| 513 |
|
|
return 1; |
| 514 |
|
|
case imm2: |
| 515 |
|
|
*val = get_ilong_1 (m68kpc_offset); |
| 516 |
|
|
m68kpc_offset += 4; |
| 517 |
|
|
return 1; |
| 518 |
|
|
case immi: |
| 519 |
|
|
*val = (uae_s32)(uae_s8)(reg & 0xff); |
| 520 |
|
|
return 1; |
| 521 |
|
|
default: |
| 522 |
|
|
addr = 0; |
| 523 |
|
|
break; |
| 524 |
|
|
} |
| 525 |
|
|
if ((addr & 1) == 0) |
| 526 |
|
|
return 1; |
| 527 |
|
|
|
| 528 |
|
|
last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset; |
| 529 |
|
|
last_fault_for_exception_3 = addr; |
| 530 |
|
|
return 0; |
| 531 |
|
|
} |
| 532 |
|
|
|
| 533 |
|
|
uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp) |
| 534 |
|
|
{ |
| 535 |
|
|
int reg = (dp >> 12) & 15; |
| 536 |
|
|
uae_s32 regd = regs.regs[reg]; |
| 537 |
|
|
if ((dp & 0x800) == 0) |
| 538 |
|
|
regd = (uae_s32)(uae_s16)regd; |
| 539 |
|
|
regd <<= (dp >> 9) & 3; |
| 540 |
|
|
if (dp & 0x100) { |
| 541 |
|
|
uae_s32 outer = 0; |
| 542 |
|
|
if (dp & 0x80) base = 0; |
| 543 |
|
|
if (dp & 0x40) regd = 0; |
| 544 |
|
|
|
| 545 |
|
|
if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword(); |
| 546 |
|
|
if ((dp & 0x30) == 0x30) base += next_ilong(); |
| 547 |
|
|
|
| 548 |
|
|
if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword(); |
| 549 |
|
|
if ((dp & 0x3) == 0x3) outer = next_ilong(); |
| 550 |
|
|
|
| 551 |
|
|
if ((dp & 0x4) == 0) base += regd; |
| 552 |
|
|
if (dp & 0x3) base = get_long (base); |
| 553 |
|
|
if (dp & 0x4) base += regd; |
| 554 |
|
|
|
| 555 |
|
|
return base + outer; |
| 556 |
|
|
} else { |
| 557 |
|
|
return base + (uae_s32)((uae_s8)dp) + regd; |
| 558 |
|
|
} |
| 559 |
|
|
} |
| 560 |
|
|
|
| 561 |
|
|
uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp) |
| 562 |
|
|
{ |
| 563 |
|
|
int reg = (dp >> 12) & 15; |
| 564 |
|
|
uae_s32 regd = regs.regs[reg]; |
| 565 |
|
|
#if 1 |
| 566 |
|
|
if ((dp & 0x800) == 0) |
| 567 |
|
|
regd = (uae_s32)(uae_s16)regd; |
| 568 |
|
|
return base + (uae_s8)dp + regd; |
| 569 |
|
|
#else |
| 570 |
|
|
/* Branch-free code... benchmark this again now that |
| 571 |
|
|
* things are no longer inline. */ |
| 572 |
|
|
uae_s32 regd16; |
| 573 |
|
|
uae_u32 mask; |
| 574 |
|
|
mask = ((dp & 0x800) >> 11) - 1; |
| 575 |
|
|
regd16 = (uae_s32)(uae_s16)regd; |
| 576 |
|
|
regd16 &= mask; |
| 577 |
|
|
mask = ~mask; |
| 578 |
|
|
base += (uae_s8)dp; |
| 579 |
|
|
regd &= mask; |
| 580 |
|
|
regd |= regd16; |
| 581 |
|
|
return base + regd; |
| 582 |
|
|
#endif |
| 583 |
|
|
} |
| 584 |
|
|
|
| 585 |
|
|
void MakeSR (void) |
| 586 |
|
|
{ |
| 587 |
|
|
#if 0 |
| 588 |
|
|
assert((regs.t1 & 1) == regs.t1); |
| 589 |
|
|
assert((regs.t0 & 1) == regs.t0); |
| 590 |
|
|
assert((regs.s & 1) == regs.s); |
| 591 |
|
|
assert((regs.m & 1) == regs.m); |
| 592 |
|
|
assert((XFLG & 1) == XFLG); |
| 593 |
|
|
assert((NFLG & 1) == NFLG); |
| 594 |
|
|
assert((ZFLG & 1) == ZFLG); |
| 595 |
|
|
assert((VFLG & 1) == VFLG); |
| 596 |
|
|
assert((CFLG & 1) == CFLG); |
| 597 |
|
|
#endif |
| 598 |
|
|
regs.sr = ((regs.t1 << 15) | (regs.t0 << 14) |
| 599 |
|
|
| (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8) |
| 600 |
|
|
| (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1) |
| 601 |
|
|
| GET_CFLG); |
| 602 |
|
|
} |
| 603 |
|
|
|
| 604 |
|
|
void MakeFromSR (void) |
| 605 |
|
|
{ |
| 606 |
|
|
int oldm = regs.m; |
| 607 |
|
|
int olds = regs.s; |
| 608 |
|
|
|
| 609 |
|
|
regs.t1 = (regs.sr >> 15) & 1; |
| 610 |
|
|
regs.t0 = (regs.sr >> 14) & 1; |
| 611 |
|
|
regs.s = (regs.sr >> 13) & 1; |
| 612 |
|
|
regs.m = (regs.sr >> 12) & 1; |
| 613 |
|
|
regs.intmask = (regs.sr >> 8) & 7; |
| 614 |
|
|
SET_XFLG ((regs.sr >> 4) & 1); |
| 615 |
|
|
SET_NFLG ((regs.sr >> 3) & 1); |
| 616 |
|
|
SET_ZFLG ((regs.sr >> 2) & 1); |
| 617 |
|
|
SET_VFLG ((regs.sr >> 1) & 1); |
| 618 |
|
|
SET_CFLG (regs.sr & 1); |
| 619 |
|
|
if (CPUType >= 2) { |
| 620 |
|
|
if (olds != regs.s) { |
| 621 |
|
|
if (olds) { |
| 622 |
|
|
if (oldm) |
| 623 |
|
|
regs.msp = m68k_areg(regs, 7); |
| 624 |
|
|
else |
| 625 |
|
|
regs.isp = m68k_areg(regs, 7); |
| 626 |
|
|
m68k_areg(regs, 7) = regs.usp; |
| 627 |
|
|
} else { |
| 628 |
|
|
regs.usp = m68k_areg(regs, 7); |
| 629 |
|
|
m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp; |
| 630 |
|
|
} |
| 631 |
|
|
} else if (olds && oldm != regs.m) { |
| 632 |
|
|
if (oldm) { |
| 633 |
|
|
regs.msp = m68k_areg(regs, 7); |
| 634 |
|
|
m68k_areg(regs, 7) = regs.isp; |
| 635 |
|
|
} else { |
| 636 |
|
|
regs.isp = m68k_areg(regs, 7); |
| 637 |
|
|
m68k_areg(regs, 7) = regs.msp; |
| 638 |
|
|
} |
| 639 |
|
|
} |
| 640 |
|
|
} else { |
| 641 |
|
|
if (olds != regs.s) { |
| 642 |
|
|
if (olds) { |
| 643 |
|
|
regs.isp = m68k_areg(regs, 7); |
| 644 |
|
|
m68k_areg(regs, 7) = regs.usp; |
| 645 |
|
|
} else { |
| 646 |
|
|
regs.usp = m68k_areg(regs, 7); |
| 647 |
|
|
m68k_areg(regs, 7) = regs.isp; |
| 648 |
|
|
} |
| 649 |
|
|
} |
| 650 |
|
|
} |
| 651 |
|
|
|
| 652 |
|
|
regs.spcflags |= SPCFLAG_INT; |
| 653 |
|
|
if (regs.t1 || regs.t0) |
| 654 |
|
|
regs.spcflags |= SPCFLAG_TRACE; |
| 655 |
|
|
else |
| 656 |
|
|
regs.spcflags &= ~(SPCFLAG_TRACE | SPCFLAG_DOTRACE); |
| 657 |
|
|
} |
| 658 |
|
|
|
| 659 |
|
|
void Exception(int nr, uaecptr oldpc) |
| 660 |
|
|
{ |
| 661 |
|
|
MakeSR(); |
| 662 |
|
|
if (!regs.s) { |
| 663 |
|
|
regs.usp = m68k_areg(regs, 7); |
| 664 |
|
|
if (CPUType >= 2) |
| 665 |
|
|
m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp; |
| 666 |
|
|
else |
| 667 |
|
|
m68k_areg(regs, 7) = regs.isp; |
| 668 |
|
|
regs.s = 1; |
| 669 |
|
|
} |
| 670 |
|
|
if (CPUType > 0) { |
| 671 |
|
|
if (nr == 2 || nr == 3) { |
| 672 |
|
|
int i; |
| 673 |
|
|
/* @@@ this is probably wrong (?) */ |
| 674 |
|
|
for (i = 0 ; i < 12 ; i++) { |
| 675 |
|
|
m68k_areg(regs, 7) -= 2; |
| 676 |
|
|
put_word (m68k_areg(regs, 7), 0); |
| 677 |
|
|
} |
| 678 |
|
|
m68k_areg(regs, 7) -= 2; |
| 679 |
|
|
put_word (m68k_areg(regs, 7), 0xa000 + nr * 4); |
| 680 |
|
|
} else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) { |
| 681 |
|
|
m68k_areg(regs, 7) -= 4; |
| 682 |
|
|
put_long (m68k_areg(regs, 7), oldpc); |
| 683 |
|
|
m68k_areg(regs, 7) -= 2; |
| 684 |
|
|
put_word (m68k_areg(regs, 7), 0x2000 + nr * 4); |
| 685 |
|
|
} else if (regs.m && nr >= 24 && nr < 32) { |
| 686 |
|
|
m68k_areg(regs, 7) -= 2; |
| 687 |
|
|
put_word (m68k_areg(regs, 7), nr * 4); |
| 688 |
|
|
m68k_areg(regs, 7) -= 4; |
| 689 |
|
|
put_long (m68k_areg(regs, 7), m68k_getpc ()); |
| 690 |
|
|
m68k_areg(regs, 7) -= 2; |
| 691 |
|
|
put_word (m68k_areg(regs, 7), regs.sr); |
| 692 |
|
|
regs.sr |= (1 << 13); |
| 693 |
|
|
regs.msp = m68k_areg(regs, 7); |
| 694 |
|
|
m68k_areg(regs, 7) = regs.isp; |
| 695 |
|
|
m68k_areg(regs, 7) -= 2; |
| 696 |
|
|
put_word (m68k_areg(regs, 7), 0x1000 + nr * 4); |
| 697 |
|
|
} else { |
| 698 |
|
|
m68k_areg(regs, 7) -= 2; |
| 699 |
|
|
put_word (m68k_areg(regs, 7), nr * 4); |
| 700 |
|
|
} |
| 701 |
|
|
} else { |
| 702 |
|
|
if (nr == 2 || nr == 3) { |
| 703 |
|
|
m68k_areg(regs, 7) -= 12; |
| 704 |
|
|
/* ??????? */ |
| 705 |
|
|
if (nr == 3) { |
| 706 |
|
|
put_long (m68k_areg(regs, 7), last_fault_for_exception_3); |
| 707 |
|
|
put_word (m68k_areg(regs, 7)+4, last_op_for_exception_3); |
| 708 |
|
|
put_long (m68k_areg(regs, 7)+8, last_addr_for_exception_3); |
| 709 |
|
|
} |
| 710 |
|
|
write_log ("Exception!\n"); |
| 711 |
|
|
goto kludge_me_do; |
| 712 |
|
|
} |
| 713 |
|
|
} |
| 714 |
|
|
m68k_areg(regs, 7) -= 4; |
| 715 |
|
|
put_long (m68k_areg(regs, 7), m68k_getpc ()); |
| 716 |
|
|
kludge_me_do: |
| 717 |
|
|
m68k_areg(regs, 7) -= 2; |
| 718 |
|
|
put_word (m68k_areg(regs, 7), regs.sr); |
| 719 |
|
|
m68k_setpc (get_long (regs.vbr + 4*nr)); |
| 720 |
|
|
fill_prefetch_0 (); |
| 721 |
|
|
regs.t1 = regs.t0 = regs.m = 0; |
| 722 |
|
|
regs.spcflags &= ~(SPCFLAG_TRACE | SPCFLAG_DOTRACE); |
| 723 |
|
|
} |
| 724 |
|
|
|
| 725 |
|
|
static void Interrupt(int nr) |
| 726 |
|
|
{ |
| 727 |
|
|
assert(nr < 8 && nr >= 0); |
| 728 |
|
|
lastint_regs = regs; |
| 729 |
|
|
lastint_no = nr; |
| 730 |
|
|
Exception(nr+24, 0); |
| 731 |
|
|
|
| 732 |
|
|
regs.intmask = nr; |
| 733 |
|
|
regs.spcflags |= SPCFLAG_INT; |
| 734 |
|
|
} |
| 735 |
|
|
|
| 736 |
cebix |
1.2 |
static int caar, cacr, tc, itt0, itt1, dtt0, dtt1; |
| 737 |
cebix |
1.1 |
|
| 738 |
|
|
void m68k_move2c (int regno, uae_u32 *regp) |
| 739 |
|
|
{ |
| 740 |
|
|
if (CPUType == 1 && (regno & 0x7FF) > 1) |
| 741 |
|
|
op_illg (0x4E7B); |
| 742 |
|
|
else |
| 743 |
|
|
switch (regno) { |
| 744 |
|
|
case 0: regs.sfc = *regp & 7; break; |
| 745 |
|
|
case 1: regs.dfc = *regp & 7; break; |
| 746 |
|
|
case 2: cacr = *regp & 0x3; break; /* ignore C and CE */ |
| 747 |
cebix |
1.2 |
case 3: tc = *regp & 0xc000; break; |
| 748 |
|
|
case 4: itt0 = *regp & 0xffffe364; break; |
| 749 |
|
|
case 5: itt1 = *regp & 0xffffe364; break; |
| 750 |
|
|
case 6: dtt0 = *regp & 0xffffe364; break; |
| 751 |
|
|
case 7: dtt1 = *regp & 0xffffe364; break; |
| 752 |
cebix |
1.1 |
case 0x800: regs.usp = *regp; break; |
| 753 |
|
|
case 0x801: regs.vbr = *regp; break; |
| 754 |
|
|
case 0x802: caar = *regp &0xfc; break; |
| 755 |
|
|
case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break; |
| 756 |
|
|
case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break; |
| 757 |
|
|
default: |
| 758 |
|
|
op_illg (0x4E7B); |
| 759 |
|
|
break; |
| 760 |
|
|
} |
| 761 |
|
|
} |
| 762 |
|
|
|
| 763 |
|
|
void m68k_movec2 (int regno, uae_u32 *regp) |
| 764 |
|
|
{ |
| 765 |
|
|
if (CPUType == 1 && (regno & 0x7FF) > 1) |
| 766 |
|
|
op_illg (0x4E7A); |
| 767 |
|
|
else |
| 768 |
|
|
switch (regno) { |
| 769 |
|
|
case 0: *regp = regs.sfc; break; |
| 770 |
|
|
case 1: *regp = regs.dfc; break; |
| 771 |
|
|
case 2: *regp = cacr; break; |
| 772 |
cebix |
1.2 |
case 3: *regp = tc; break; |
| 773 |
|
|
case 4: *regp = itt0; break; |
| 774 |
|
|
case 5: *regp = itt1; break; |
| 775 |
|
|
case 6: *regp = dtt0; break; |
| 776 |
|
|
case 7: *regp = dtt1; break; |
| 777 |
cebix |
1.1 |
case 0x800: *regp = regs.usp; break; |
| 778 |
|
|
case 0x801: *regp = regs.vbr; break; |
| 779 |
|
|
case 0x802: *regp = caar; break; |
| 780 |
|
|
case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break; |
| 781 |
|
|
case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break; |
| 782 |
|
|
default: |
| 783 |
|
|
op_illg (0x4E7A); |
| 784 |
|
|
break; |
| 785 |
|
|
} |
| 786 |
|
|
} |
| 787 |
|
|
|
| 788 |
|
|
static __inline__ int |
| 789 |
|
|
div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 div, uae_u32 *quot, uae_u32 *rem) |
| 790 |
|
|
{ |
| 791 |
|
|
uae_u32 q = 0, cbit = 0; |
| 792 |
|
|
int i; |
| 793 |
|
|
|
| 794 |
|
|
if (div <= src_hi) { |
| 795 |
|
|
return 1; |
| 796 |
|
|
} |
| 797 |
|
|
for (i = 0 ; i < 32 ; i++) { |
| 798 |
|
|
cbit = src_hi & 0x80000000ul; |
| 799 |
|
|
src_hi <<= 1; |
| 800 |
|
|
if (src_lo & 0x80000000ul) src_hi++; |
| 801 |
|
|
src_lo <<= 1; |
| 802 |
|
|
q = q << 1; |
| 803 |
|
|
if (cbit || div <= src_hi) { |
| 804 |
|
|
q |= 1; |
| 805 |
|
|
src_hi -= div; |
| 806 |
|
|
} |
| 807 |
|
|
} |
| 808 |
|
|
*quot = q; |
| 809 |
|
|
*rem = src_hi; |
| 810 |
|
|
return 0; |
| 811 |
|
|
} |
| 812 |
|
|
|
| 813 |
|
|
void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc) |
| 814 |
|
|
{ |
| 815 |
|
|
#if defined(uae_s64) |
| 816 |
|
|
if (src == 0) { |
| 817 |
|
|
Exception (5, oldpc); |
| 818 |
|
|
return; |
| 819 |
|
|
} |
| 820 |
|
|
if (extra & 0x800) { |
| 821 |
|
|
/* signed variant */ |
| 822 |
|
|
uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7); |
| 823 |
|
|
uae_s64 quot, rem; |
| 824 |
|
|
|
| 825 |
|
|
if (extra & 0x400) { |
| 826 |
|
|
a &= 0xffffffffu; |
| 827 |
|
|
a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32; |
| 828 |
|
|
} |
| 829 |
|
|
rem = a % (uae_s64)(uae_s32)src; |
| 830 |
|
|
quot = a / (uae_s64)(uae_s32)src; |
| 831 |
|
|
if ((quot & UVAL64(0xffffffff80000000)) != 0 |
| 832 |
|
|
&& (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000)) |
| 833 |
|
|
{ |
| 834 |
|
|
SET_VFLG (1); |
| 835 |
|
|
SET_NFLG (1); |
| 836 |
|
|
SET_CFLG (0); |
| 837 |
|
|
} else { |
| 838 |
|
|
if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem; |
| 839 |
|
|
SET_VFLG (0); |
| 840 |
|
|
SET_CFLG (0); |
| 841 |
|
|
SET_ZFLG (((uae_s32)quot) == 0); |
| 842 |
|
|
SET_NFLG (((uae_s32)quot) < 0); |
| 843 |
|
|
m68k_dreg(regs, extra & 7) = rem; |
| 844 |
|
|
m68k_dreg(regs, (extra >> 12) & 7) = quot; |
| 845 |
|
|
} |
| 846 |
|
|
} else { |
| 847 |
|
|
/* unsigned */ |
| 848 |
|
|
uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7); |
| 849 |
|
|
uae_u64 quot, rem; |
| 850 |
|
|
|
| 851 |
|
|
if (extra & 0x400) { |
| 852 |
|
|
a &= 0xffffffffu; |
| 853 |
|
|
a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32; |
| 854 |
|
|
} |
| 855 |
|
|
rem = a % (uae_u64)src; |
| 856 |
|
|
quot = a / (uae_u64)src; |
| 857 |
|
|
if (quot > 0xffffffffu) { |
| 858 |
|
|
SET_VFLG (1); |
| 859 |
|
|
SET_NFLG (1); |
| 860 |
|
|
SET_CFLG (0); |
| 861 |
|
|
} else { |
| 862 |
|
|
SET_VFLG (0); |
| 863 |
|
|
SET_CFLG (0); |
| 864 |
|
|
SET_ZFLG (((uae_s32)quot) == 0); |
| 865 |
|
|
SET_NFLG (((uae_s32)quot) < 0); |
| 866 |
|
|
m68k_dreg(regs, extra & 7) = rem; |
| 867 |
|
|
m68k_dreg(regs, (extra >> 12) & 7) = quot; |
| 868 |
|
|
} |
| 869 |
|
|
} |
| 870 |
|
|
#else |
| 871 |
|
|
if (src == 0) { |
| 872 |
|
|
Exception (5, oldpc); |
| 873 |
|
|
return; |
| 874 |
|
|
} |
| 875 |
|
|
if (extra & 0x800) { |
| 876 |
|
|
/* signed variant */ |
| 877 |
|
|
uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7); |
| 878 |
|
|
uae_s32 hi = lo < 0 ? -1 : 0; |
| 879 |
|
|
uae_s32 save_high; |
| 880 |
|
|
uae_u32 quot, rem; |
| 881 |
|
|
uae_u32 sign; |
| 882 |
|
|
|
| 883 |
|
|
if (extra & 0x400) { |
| 884 |
|
|
hi = (uae_s32)m68k_dreg(regs, extra & 7); |
| 885 |
|
|
} |
| 886 |
|
|
save_high = hi; |
| 887 |
|
|
sign = (hi ^ src); |
| 888 |
|
|
if (hi < 0) { |
| 889 |
|
|
hi = ~hi; |
| 890 |
|
|
lo = -lo; |
| 891 |
|
|
if (lo == 0) hi++; |
| 892 |
|
|
} |
| 893 |
|
|
if ((uae_s32)src < 0) src = -src; |
| 894 |
|
|
if (div_unsigned(hi, lo, src, ", &rem) || |
| 895 |
|
|
(sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) { |
| 896 |
|
|
SET_VFLG (1); |
| 897 |
|
|
SET_NFLG (1); |
| 898 |
|
|
SET_CFLG (0); |
| 899 |
|
|
} else { |
| 900 |
|
|
if (sign & 0x80000000) quot = -quot; |
| 901 |
|
|
if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem; |
| 902 |
|
|
SET_VFLG (0); |
| 903 |
|
|
SET_CFLG (0); |
| 904 |
|
|
SET_ZFLG (((uae_s32)quot) == 0); |
| 905 |
|
|
SET_NFLG (((uae_s32)quot) < 0); |
| 906 |
|
|
m68k_dreg(regs, extra & 7) = rem; |
| 907 |
|
|
m68k_dreg(regs, (extra >> 12) & 7) = quot; |
| 908 |
|
|
} |
| 909 |
|
|
} else { |
| 910 |
|
|
/* unsigned */ |
| 911 |
|
|
uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7); |
| 912 |
|
|
uae_u32 hi = 0; |
| 913 |
|
|
uae_u32 quot, rem; |
| 914 |
|
|
|
| 915 |
|
|
if (extra & 0x400) { |
| 916 |
|
|
hi = (uae_u32)m68k_dreg(regs, extra & 7); |
| 917 |
|
|
} |
| 918 |
|
|
if (div_unsigned(hi, lo, src, ", &rem)) { |
| 919 |
|
|
SET_VFLG (1); |
| 920 |
|
|
SET_NFLG (1); |
| 921 |
|
|
SET_CFLG (0); |
| 922 |
|
|
} else { |
| 923 |
|
|
SET_VFLG (0); |
| 924 |
|
|
SET_CFLG (0); |
| 925 |
|
|
SET_ZFLG (((uae_s32)quot) == 0); |
| 926 |
|
|
SET_NFLG (((uae_s32)quot) < 0); |
| 927 |
|
|
m68k_dreg(regs, extra & 7) = rem; |
| 928 |
|
|
m68k_dreg(regs, (extra >> 12) & 7) = quot; |
| 929 |
|
|
} |
| 930 |
|
|
} |
| 931 |
|
|
#endif |
| 932 |
|
|
} |
| 933 |
|
|
|
| 934 |
|
|
static __inline__ void |
| 935 |
|
|
mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo) |
| 936 |
|
|
{ |
| 937 |
|
|
uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff); |
| 938 |
|
|
uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff); |
| 939 |
|
|
uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff); |
| 940 |
|
|
uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff); |
| 941 |
|
|
uae_u32 lo; |
| 942 |
|
|
|
| 943 |
|
|
lo = r0 + ((r1 << 16) & 0xffff0000ul); |
| 944 |
|
|
if (lo < r0) r3++; |
| 945 |
|
|
r0 = lo; |
| 946 |
|
|
lo = r0 + ((r2 << 16) & 0xffff0000ul); |
| 947 |
|
|
if (lo < r0) r3++; |
| 948 |
|
|
r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff); |
| 949 |
|
|
*dst_lo = lo; |
| 950 |
|
|
*dst_hi = r3; |
| 951 |
|
|
} |
| 952 |
|
|
|
| 953 |
|
|
void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra) |
| 954 |
|
|
{ |
| 955 |
|
|
#if defined(uae_s64) |
| 956 |
|
|
if (extra & 0x800) { |
| 957 |
|
|
/* signed variant */ |
| 958 |
|
|
uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7); |
| 959 |
|
|
|
| 960 |
|
|
a *= (uae_s64)(uae_s32)src; |
| 961 |
|
|
SET_VFLG (0); |
| 962 |
|
|
SET_CFLG (0); |
| 963 |
|
|
SET_ZFLG (a == 0); |
| 964 |
|
|
SET_NFLG (a < 0); |
| 965 |
|
|
if (extra & 0x400) |
| 966 |
|
|
m68k_dreg(regs, extra & 7) = a >> 32; |
| 967 |
|
|
else if ((a & UVAL64(0xffffffff80000000)) != 0 |
| 968 |
|
|
&& (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000)) |
| 969 |
|
|
{ |
| 970 |
|
|
SET_VFLG (1); |
| 971 |
|
|
} |
| 972 |
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a; |
| 973 |
|
|
} else { |
| 974 |
|
|
/* unsigned */ |
| 975 |
|
|
uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7); |
| 976 |
|
|
|
| 977 |
|
|
a *= (uae_u64)src; |
| 978 |
|
|
SET_VFLG (0); |
| 979 |
|
|
SET_CFLG (0); |
| 980 |
|
|
SET_ZFLG (a == 0); |
| 981 |
|
|
SET_NFLG (((uae_s64)a) < 0); |
| 982 |
|
|
if (extra & 0x400) |
| 983 |
|
|
m68k_dreg(regs, extra & 7) = a >> 32; |
| 984 |
|
|
else if ((a & UVAL64(0xffffffff00000000)) != 0) { |
| 985 |
|
|
SET_VFLG (1); |
| 986 |
|
|
} |
| 987 |
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a; |
| 988 |
|
|
} |
| 989 |
|
|
#else |
| 990 |
|
|
if (extra & 0x800) { |
| 991 |
|
|
/* signed variant */ |
| 992 |
|
|
uae_s32 src1,src2; |
| 993 |
|
|
uae_u32 dst_lo,dst_hi; |
| 994 |
|
|
uae_u32 sign; |
| 995 |
|
|
|
| 996 |
|
|
src1 = (uae_s32)src; |
| 997 |
|
|
src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7); |
| 998 |
|
|
sign = (src1 ^ src2); |
| 999 |
|
|
if (src1 < 0) src1 = -src1; |
| 1000 |
|
|
if (src2 < 0) src2 = -src2; |
| 1001 |
|
|
mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo); |
| 1002 |
|
|
if (sign & 0x80000000) { |
| 1003 |
|
|
dst_hi = ~dst_hi; |
| 1004 |
|
|
dst_lo = -dst_lo; |
| 1005 |
|
|
if (dst_lo == 0) dst_hi++; |
| 1006 |
|
|
} |
| 1007 |
|
|
SET_VFLG (0); |
| 1008 |
|
|
SET_CFLG (0); |
| 1009 |
|
|
SET_ZFLG (dst_hi == 0 && dst_lo == 0); |
| 1010 |
|
|
SET_NFLG (((uae_s32)dst_hi) < 0); |
| 1011 |
|
|
if (extra & 0x400) |
| 1012 |
|
|
m68k_dreg(regs, extra & 7) = dst_hi; |
| 1013 |
|
|
else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0) |
| 1014 |
|
|
&& ((dst_hi & 0xffffffff) != 0xffffffff |
| 1015 |
|
|
|| (dst_lo & 0x80000000) != 0x80000000)) |
| 1016 |
|
|
{ |
| 1017 |
|
|
SET_VFLG (1); |
| 1018 |
|
|
} |
| 1019 |
|
|
m68k_dreg(regs, (extra >> 12) & 7) = dst_lo; |
| 1020 |
|
|
} else { |
| 1021 |
|
|
/* unsigned */ |
| 1022 |
|
|
uae_u32 dst_lo,dst_hi; |
| 1023 |
|
|
|
| 1024 |
|
|
mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo); |
| 1025 |
|
|
|
| 1026 |
|
|
SET_VFLG (0); |
| 1027 |
|
|
SET_CFLG (0); |
| 1028 |
|
|
SET_ZFLG (dst_hi == 0 && dst_lo == 0); |
| 1029 |
|
|
SET_NFLG (((uae_s32)dst_hi) < 0); |
| 1030 |
|
|
if (extra & 0x400) |
| 1031 |
|
|
m68k_dreg(regs, extra & 7) = dst_hi; |
| 1032 |
|
|
else if (dst_hi != 0) { |
| 1033 |
|
|
SET_VFLG (1); |
| 1034 |
|
|
} |
| 1035 |
|
|
m68k_dreg(regs, (extra >> 12) & 7) = dst_lo; |
| 1036 |
|
|
} |
| 1037 |
|
|
#endif |
| 1038 |
|
|
} |
| 1039 |
|
|
static char* ccnames[] = |
| 1040 |
|
|
{ "T ","F ","HI","LS","CC","CS","NE","EQ", |
| 1041 |
|
|
"VC","VS","PL","MI","GE","LT","GT","LE" }; |
| 1042 |
|
|
|
| 1043 |
|
|
void m68k_reset (void) |
| 1044 |
|
|
{ |
| 1045 |
|
|
m68k_areg (regs, 7) = 0x2000; |
| 1046 |
|
|
m68k_setpc (ROMBaseMac + 0x2a); |
| 1047 |
|
|
fill_prefetch_0 (); |
| 1048 |
|
|
regs.kick_mask = 0xF80000; |
| 1049 |
|
|
regs.s = 1; |
| 1050 |
|
|
regs.m = 0; |
| 1051 |
|
|
regs.stopped = 0; |
| 1052 |
|
|
regs.t1 = 0; |
| 1053 |
|
|
regs.t0 = 0; |
| 1054 |
|
|
SET_ZFLG (0); |
| 1055 |
|
|
SET_XFLG (0); |
| 1056 |
|
|
SET_CFLG (0); |
| 1057 |
|
|
SET_VFLG (0); |
| 1058 |
|
|
SET_NFLG (0); |
| 1059 |
|
|
regs.spcflags = 0; |
| 1060 |
|
|
regs.intmask = 7; |
| 1061 |
|
|
regs.vbr = regs.sfc = regs.dfc = 0; |
| 1062 |
gbeauche |
1.6 |
/* gb-- moved into {fpp,fpu_x86}.cpp::fpu_init() |
| 1063 |
|
|
regs.fpcr = regs.fpsr = regs.fpiar = 0; */ |
| 1064 |
|
|
fpu_reset(); |
| 1065 |
cebix |
1.1 |
} |
| 1066 |
|
|
|
| 1067 |
cebix |
1.4 |
void REGPARAM2 op_illg (uae_u32 opcode) |
| 1068 |
cebix |
1.1 |
{ |
| 1069 |
|
|
uaecptr pc = m68k_getpc (); |
| 1070 |
|
|
|
| 1071 |
|
|
if ((opcode & 0xFF00) == 0x7100) { |
| 1072 |
|
|
struct M68kRegisters r; |
| 1073 |
|
|
int i; |
| 1074 |
|
|
|
| 1075 |
|
|
// Return from Execute68k()? |
| 1076 |
|
|
if (opcode == M68K_EXEC_RETURN) { |
| 1077 |
|
|
regs.spcflags |= SPCFLAG_BRK; |
| 1078 |
|
|
quit_program = 1; |
| 1079 |
cebix |
1.4 |
return; |
| 1080 |
cebix |
1.1 |
} |
| 1081 |
|
|
|
| 1082 |
|
|
// Call EMUL_OP opcode |
| 1083 |
|
|
for (i=0; i<8; i++) { |
| 1084 |
|
|
r.d[i] = m68k_dreg(regs, i); |
| 1085 |
|
|
r.a[i] = m68k_areg(regs, i); |
| 1086 |
|
|
} |
| 1087 |
|
|
MakeSR(); |
| 1088 |
|
|
r.sr = regs.sr; |
| 1089 |
|
|
EmulOp(opcode, &r); |
| 1090 |
|
|
for (i=0; i<8; i++) { |
| 1091 |
|
|
m68k_dreg(regs, i) = r.d[i]; |
| 1092 |
|
|
m68k_areg(regs, i) = r.a[i]; |
| 1093 |
|
|
} |
| 1094 |
|
|
regs.sr = r.sr; |
| 1095 |
|
|
MakeFromSR(); |
| 1096 |
|
|
m68k_incpc(2); |
| 1097 |
|
|
fill_prefetch_0 (); |
| 1098 |
cebix |
1.4 |
return; |
| 1099 |
cebix |
1.1 |
} |
| 1100 |
|
|
|
| 1101 |
|
|
if ((opcode & 0xF000) == 0xA000) { |
| 1102 |
|
|
Exception(0xA,0); |
| 1103 |
cebix |
1.4 |
return; |
| 1104 |
cebix |
1.1 |
} |
| 1105 |
|
|
|
| 1106 |
cebix |
1.4 |
// write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc); |
| 1107 |
cebix |
1.3 |
|
| 1108 |
cebix |
1.1 |
if ((opcode & 0xF000) == 0xF000) { |
| 1109 |
|
|
Exception(0xB,0); |
| 1110 |
cebix |
1.4 |
return; |
| 1111 |
cebix |
1.1 |
} |
| 1112 |
|
|
|
| 1113 |
cebix |
1.4 |
write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc); |
| 1114 |
|
|
|
| 1115 |
cebix |
1.1 |
Exception (4,0); |
| 1116 |
|
|
} |
| 1117 |
|
|
|
| 1118 |
|
|
void mmu_op(uae_u32 opcode, uae_u16 extra) |
| 1119 |
|
|
{ |
| 1120 |
|
|
if ((extra & 0xB000) == 0) { /* PMOVE instruction */ |
| 1121 |
|
|
|
| 1122 |
|
|
} else if ((extra & 0xF000) == 0x2000) { /* PLOAD instruction */ |
| 1123 |
|
|
} else if ((extra & 0xF000) == 0x8000) { /* PTEST instruction */ |
| 1124 |
|
|
} else |
| 1125 |
|
|
op_illg (opcode); |
| 1126 |
|
|
} |
| 1127 |
|
|
|
| 1128 |
|
|
static int n_insns = 0, n_spcinsns = 0; |
| 1129 |
|
|
|
| 1130 |
|
|
static uaecptr last_trace_ad = 0; |
| 1131 |
|
|
|
| 1132 |
|
|
static void do_trace (void) |
| 1133 |
|
|
{ |
| 1134 |
|
|
if (regs.t0) { |
| 1135 |
|
|
uae_u16 opcode; |
| 1136 |
|
|
/* should also include TRAP, CHK, SR modification FPcc */ |
| 1137 |
|
|
/* probably never used so why bother */ |
| 1138 |
|
|
/* We can afford this to be inefficient... */ |
| 1139 |
|
|
m68k_setpc (m68k_getpc ()); |
| 1140 |
|
|
fill_prefetch_0 (); |
| 1141 |
|
|
opcode = get_word (regs.pc); |
| 1142 |
|
|
if (opcode == 0x4e72 /* RTE */ |
| 1143 |
|
|
|| opcode == 0x4e74 /* RTD */ |
| 1144 |
|
|
|| opcode == 0x4e75 /* RTS */ |
| 1145 |
|
|
|| opcode == 0x4e77 /* RTR */ |
| 1146 |
|
|
|| opcode == 0x4e76 /* TRAPV */ |
| 1147 |
|
|
|| (opcode & 0xffc0) == 0x4e80 /* JSR */ |
| 1148 |
|
|
|| (opcode & 0xffc0) == 0x4ec0 /* JMP */ |
| 1149 |
|
|
|| (opcode & 0xff00) == 0x6100 /* BSR */ |
| 1150 |
|
|
|| ((opcode & 0xf000) == 0x6000 /* Bcc */ |
| 1151 |
|
|
&& cctrue((opcode >> 8) & 0xf)) |
| 1152 |
|
|
|| ((opcode & 0xf0f0) == 0x5050 /* DBcc */ |
| 1153 |
|
|
&& !cctrue((opcode >> 8) & 0xf) |
| 1154 |
|
|
&& (uae_s16)m68k_dreg(regs, opcode & 7) != 0)) |
| 1155 |
|
|
{ |
| 1156 |
|
|
last_trace_ad = m68k_getpc (); |
| 1157 |
|
|
regs.spcflags &= ~SPCFLAG_TRACE; |
| 1158 |
|
|
regs.spcflags |= SPCFLAG_DOTRACE; |
| 1159 |
|
|
} |
| 1160 |
|
|
} else if (regs.t1) { |
| 1161 |
|
|
last_trace_ad = m68k_getpc (); |
| 1162 |
|
|
regs.spcflags &= ~SPCFLAG_TRACE; |
| 1163 |
|
|
regs.spcflags |= SPCFLAG_DOTRACE; |
| 1164 |
|
|
} |
| 1165 |
|
|
} |
| 1166 |
|
|
|
| 1167 |
|
|
|
| 1168 |
|
|
static int do_specialties (void) |
| 1169 |
|
|
{ |
| 1170 |
|
|
/*n_spcinsns++;*/ |
| 1171 |
|
|
if (regs.spcflags & SPCFLAG_DOTRACE) { |
| 1172 |
|
|
Exception (9,last_trace_ad); |
| 1173 |
|
|
} |
| 1174 |
|
|
while (regs.spcflags & SPCFLAG_STOP) { |
| 1175 |
|
|
if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)){ |
| 1176 |
|
|
int intr = intlev (); |
| 1177 |
|
|
regs.spcflags &= ~(SPCFLAG_INT | SPCFLAG_DOINT); |
| 1178 |
|
|
if (intr != -1 && intr > regs.intmask) { |
| 1179 |
|
|
Interrupt (intr); |
| 1180 |
|
|
regs.stopped = 0; |
| 1181 |
|
|
regs.spcflags &= ~SPCFLAG_STOP; |
| 1182 |
|
|
} |
| 1183 |
|
|
} |
| 1184 |
|
|
} |
| 1185 |
|
|
if (regs.spcflags & SPCFLAG_TRACE) |
| 1186 |
|
|
do_trace (); |
| 1187 |
|
|
|
| 1188 |
|
|
if (regs.spcflags & SPCFLAG_DOINT) { |
| 1189 |
|
|
int intr = intlev (); |
| 1190 |
|
|
regs.spcflags &= ~SPCFLAG_DOINT; |
| 1191 |
|
|
if (intr != -1 && intr > regs.intmask) { |
| 1192 |
|
|
Interrupt (intr); |
| 1193 |
|
|
regs.stopped = 0; |
| 1194 |
|
|
} |
| 1195 |
|
|
} |
| 1196 |
|
|
if (regs.spcflags & SPCFLAG_INT) { |
| 1197 |
|
|
regs.spcflags &= ~SPCFLAG_INT; |
| 1198 |
|
|
regs.spcflags |= SPCFLAG_DOINT; |
| 1199 |
|
|
} |
| 1200 |
|
|
if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) { |
| 1201 |
|
|
regs.spcflags &= ~(SPCFLAG_BRK | SPCFLAG_MODE_CHANGE); |
| 1202 |
|
|
return 1; |
| 1203 |
|
|
} |
| 1204 |
|
|
return 0; |
| 1205 |
|
|
} |
| 1206 |
|
|
|
| 1207 |
|
|
static void m68k_run_1 (void) |
| 1208 |
|
|
{ |
| 1209 |
cebix |
1.4 |
for (;;) { |
| 1210 |
|
|
uae_u32 opcode = GET_OPCODE; |
| 1211 |
|
|
(*cpufunctbl[opcode])(opcode); |
| 1212 |
|
|
if (regs.spcflags) { |
| 1213 |
|
|
if (do_specialties()) |
| 1214 |
|
|
return; |
| 1215 |
|
|
} |
| 1216 |
cebix |
1.1 |
} |
| 1217 |
|
|
} |
| 1218 |
|
|
|
| 1219 |
|
|
#define m68k_run1 m68k_run_1 |
| 1220 |
|
|
|
| 1221 |
|
|
int in_m68k_go = 0; |
| 1222 |
|
|
|
| 1223 |
|
|
void m68k_go (int may_quit) |
| 1224 |
|
|
{ |
| 1225 |
|
|
// m68k_go() must be reentrant for Execute68k() and Execute68kTrap() to work |
| 1226 |
|
|
/* |
| 1227 |
|
|
if (in_m68k_go || !may_quit) { |
| 1228 |
|
|
write_log("Bug! m68k_go is not reentrant.\n"); |
| 1229 |
|
|
abort(); |
| 1230 |
|
|
} |
| 1231 |
|
|
*/ |
| 1232 |
|
|
in_m68k_go++; |
| 1233 |
|
|
for (;;) { |
| 1234 |
|
|
if (quit_program > 0) { |
| 1235 |
|
|
if (quit_program == 1) |
| 1236 |
|
|
break; |
| 1237 |
|
|
quit_program = 0; |
| 1238 |
|
|
m68k_reset (); |
| 1239 |
|
|
} |
| 1240 |
|
|
m68k_run1(); |
| 1241 |
|
|
} |
| 1242 |
|
|
if (debugging) { |
| 1243 |
|
|
uaecptr nextpc; |
| 1244 |
|
|
m68k_dumpstate(&nextpc); |
| 1245 |
|
|
exit(1); |
| 1246 |
|
|
} |
| 1247 |
|
|
in_m68k_go--; |
| 1248 |
|
|
} |
| 1249 |
|
|
|
| 1250 |
|
|
static void m68k_verify (uaecptr addr, uaecptr *nextpc) |
| 1251 |
|
|
{ |
| 1252 |
|
|
uae_u32 opcode, val; |
| 1253 |
|
|
struct instr *dp; |
| 1254 |
|
|
|
| 1255 |
|
|
opcode = get_iword_1(0); |
| 1256 |
|
|
last_op_for_exception_3 = opcode; |
| 1257 |
|
|
m68kpc_offset = 2; |
| 1258 |
|
|
|
| 1259 |
|
|
if (cpufunctbl[cft_map (opcode)] == op_illg_1) { |
| 1260 |
|
|
opcode = 0x4AFC; |
| 1261 |
|
|
} |
| 1262 |
|
|
dp = table68k + opcode; |
| 1263 |
|
|
|
| 1264 |
|
|
if (dp->suse) { |
| 1265 |
|
|
if (!verify_ea (dp->sreg, (amodes)dp->smode, (wordsizes)dp->size, &val)) { |
| 1266 |
|
|
Exception (3, 0); |
| 1267 |
|
|
return; |
| 1268 |
|
|
} |
| 1269 |
|
|
} |
| 1270 |
|
|
if (dp->duse) { |
| 1271 |
|
|
if (!verify_ea (dp->dreg, (amodes)dp->dmode, (wordsizes)dp->size, &val)) { |
| 1272 |
|
|
Exception (3, 0); |
| 1273 |
|
|
return; |
| 1274 |
|
|
} |
| 1275 |
|
|
} |
| 1276 |
|
|
} |
| 1277 |
|
|
|
| 1278 |
|
|
void m68k_disasm (uaecptr addr, uaecptr *nextpc, int cnt) |
| 1279 |
|
|
{ |
| 1280 |
|
|
uaecptr newpc = 0; |
| 1281 |
|
|
m68kpc_offset = addr - m68k_getpc (); |
| 1282 |
|
|
while (cnt-- > 0) { |
| 1283 |
|
|
char instrname[20],*ccpt; |
| 1284 |
|
|
int opwords; |
| 1285 |
|
|
uae_u32 opcode; |
| 1286 |
|
|
struct mnemolookup *lookup; |
| 1287 |
|
|
struct instr *dp; |
| 1288 |
|
|
printf ("%08lx: ", m68k_getpc () + m68kpc_offset); |
| 1289 |
|
|
for (opwords = 0; opwords < 5; opwords++){ |
| 1290 |
|
|
printf ("%04x ", get_iword_1 (m68kpc_offset + opwords*2)); |
| 1291 |
|
|
} |
| 1292 |
|
|
opcode = get_iword_1 (m68kpc_offset); |
| 1293 |
|
|
m68kpc_offset += 2; |
| 1294 |
|
|
if (cpufunctbl[cft_map (opcode)] == op_illg_1) { |
| 1295 |
|
|
opcode = 0x4AFC; |
| 1296 |
|
|
} |
| 1297 |
|
|
dp = table68k + opcode; |
| 1298 |
|
|
for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++) |
| 1299 |
|
|
; |
| 1300 |
|
|
|
| 1301 |
|
|
strcpy (instrname, lookup->name); |
| 1302 |
|
|
ccpt = strstr (instrname, "cc"); |
| 1303 |
|
|
if (ccpt != 0) { |
| 1304 |
|
|
strncpy (ccpt, ccnames[dp->cc], 2); |
| 1305 |
|
|
} |
| 1306 |
|
|
printf ("%s", instrname); |
| 1307 |
|
|
switch (dp->size){ |
| 1308 |
|
|
case sz_byte: printf (".B "); break; |
| 1309 |
|
|
case sz_word: printf (".W "); break; |
| 1310 |
|
|
case sz_long: printf (".L "); break; |
| 1311 |
|
|
default: printf (" "); break; |
| 1312 |
|
|
} |
| 1313 |
|
|
|
| 1314 |
|
|
if (dp->suse) { |
| 1315 |
|
|
newpc = m68k_getpc () + m68kpc_offset; |
| 1316 |
|
|
newpc += ShowEA (dp->sreg, (amodes)dp->smode, (wordsizes)dp->size, 0); |
| 1317 |
|
|
} |
| 1318 |
|
|
if (dp->suse && dp->duse) |
| 1319 |
|
|
printf (","); |
| 1320 |
|
|
if (dp->duse) { |
| 1321 |
|
|
newpc = m68k_getpc () + m68kpc_offset; |
| 1322 |
|
|
newpc += ShowEA (dp->dreg, (amodes)dp->dmode, (wordsizes)dp->size, 0); |
| 1323 |
|
|
} |
| 1324 |
|
|
if (ccpt != 0) { |
| 1325 |
|
|
if (cctrue(dp->cc)) |
| 1326 |
|
|
printf (" == %08lx (TRUE)", newpc); |
| 1327 |
|
|
else |
| 1328 |
|
|
printf (" == %08lx (FALSE)", newpc); |
| 1329 |
|
|
} else if ((opcode & 0xff00) == 0x6100) /* BSR */ |
| 1330 |
|
|
printf (" == %08lx", newpc); |
| 1331 |
|
|
printf ("\n"); |
| 1332 |
|
|
} |
| 1333 |
|
|
if (nextpc) |
| 1334 |
|
|
*nextpc = m68k_getpc () + m68kpc_offset; |
| 1335 |
|
|
} |
| 1336 |
|
|
|
| 1337 |
|
|
void m68k_dumpstate (uaecptr *nextpc) |
| 1338 |
|
|
{ |
| 1339 |
|
|
int i; |
| 1340 |
|
|
for (i = 0; i < 8; i++){ |
| 1341 |
|
|
printf ("D%d: %08lx ", i, m68k_dreg(regs, i)); |
| 1342 |
|
|
if ((i & 3) == 3) printf ("\n"); |
| 1343 |
|
|
} |
| 1344 |
|
|
for (i = 0; i < 8; i++){ |
| 1345 |
|
|
printf ("A%d: %08lx ", i, m68k_areg(regs, i)); |
| 1346 |
|
|
if ((i & 3) == 3) printf ("\n"); |
| 1347 |
|
|
} |
| 1348 |
|
|
if (regs.s == 0) regs.usp = m68k_areg(regs, 7); |
| 1349 |
|
|
if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7); |
| 1350 |
|
|
if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7); |
| 1351 |
|
|
printf ("USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n", |
| 1352 |
|
|
regs.usp,regs.isp,regs.msp,regs.vbr); |
| 1353 |
|
|
printf ("T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n", |
| 1354 |
|
|
regs.t1, regs.t0, regs.s, regs.m, |
| 1355 |
|
|
GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask); |
| 1356 |
|
|
for (i = 0; i < 8; i++){ |
| 1357 |
|
|
printf ("FP%d: %g ", i, regs.fp[i]); |
| 1358 |
|
|
if ((i & 3) == 3) printf ("\n"); |
| 1359 |
|
|
} |
| 1360 |
|
|
printf ("N=%d Z=%d I=%d NAN=%d\n", |
| 1361 |
|
|
(regs.fpsr & 0x8000000) != 0, |
| 1362 |
|
|
(regs.fpsr & 0x4000000) != 0, |
| 1363 |
|
|
(regs.fpsr & 0x2000000) != 0, |
| 1364 |
|
|
(regs.fpsr & 0x1000000) != 0); |
| 1365 |
|
|
|
| 1366 |
|
|
m68k_disasm(m68k_getpc (), nextpc, 1); |
| 1367 |
|
|
if (nextpc) |
| 1368 |
|
|
printf ("next PC: %08lx\n", *nextpc); |
| 1369 |
|
|
} |
