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root/cebix/BasiliskII/src/uae_cpu/newcpu.cpp
Revision: 1.10
Committed: 2002-03-16T16:31:54Z (22 years, 7 months ago) by gbeauche
Branch: MAIN
Changes since 1.9: +67 -0 lines
Log Message:
- Add Flight Recorder for m68k too. That helps. ;-)

File Contents

# User Rev Content
1 cebix 1.1 /*
2     * UAE - The Un*x Amiga Emulator
3     *
4     * MC68000 emulation
5     *
6     * (c) 1995 Bernd Schmidt
7     */
8    
9     #include <stdio.h>
10     #include <stdlib.h>
11     #include <string.h>
12    
13     #include "sysdeps.h"
14    
15     #include "cpu_emulation.h"
16     #include "main.h"
17     #include "emul_op.h"
18    
19     extern int intlev(void); // From baisilisk_glue.cpp
20    
21     #include "m68k.h"
22     #include "memory.h"
23     #include "readcpu.h"
24     #include "newcpu.h"
25    
26 gbeauche 1.10 #if ENABLE_MON
27     #include "mon.h"
28     #include "mon_disass.h"
29     #endif
30    
31 cebix 1.1 int quit_program = 0;
32     int debugging = 0;
33     struct flag_struct regflags;
34    
35     /* Opcode of faulting instruction */
36     uae_u16 last_op_for_exception_3;
37     /* PC at fault time */
38     uaecptr last_addr_for_exception_3;
39     /* Address that generated the exception */
40     uaecptr last_fault_for_exception_3;
41    
42     int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
43     int imm8_table[] = { 8,1,2,3,4,5,6,7 };
44    
45     int movem_index1[256];
46     int movem_index2[256];
47     int movem_next[256];
48    
49     int fpp_movem_index1[256];
50     int fpp_movem_index2[256];
51     int fpp_movem_next[256];
52    
53     cpuop_func *cpufunctbl[65536];
54    
55 gbeauche 1.10 #define FLIGHT_RECORDER 0
56    
57     #if FLIGHT_RECORDER
58     struct rec_step {
59     uae_u32 d[8];
60     uae_u32 a[8];
61     uae_u32 pc;
62     };
63    
64     const int LOG_SIZE = 8192;
65     static rec_step log[LOG_SIZE];
66     static int log_ptr = -1; // First time initialization
67    
68     static const char *log_filename(void)
69     {
70     const char *name = getenv("M68K_LOG_FILE");
71     return name ? name : "log.68k";
72     }
73    
74     static void record_step(uaecptr pc)
75     {
76     for (int i = 0; i < 8; i++) {
77     log[log_ptr].d[i] = m68k_dreg(regs, i);
78     log[log_ptr].a[i] = m68k_areg(regs, i);
79     }
80     log[log_ptr].pc = pc;
81     log_ptr = (log_ptr + 1) % LOG_SIZE;
82     }
83    
84     static void dump_log(void)
85     {
86     FILE *f = fopen(log_filename(), "w");
87     if (f == NULL)
88     return;
89     for (int i = 0; i < LOG_SIZE; i++) {
90     int j = (i + log_ptr) % LOG_SIZE;
91     fprintf(f, "pc %08x\n", log[j].pc);
92     fprintf(f, "d0 %08x d1 %08x d2 %08x d3 %08x\n", log[j].d[0], log[j].d[1], log[j].d[2], log[j].d[3]);
93     fprintf(f, "d4 %08x d5 %08x d6 %08x d7 %08x\n", log[j].d[4], log[j].d[5], log[j].d[6], log[j].d[7]);
94     fprintf(f, "a0 %08x a1 %08x a2 %08x a3 %08x\n", log[j].a[0], log[j].a[1], log[j].a[2], log[j].a[3]);
95     fprintf(f, "a4 %08x a5 %08x a6 %08x a7 %08x\n", log[j].a[4], log[j].a[5], log[j].a[6], log[j].a[7]);
96     #if ENABLE_MON
97     disass_68k(f, log[j].pc);
98     #endif
99     }
100     }
101     #endif
102    
103 cebix 1.1 #define COUNT_INSTRS 0
104    
105     #if COUNT_INSTRS
106     static unsigned long int instrcount[65536];
107     static uae_u16 opcodenums[65536];
108    
109     static int compfn (const void *el1, const void *el2)
110     {
111     return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
112     }
113    
114     static char *icountfilename (void)
115     {
116     char *name = getenv ("INSNCOUNT");
117     if (name)
118     return name;
119     return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
120     }
121    
122     void dump_counts (void)
123     {
124     FILE *f = fopen (icountfilename (), "w");
125     unsigned long int total;
126     int i;
127    
128     write_log ("Writing instruction count file...\n");
129     for (i = 0; i < 65536; i++) {
130     opcodenums[i] = i;
131     total += instrcount[i];
132     }
133     qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
134    
135     fprintf (f, "Total: %lu\n", total);
136     for (i=0; i < 65536; i++) {
137     unsigned long int cnt = instrcount[opcodenums[i]];
138     struct instr *dp;
139     struct mnemolookup *lookup;
140     if (!cnt)
141     break;
142     dp = table68k + opcodenums[i];
143     for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
144     ;
145     fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
146     }
147     fclose (f);
148     }
149     #else
150     void dump_counts (void)
151     {
152     }
153     #endif
154    
155     int broken_in;
156    
157     static __inline__ unsigned int cft_map (unsigned int f)
158     {
159     #ifndef HAVE_GET_WORD_UNSWAPPED
160     return f;
161     #else
162     return ((f >> 8) & 255) | ((f & 255) << 8);
163     #endif
164     }
165    
166 cebix 1.4 static void REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM;
167 cebix 1.1
168 cebix 1.4 static void REGPARAM2 op_illg_1 (uae_u32 opcode)
169 cebix 1.1 {
170     op_illg (cft_map (opcode));
171     }
172    
173     static void build_cpufunctbl (void)
174     {
175     int i;
176     unsigned long opcode;
177 cebix 1.2 int cpu_level = 0; // 68000 (default)
178     if (CPUType == 4)
179     cpu_level = 4; // 68040 with FPU
180     else {
181     if (FPUType)
182     cpu_level = 3; // 68020 with FPU
183     else if (CPUType >= 2)
184     cpu_level = 2; // 68020
185     else if (CPUType == 1)
186     cpu_level = 1;
187     }
188     struct cputbl *tbl = (
189     cpu_level == 4 ? op_smalltbl_0
190     : cpu_level == 3 ? op_smalltbl_1
191     : cpu_level == 2 ? op_smalltbl_2
192     : cpu_level == 1 ? op_smalltbl_3
193     : op_smalltbl_4);
194 cebix 1.1
195     for (opcode = 0; opcode < 65536; opcode++)
196     cpufunctbl[cft_map (opcode)] = op_illg_1;
197     for (i = 0; tbl[i].handler != NULL; i++) {
198     if (! tbl[i].specific)
199     cpufunctbl[cft_map (tbl[i].opcode)] = tbl[i].handler;
200     }
201     for (opcode = 0; opcode < 65536; opcode++) {
202     cpuop_func *f;
203    
204     if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > cpu_level)
205     continue;
206    
207     if (table68k[opcode].handler != -1) {
208     f = cpufunctbl[cft_map (table68k[opcode].handler)];
209     if (f == op_illg_1)
210     abort();
211     cpufunctbl[cft_map (opcode)] = f;
212     }
213     }
214     for (i = 0; tbl[i].handler != NULL; i++) {
215     if (tbl[i].specific)
216     cpufunctbl[cft_map (tbl[i].opcode)] = tbl[i].handler;
217     }
218     }
219    
220     void init_m68k (void)
221     {
222     int i;
223    
224     for (i = 0 ; i < 256 ; i++) {
225     int j;
226     for (j = 0 ; j < 8 ; j++) {
227     if (i & (1 << j)) break;
228     }
229     movem_index1[i] = j;
230     movem_index2[i] = 7-j;
231     movem_next[i] = i & (~(1 << j));
232     }
233     for (i = 0 ; i < 256 ; i++) {
234     int j;
235     for (j = 7 ; j >= 0 ; j--) {
236     if (i & (1 << j)) break;
237     }
238 cebix 1.5 fpp_movem_index1[i] = 7-j;
239     fpp_movem_index2[i] = j;
240 cebix 1.1 fpp_movem_next[i] = i & (~(1 << j));
241     }
242     #if COUNT_INSTRS
243     {
244     FILE *f = fopen (icountfilename (), "r");
245     memset (instrcount, 0, sizeof instrcount);
246     if (f) {
247     uae_u32 opcode, count, total;
248     char name[20];
249     write_log ("Reading instruction count file...\n");
250     fscanf (f, "Total: %lu\n", &total);
251     while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
252     instrcount[opcode] = count;
253     }
254     fclose(f);
255     }
256     }
257     #endif
258     read_table68k ();
259     do_merges ();
260    
261     build_cpufunctbl ();
262 gbeauche 1.6
263     fpu_init ();
264     fpu_set_integral_fpu (CPUType == 4);
265     }
266    
267     void exit_m68k (void)
268     {
269     fpu_exit ();
270 cebix 1.1 }
271    
272     struct regstruct regs, lastint_regs;
273     static struct regstruct regs_backup[16];
274     static int backup_pointer = 0;
275     static long int m68kpc_offset;
276     int lastint_no;
277    
278 gbeauche 1.7 #if REAL_ADDRESSING || DIRECT_ADDRESSING
279     #define get_ibyte_1(o) get_byte(get_virtual_address(regs.pc_p) + (o) + 1)
280     #define get_iword_1(o) get_word(get_virtual_address(regs.pc_p) + (o))
281     #define get_ilong_1(o) get_long(get_virtual_address(regs.pc_p) + (o))
282     #else
283 cebix 1.1 #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
284     #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
285     #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
286 gbeauche 1.7 #endif
287 cebix 1.1
288     uae_s32 ShowEA (int reg, amodes mode, wordsizes size, char *buf)
289     {
290     uae_u16 dp;
291     uae_s8 disp8;
292     uae_s16 disp16;
293     int r;
294     uae_u32 dispreg;
295     uaecptr addr;
296     uae_s32 offset = 0;
297     char buffer[80];
298    
299     switch (mode){
300     case Dreg:
301     sprintf (buffer,"D%d", reg);
302     break;
303     case Areg:
304     sprintf (buffer,"A%d", reg);
305     break;
306     case Aind:
307     sprintf (buffer,"(A%d)", reg);
308     break;
309     case Aipi:
310     sprintf (buffer,"(A%d)+", reg);
311     break;
312     case Apdi:
313     sprintf (buffer,"-(A%d)", reg);
314     break;
315     case Ad16:
316     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
317     addr = m68k_areg(regs,reg) + (uae_s16)disp16;
318     sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
319 cebix 1.5 (unsigned long)addr);
320 cebix 1.1 break;
321     case Ad8r:
322     dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
323     disp8 = dp & 0xFF;
324     r = (dp & 0x7000) >> 12;
325     dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
326     if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
327     dispreg <<= (dp >> 9) & 3;
328    
329     if (dp & 0x100) {
330     uae_s32 outer = 0, disp = 0;
331     uae_s32 base = m68k_areg(regs,reg);
332     char name[10];
333     sprintf (name,"A%d, ",reg);
334     if (dp & 0x80) { base = 0; name[0] = 0; }
335     if (dp & 0x40) dispreg = 0;
336     if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
337     if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
338     base += disp;
339    
340     if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
341     if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
342    
343     if (!(dp & 4)) base += dispreg;
344     if (dp & 3) base = get_long (base);
345     if (dp & 4) base += dispreg;
346    
347     addr = base + outer;
348     sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
349     dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
350     1 << ((dp >> 9) & 3),
351     disp,outer,
352 cebix 1.5 (unsigned long)addr);
353 cebix 1.1 } else {
354     addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
355     sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
356     dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
357     1 << ((dp >> 9) & 3), disp8,
358 cebix 1.5 (unsigned long)addr);
359 cebix 1.1 }
360     break;
361     case PC16:
362     addr = m68k_getpc () + m68kpc_offset;
363     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
364     addr += (uae_s16)disp16;
365 cebix 1.5 sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
366 cebix 1.1 break;
367     case PC8r:
368     addr = m68k_getpc () + m68kpc_offset;
369     dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
370     disp8 = dp & 0xFF;
371     r = (dp & 0x7000) >> 12;
372     dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
373     if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
374     dispreg <<= (dp >> 9) & 3;
375    
376     if (dp & 0x100) {
377     uae_s32 outer = 0,disp = 0;
378     uae_s32 base = addr;
379     char name[10];
380     sprintf (name,"PC, ");
381     if (dp & 0x80) { base = 0; name[0] = 0; }
382     if (dp & 0x40) dispreg = 0;
383     if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
384     if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
385     base += disp;
386    
387     if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
388     if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
389    
390     if (!(dp & 4)) base += dispreg;
391     if (dp & 3) base = get_long (base);
392     if (dp & 4) base += dispreg;
393    
394     addr = base + outer;
395     sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
396     dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
397     1 << ((dp >> 9) & 3),
398     disp,outer,
399 cebix 1.5 (unsigned long)addr);
400 cebix 1.1 } else {
401     addr += (uae_s32)((uae_s8)disp8) + dispreg;
402     sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
403     (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
404 cebix 1.5 disp8, (unsigned long)addr);
405 cebix 1.1 }
406     break;
407     case absw:
408 cebix 1.5 sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
409 cebix 1.1 m68kpc_offset += 2;
410     break;
411     case absl:
412 cebix 1.5 sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
413 cebix 1.1 m68kpc_offset += 4;
414     break;
415     case imm:
416     switch (size){
417     case sz_byte:
418     sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
419     m68kpc_offset += 2;
420     break;
421     case sz_word:
422     sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
423     m68kpc_offset += 2;
424     break;
425     case sz_long:
426 cebix 1.5 sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
427 cebix 1.1 m68kpc_offset += 4;
428     break;
429     default:
430     break;
431     }
432     break;
433     case imm0:
434     offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
435     m68kpc_offset += 2;
436     sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
437     break;
438     case imm1:
439     offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
440     m68kpc_offset += 2;
441     sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
442     break;
443     case imm2:
444     offset = (uae_s32)get_ilong_1 (m68kpc_offset);
445     m68kpc_offset += 4;
446 cebix 1.5 sprintf (buffer,"#$%08lx", (unsigned long)offset);
447 cebix 1.1 break;
448     case immi:
449     offset = (uae_s32)(uae_s8)(reg & 0xff);
450 cebix 1.5 sprintf (buffer,"#$%08lx", (unsigned long)offset);
451 cebix 1.1 break;
452     default:
453     break;
454     }
455     if (buf == 0)
456     printf ("%s", buffer);
457     else
458     strcat (buf, buffer);
459     return offset;
460     }
461    
462     /* The plan is that this will take over the job of exception 3 handling -
463     * the CPU emulation functions will just do a longjmp to m68k_go whenever
464     * they hit an odd address. */
465     static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
466     {
467     uae_u16 dp;
468     uae_s8 disp8;
469     uae_s16 disp16;
470     int r;
471     uae_u32 dispreg;
472     uaecptr addr;
473     uae_s32 offset = 0;
474    
475     switch (mode){
476     case Dreg:
477     *val = m68k_dreg (regs, reg);
478     return 1;
479     case Areg:
480     *val = m68k_areg (regs, reg);
481     return 1;
482    
483     case Aind:
484     case Aipi:
485     addr = m68k_areg (regs, reg);
486     break;
487     case Apdi:
488     addr = m68k_areg (regs, reg);
489     break;
490     case Ad16:
491     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
492     addr = m68k_areg(regs,reg) + (uae_s16)disp16;
493     break;
494     case Ad8r:
495     addr = m68k_areg (regs, reg);
496     d8r_common:
497     dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
498     disp8 = dp & 0xFF;
499     r = (dp & 0x7000) >> 12;
500     dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
501     if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
502     dispreg <<= (dp >> 9) & 3;
503    
504     if (dp & 0x100) {
505     uae_s32 outer = 0, disp = 0;
506     uae_s32 base = addr;
507     if (dp & 0x80) base = 0;
508     if (dp & 0x40) dispreg = 0;
509     if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
510     if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
511     base += disp;
512    
513     if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
514     if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
515    
516     if (!(dp & 4)) base += dispreg;
517     if (dp & 3) base = get_long (base);
518     if (dp & 4) base += dispreg;
519    
520     addr = base + outer;
521     } else {
522     addr += (uae_s32)((uae_s8)disp8) + dispreg;
523     }
524     break;
525     case PC16:
526     addr = m68k_getpc () + m68kpc_offset;
527     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
528     addr += (uae_s16)disp16;
529     break;
530     case PC8r:
531     addr = m68k_getpc () + m68kpc_offset;
532     goto d8r_common;
533     case absw:
534     addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
535     m68kpc_offset += 2;
536     break;
537     case absl:
538     addr = get_ilong_1 (m68kpc_offset);
539     m68kpc_offset += 4;
540     break;
541     case imm:
542     switch (size){
543     case sz_byte:
544     *val = get_iword_1 (m68kpc_offset) & 0xff;
545     m68kpc_offset += 2;
546     break;
547     case sz_word:
548     *val = get_iword_1 (m68kpc_offset) & 0xffff;
549     m68kpc_offset += 2;
550     break;
551     case sz_long:
552     *val = get_ilong_1 (m68kpc_offset);
553     m68kpc_offset += 4;
554     break;
555     default:
556     break;
557     }
558     return 1;
559     case imm0:
560     *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
561     m68kpc_offset += 2;
562     return 1;
563     case imm1:
564     *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
565     m68kpc_offset += 2;
566     return 1;
567     case imm2:
568     *val = get_ilong_1 (m68kpc_offset);
569     m68kpc_offset += 4;
570     return 1;
571     case immi:
572     *val = (uae_s32)(uae_s8)(reg & 0xff);
573     return 1;
574     default:
575     addr = 0;
576     break;
577     }
578     if ((addr & 1) == 0)
579     return 1;
580    
581     last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
582     last_fault_for_exception_3 = addr;
583     return 0;
584     }
585    
586     uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
587     {
588     int reg = (dp >> 12) & 15;
589     uae_s32 regd = regs.regs[reg];
590     if ((dp & 0x800) == 0)
591     regd = (uae_s32)(uae_s16)regd;
592     regd <<= (dp >> 9) & 3;
593     if (dp & 0x100) {
594     uae_s32 outer = 0;
595     if (dp & 0x80) base = 0;
596     if (dp & 0x40) regd = 0;
597    
598     if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
599     if ((dp & 0x30) == 0x30) base += next_ilong();
600    
601     if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
602     if ((dp & 0x3) == 0x3) outer = next_ilong();
603    
604     if ((dp & 0x4) == 0) base += regd;
605     if (dp & 0x3) base = get_long (base);
606     if (dp & 0x4) base += regd;
607    
608     return base + outer;
609     } else {
610     return base + (uae_s32)((uae_s8)dp) + regd;
611     }
612     }
613    
614     uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
615     {
616     int reg = (dp >> 12) & 15;
617     uae_s32 regd = regs.regs[reg];
618     #if 1
619     if ((dp & 0x800) == 0)
620     regd = (uae_s32)(uae_s16)regd;
621     return base + (uae_s8)dp + regd;
622     #else
623     /* Branch-free code... benchmark this again now that
624     * things are no longer inline. */
625     uae_s32 regd16;
626     uae_u32 mask;
627     mask = ((dp & 0x800) >> 11) - 1;
628     regd16 = (uae_s32)(uae_s16)regd;
629     regd16 &= mask;
630     mask = ~mask;
631     base += (uae_s8)dp;
632     regd &= mask;
633     regd |= regd16;
634     return base + regd;
635     #endif
636     }
637    
638     void MakeSR (void)
639     {
640     #if 0
641     assert((regs.t1 & 1) == regs.t1);
642     assert((regs.t0 & 1) == regs.t0);
643     assert((regs.s & 1) == regs.s);
644     assert((regs.m & 1) == regs.m);
645     assert((XFLG & 1) == XFLG);
646     assert((NFLG & 1) == NFLG);
647     assert((ZFLG & 1) == ZFLG);
648     assert((VFLG & 1) == VFLG);
649     assert((CFLG & 1) == CFLG);
650     #endif
651     regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
652     | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
653     | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
654     | GET_CFLG);
655     }
656    
657     void MakeFromSR (void)
658     {
659     int oldm = regs.m;
660     int olds = regs.s;
661    
662     regs.t1 = (regs.sr >> 15) & 1;
663     regs.t0 = (regs.sr >> 14) & 1;
664     regs.s = (regs.sr >> 13) & 1;
665     regs.m = (regs.sr >> 12) & 1;
666     regs.intmask = (regs.sr >> 8) & 7;
667     SET_XFLG ((regs.sr >> 4) & 1);
668     SET_NFLG ((regs.sr >> 3) & 1);
669     SET_ZFLG ((regs.sr >> 2) & 1);
670     SET_VFLG ((regs.sr >> 1) & 1);
671     SET_CFLG (regs.sr & 1);
672     if (CPUType >= 2) {
673     if (olds != regs.s) {
674     if (olds) {
675     if (oldm)
676     regs.msp = m68k_areg(regs, 7);
677     else
678     regs.isp = m68k_areg(regs, 7);
679     m68k_areg(regs, 7) = regs.usp;
680     } else {
681     regs.usp = m68k_areg(regs, 7);
682     m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
683     }
684     } else if (olds && oldm != regs.m) {
685     if (oldm) {
686     regs.msp = m68k_areg(regs, 7);
687     m68k_areg(regs, 7) = regs.isp;
688     } else {
689     regs.isp = m68k_areg(regs, 7);
690     m68k_areg(regs, 7) = regs.msp;
691     }
692     }
693     } else {
694     if (olds != regs.s) {
695     if (olds) {
696     regs.isp = m68k_areg(regs, 7);
697     m68k_areg(regs, 7) = regs.usp;
698     } else {
699     regs.usp = m68k_areg(regs, 7);
700     m68k_areg(regs, 7) = regs.isp;
701     }
702     }
703     }
704    
705     regs.spcflags |= SPCFLAG_INT;
706     if (regs.t1 || regs.t0)
707     regs.spcflags |= SPCFLAG_TRACE;
708     else
709     regs.spcflags &= ~(SPCFLAG_TRACE | SPCFLAG_DOTRACE);
710     }
711    
712     void Exception(int nr, uaecptr oldpc)
713     {
714 gbeauche 1.9 uae_u32 currpc = m68k_getpc ();
715 cebix 1.1 MakeSR();
716     if (!regs.s) {
717     regs.usp = m68k_areg(regs, 7);
718     if (CPUType >= 2)
719     m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
720     else
721     m68k_areg(regs, 7) = regs.isp;
722     regs.s = 1;
723     }
724     if (CPUType > 0) {
725     if (nr == 2 || nr == 3) {
726     int i;
727     /* @@@ this is probably wrong (?) */
728     for (i = 0 ; i < 12 ; i++) {
729     m68k_areg(regs, 7) -= 2;
730     put_word (m68k_areg(regs, 7), 0);
731     }
732     m68k_areg(regs, 7) -= 2;
733     put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
734     } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
735     m68k_areg(regs, 7) -= 4;
736     put_long (m68k_areg(regs, 7), oldpc);
737     m68k_areg(regs, 7) -= 2;
738     put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
739     } else if (regs.m && nr >= 24 && nr < 32) {
740     m68k_areg(regs, 7) -= 2;
741     put_word (m68k_areg(regs, 7), nr * 4);
742     m68k_areg(regs, 7) -= 4;
743 gbeauche 1.9 put_long (m68k_areg(regs, 7), currpc);
744 cebix 1.1 m68k_areg(regs, 7) -= 2;
745     put_word (m68k_areg(regs, 7), regs.sr);
746     regs.sr |= (1 << 13);
747     regs.msp = m68k_areg(regs, 7);
748     m68k_areg(regs, 7) = regs.isp;
749     m68k_areg(regs, 7) -= 2;
750     put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
751     } else {
752     m68k_areg(regs, 7) -= 2;
753     put_word (m68k_areg(regs, 7), nr * 4);
754     }
755     } else {
756     if (nr == 2 || nr == 3) {
757     m68k_areg(regs, 7) -= 12;
758     /* ??????? */
759     if (nr == 3) {
760     put_long (m68k_areg(regs, 7), last_fault_for_exception_3);
761     put_word (m68k_areg(regs, 7)+4, last_op_for_exception_3);
762     put_long (m68k_areg(regs, 7)+8, last_addr_for_exception_3);
763     }
764     write_log ("Exception!\n");
765     goto kludge_me_do;
766     }
767     }
768     m68k_areg(regs, 7) -= 4;
769 gbeauche 1.9 put_long (m68k_areg(regs, 7), currpc);
770 cebix 1.1 kludge_me_do:
771     m68k_areg(regs, 7) -= 2;
772     put_word (m68k_areg(regs, 7), regs.sr);
773     m68k_setpc (get_long (regs.vbr + 4*nr));
774     fill_prefetch_0 ();
775     regs.t1 = regs.t0 = regs.m = 0;
776     regs.spcflags &= ~(SPCFLAG_TRACE | SPCFLAG_DOTRACE);
777     }
778    
779     static void Interrupt(int nr)
780     {
781     assert(nr < 8 && nr >= 0);
782     lastint_regs = regs;
783     lastint_no = nr;
784     Exception(nr+24, 0);
785    
786     regs.intmask = nr;
787     regs.spcflags |= SPCFLAG_INT;
788     }
789    
790 cebix 1.2 static int caar, cacr, tc, itt0, itt1, dtt0, dtt1;
791 cebix 1.1
792 gbeauche 1.9 int m68k_move2c (int regno, uae_u32 *regp)
793 cebix 1.1 {
794 gbeauche 1.9 if ((CPUType == 1 && (regno & 0x7FF) > 1)
795     || (CPUType < 4 && (regno & 0x7FF) > 2)
796     || (CPUType == 4 && regno == 0x802))
797     {
798 cebix 1.1 op_illg (0x4E7B);
799 gbeauche 1.9 return 0;
800     } else {
801 cebix 1.1 switch (regno) {
802     case 0: regs.sfc = *regp & 7; break;
803     case 1: regs.dfc = *regp & 7; break;
804 gbeauche 1.9 case 2: cacr = *regp & (CPUType < 4 ? 0x3 : 0x80008000); break;
805 cebix 1.2 case 3: tc = *regp & 0xc000; break;
806     case 4: itt0 = *regp & 0xffffe364; break;
807     case 5: itt1 = *regp & 0xffffe364; break;
808     case 6: dtt0 = *regp & 0xffffe364; break;
809     case 7: dtt1 = *regp & 0xffffe364; break;
810 cebix 1.1 case 0x800: regs.usp = *regp; break;
811     case 0x801: regs.vbr = *regp; break;
812     case 0x802: caar = *regp &0xfc; break;
813     case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
814     case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
815     default:
816     op_illg (0x4E7B);
817 gbeauche 1.9 return 0;
818 cebix 1.1 }
819 gbeauche 1.9 }
820     return 1;
821 cebix 1.1 }
822    
823 gbeauche 1.9 int m68k_movec2 (int regno, uae_u32 *regp)
824 cebix 1.1 {
825 gbeauche 1.9 if ((CPUType == 1 && (regno & 0x7FF) > 1)
826     || (CPUType < 4 && (regno & 0x7FF) > 2)
827     || (CPUType == 4 && regno == 0x802))
828     {
829 cebix 1.1 op_illg (0x4E7A);
830 gbeauche 1.9 return 0;
831     } else {
832 cebix 1.1 switch (regno) {
833     case 0: *regp = regs.sfc; break;
834     case 1: *regp = regs.dfc; break;
835     case 2: *regp = cacr; break;
836 cebix 1.2 case 3: *regp = tc; break;
837     case 4: *regp = itt0; break;
838     case 5: *regp = itt1; break;
839     case 6: *regp = dtt0; break;
840     case 7: *regp = dtt1; break;
841 cebix 1.1 case 0x800: *regp = regs.usp; break;
842     case 0x801: *regp = regs.vbr; break;
843     case 0x802: *regp = caar; break;
844     case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
845     case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
846     default:
847     op_illg (0x4E7A);
848 gbeauche 1.9 return 0;
849     }
850 cebix 1.1 }
851 gbeauche 1.9 return 1;
852 cebix 1.1 }
853    
854     static __inline__ int
855     div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 div, uae_u32 *quot, uae_u32 *rem)
856     {
857     uae_u32 q = 0, cbit = 0;
858     int i;
859    
860     if (div <= src_hi) {
861     return 1;
862     }
863     for (i = 0 ; i < 32 ; i++) {
864     cbit = src_hi & 0x80000000ul;
865     src_hi <<= 1;
866     if (src_lo & 0x80000000ul) src_hi++;
867     src_lo <<= 1;
868     q = q << 1;
869     if (cbit || div <= src_hi) {
870     q |= 1;
871     src_hi -= div;
872     }
873     }
874     *quot = q;
875     *rem = src_hi;
876     return 0;
877     }
878    
879     void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
880     {
881     #if defined(uae_s64)
882     if (src == 0) {
883     Exception (5, oldpc);
884     return;
885     }
886     if (extra & 0x800) {
887     /* signed variant */
888     uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
889     uae_s64 quot, rem;
890    
891     if (extra & 0x400) {
892     a &= 0xffffffffu;
893     a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
894     }
895     rem = a % (uae_s64)(uae_s32)src;
896     quot = a / (uae_s64)(uae_s32)src;
897     if ((quot & UVAL64(0xffffffff80000000)) != 0
898     && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
899     {
900     SET_VFLG (1);
901     SET_NFLG (1);
902     SET_CFLG (0);
903     } else {
904     if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
905     SET_VFLG (0);
906     SET_CFLG (0);
907     SET_ZFLG (((uae_s32)quot) == 0);
908     SET_NFLG (((uae_s32)quot) < 0);
909     m68k_dreg(regs, extra & 7) = rem;
910     m68k_dreg(regs, (extra >> 12) & 7) = quot;
911     }
912     } else {
913     /* unsigned */
914     uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
915     uae_u64 quot, rem;
916    
917     if (extra & 0x400) {
918     a &= 0xffffffffu;
919     a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
920     }
921     rem = a % (uae_u64)src;
922     quot = a / (uae_u64)src;
923     if (quot > 0xffffffffu) {
924     SET_VFLG (1);
925     SET_NFLG (1);
926     SET_CFLG (0);
927     } else {
928     SET_VFLG (0);
929     SET_CFLG (0);
930     SET_ZFLG (((uae_s32)quot) == 0);
931     SET_NFLG (((uae_s32)quot) < 0);
932     m68k_dreg(regs, extra & 7) = rem;
933     m68k_dreg(regs, (extra >> 12) & 7) = quot;
934     }
935     }
936     #else
937     if (src == 0) {
938     Exception (5, oldpc);
939     return;
940     }
941     if (extra & 0x800) {
942     /* signed variant */
943     uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
944     uae_s32 hi = lo < 0 ? -1 : 0;
945     uae_s32 save_high;
946     uae_u32 quot, rem;
947     uae_u32 sign;
948    
949     if (extra & 0x400) {
950     hi = (uae_s32)m68k_dreg(regs, extra & 7);
951     }
952     save_high = hi;
953     sign = (hi ^ src);
954     if (hi < 0) {
955     hi = ~hi;
956     lo = -lo;
957     if (lo == 0) hi++;
958     }
959     if ((uae_s32)src < 0) src = -src;
960     if (div_unsigned(hi, lo, src, &quot, &rem) ||
961     (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
962     SET_VFLG (1);
963     SET_NFLG (1);
964     SET_CFLG (0);
965     } else {
966     if (sign & 0x80000000) quot = -quot;
967     if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
968     SET_VFLG (0);
969     SET_CFLG (0);
970     SET_ZFLG (((uae_s32)quot) == 0);
971     SET_NFLG (((uae_s32)quot) < 0);
972     m68k_dreg(regs, extra & 7) = rem;
973     m68k_dreg(regs, (extra >> 12) & 7) = quot;
974     }
975     } else {
976     /* unsigned */
977     uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
978     uae_u32 hi = 0;
979     uae_u32 quot, rem;
980    
981     if (extra & 0x400) {
982     hi = (uae_u32)m68k_dreg(regs, extra & 7);
983     }
984     if (div_unsigned(hi, lo, src, &quot, &rem)) {
985     SET_VFLG (1);
986     SET_NFLG (1);
987     SET_CFLG (0);
988     } else {
989     SET_VFLG (0);
990     SET_CFLG (0);
991     SET_ZFLG (((uae_s32)quot) == 0);
992     SET_NFLG (((uae_s32)quot) < 0);
993     m68k_dreg(regs, extra & 7) = rem;
994     m68k_dreg(regs, (extra >> 12) & 7) = quot;
995     }
996     }
997     #endif
998     }
999    
1000     static __inline__ void
1001     mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1002     {
1003     uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1004     uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1005     uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1006     uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1007     uae_u32 lo;
1008    
1009     lo = r0 + ((r1 << 16) & 0xffff0000ul);
1010     if (lo < r0) r3++;
1011     r0 = lo;
1012     lo = r0 + ((r2 << 16) & 0xffff0000ul);
1013     if (lo < r0) r3++;
1014     r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1015     *dst_lo = lo;
1016     *dst_hi = r3;
1017     }
1018    
1019     void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1020     {
1021     #if defined(uae_s64)
1022     if (extra & 0x800) {
1023     /* signed variant */
1024     uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1025    
1026     a *= (uae_s64)(uae_s32)src;
1027     SET_VFLG (0);
1028     SET_CFLG (0);
1029     SET_ZFLG (a == 0);
1030     SET_NFLG (a < 0);
1031     if (extra & 0x400)
1032     m68k_dreg(regs, extra & 7) = a >> 32;
1033     else if ((a & UVAL64(0xffffffff80000000)) != 0
1034     && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1035     {
1036     SET_VFLG (1);
1037     }
1038     m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1039     } else {
1040     /* unsigned */
1041     uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1042    
1043     a *= (uae_u64)src;
1044     SET_VFLG (0);
1045     SET_CFLG (0);
1046     SET_ZFLG (a == 0);
1047     SET_NFLG (((uae_s64)a) < 0);
1048     if (extra & 0x400)
1049     m68k_dreg(regs, extra & 7) = a >> 32;
1050     else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1051     SET_VFLG (1);
1052     }
1053     m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1054     }
1055     #else
1056     if (extra & 0x800) {
1057     /* signed variant */
1058     uae_s32 src1,src2;
1059     uae_u32 dst_lo,dst_hi;
1060     uae_u32 sign;
1061    
1062     src1 = (uae_s32)src;
1063     src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1064     sign = (src1 ^ src2);
1065     if (src1 < 0) src1 = -src1;
1066     if (src2 < 0) src2 = -src2;
1067     mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1068     if (sign & 0x80000000) {
1069     dst_hi = ~dst_hi;
1070     dst_lo = -dst_lo;
1071     if (dst_lo == 0) dst_hi++;
1072     }
1073     SET_VFLG (0);
1074     SET_CFLG (0);
1075     SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1076     SET_NFLG (((uae_s32)dst_hi) < 0);
1077     if (extra & 0x400)
1078     m68k_dreg(regs, extra & 7) = dst_hi;
1079     else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1080     && ((dst_hi & 0xffffffff) != 0xffffffff
1081     || (dst_lo & 0x80000000) != 0x80000000))
1082     {
1083     SET_VFLG (1);
1084     }
1085     m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1086     } else {
1087     /* unsigned */
1088     uae_u32 dst_lo,dst_hi;
1089    
1090     mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1091    
1092     SET_VFLG (0);
1093     SET_CFLG (0);
1094     SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1095     SET_NFLG (((uae_s32)dst_hi) < 0);
1096     if (extra & 0x400)
1097     m68k_dreg(regs, extra & 7) = dst_hi;
1098     else if (dst_hi != 0) {
1099     SET_VFLG (1);
1100     }
1101     m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1102     }
1103     #endif
1104     }
1105     static char* ccnames[] =
1106     { "T ","F ","HI","LS","CC","CS","NE","EQ",
1107     "VC","VS","PL","MI","GE","LT","GT","LE" };
1108    
1109     void m68k_reset (void)
1110     {
1111     m68k_areg (regs, 7) = 0x2000;
1112     m68k_setpc (ROMBaseMac + 0x2a);
1113     fill_prefetch_0 ();
1114     regs.kick_mask = 0xF80000;
1115     regs.s = 1;
1116     regs.m = 0;
1117     regs.stopped = 0;
1118     regs.t1 = 0;
1119     regs.t0 = 0;
1120     SET_ZFLG (0);
1121     SET_XFLG (0);
1122     SET_CFLG (0);
1123     SET_VFLG (0);
1124     SET_NFLG (0);
1125     regs.spcflags = 0;
1126     regs.intmask = 7;
1127     regs.vbr = regs.sfc = regs.dfc = 0;
1128 gbeauche 1.6 /* gb-- moved into {fpp,fpu_x86}.cpp::fpu_init()
1129     regs.fpcr = regs.fpsr = regs.fpiar = 0; */
1130     fpu_reset();
1131 gbeauche 1.10
1132     #if FLIGHT_RECORDER
1133     #if ENABLE_MON
1134     if (log_ptr == -1) {
1135     // Install "log" command in mon
1136     mon_add_command("log", dump_log, "log Dump m68k emulation log\n");
1137     }
1138     #endif
1139     log_ptr = 0;
1140     memset(log, 0, sizeof(log));
1141     #endif
1142 cebix 1.1 }
1143    
1144 cebix 1.4 void REGPARAM2 op_illg (uae_u32 opcode)
1145 cebix 1.1 {
1146     uaecptr pc = m68k_getpc ();
1147    
1148     if ((opcode & 0xFF00) == 0x7100) {
1149     struct M68kRegisters r;
1150     int i;
1151    
1152 gbeauche 1.9 // Return from Exectue68k()?
1153 cebix 1.1 if (opcode == M68K_EXEC_RETURN) {
1154     regs.spcflags |= SPCFLAG_BRK;
1155     quit_program = 1;
1156 cebix 1.4 return;
1157 cebix 1.1 }
1158    
1159     // Call EMUL_OP opcode
1160     for (i=0; i<8; i++) {
1161     r.d[i] = m68k_dreg(regs, i);
1162     r.a[i] = m68k_areg(regs, i);
1163     }
1164     MakeSR();
1165     r.sr = regs.sr;
1166     EmulOp(opcode, &r);
1167     for (i=0; i<8; i++) {
1168     m68k_dreg(regs, i) = r.d[i];
1169     m68k_areg(regs, i) = r.a[i];
1170     }
1171     regs.sr = r.sr;
1172     MakeFromSR();
1173     m68k_incpc(2);
1174     fill_prefetch_0 ();
1175 cebix 1.4 return;
1176 cebix 1.1 }
1177    
1178     if ((opcode & 0xF000) == 0xA000) {
1179     Exception(0xA,0);
1180 cebix 1.4 return;
1181 cebix 1.1 }
1182    
1183 cebix 1.4 // write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc);
1184 cebix 1.3
1185 cebix 1.1 if ((opcode & 0xF000) == 0xF000) {
1186     Exception(0xB,0);
1187 cebix 1.4 return;
1188 cebix 1.1 }
1189    
1190 cebix 1.4 write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc);
1191    
1192 cebix 1.1 Exception (4,0);
1193     }
1194    
1195     void mmu_op(uae_u32 opcode, uae_u16 extra)
1196     {
1197     if ((extra & 0xB000) == 0) { /* PMOVE instruction */
1198    
1199     } else if ((extra & 0xF000) == 0x2000) { /* PLOAD instruction */
1200     } else if ((extra & 0xF000) == 0x8000) { /* PTEST instruction */
1201     } else
1202     op_illg (opcode);
1203     }
1204    
1205     static int n_insns = 0, n_spcinsns = 0;
1206    
1207     static uaecptr last_trace_ad = 0;
1208    
1209     static void do_trace (void)
1210     {
1211 gbeauche 1.9 if (regs.t0 && CPUType >= 2) {
1212 cebix 1.1 uae_u16 opcode;
1213     /* should also include TRAP, CHK, SR modification FPcc */
1214     /* probably never used so why bother */
1215     /* We can afford this to be inefficient... */
1216     m68k_setpc (m68k_getpc ());
1217     fill_prefetch_0 ();
1218     opcode = get_word (regs.pc);
1219     if (opcode == 0x4e72 /* RTE */
1220     || opcode == 0x4e74 /* RTD */
1221     || opcode == 0x4e75 /* RTS */
1222     || opcode == 0x4e77 /* RTR */
1223     || opcode == 0x4e76 /* TRAPV */
1224     || (opcode & 0xffc0) == 0x4e80 /* JSR */
1225     || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1226     || (opcode & 0xff00) == 0x6100 /* BSR */
1227     || ((opcode & 0xf000) == 0x6000 /* Bcc */
1228     && cctrue((opcode >> 8) & 0xf))
1229     || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1230     && !cctrue((opcode >> 8) & 0xf)
1231     && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1232     {
1233     last_trace_ad = m68k_getpc ();
1234     regs.spcflags &= ~SPCFLAG_TRACE;
1235     regs.spcflags |= SPCFLAG_DOTRACE;
1236     }
1237     } else if (regs.t1) {
1238     last_trace_ad = m68k_getpc ();
1239     regs.spcflags &= ~SPCFLAG_TRACE;
1240     regs.spcflags |= SPCFLAG_DOTRACE;
1241     }
1242     }
1243    
1244    
1245     static int do_specialties (void)
1246     {
1247     /*n_spcinsns++;*/
1248     if (regs.spcflags & SPCFLAG_DOTRACE) {
1249     Exception (9,last_trace_ad);
1250     }
1251     while (regs.spcflags & SPCFLAG_STOP) {
1252     if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)){
1253     int intr = intlev ();
1254     regs.spcflags &= ~(SPCFLAG_INT | SPCFLAG_DOINT);
1255     if (intr != -1 && intr > regs.intmask) {
1256     Interrupt (intr);
1257     regs.stopped = 0;
1258     regs.spcflags &= ~SPCFLAG_STOP;
1259     }
1260     }
1261     }
1262     if (regs.spcflags & SPCFLAG_TRACE)
1263     do_trace ();
1264    
1265     if (regs.spcflags & SPCFLAG_DOINT) {
1266     int intr = intlev ();
1267     regs.spcflags &= ~SPCFLAG_DOINT;
1268     if (intr != -1 && intr > regs.intmask) {
1269     Interrupt (intr);
1270     regs.stopped = 0;
1271     }
1272     }
1273     if (regs.spcflags & SPCFLAG_INT) {
1274     regs.spcflags &= ~SPCFLAG_INT;
1275     regs.spcflags |= SPCFLAG_DOINT;
1276     }
1277     if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1278     regs.spcflags &= ~(SPCFLAG_BRK | SPCFLAG_MODE_CHANGE);
1279     return 1;
1280     }
1281     return 0;
1282     }
1283    
1284     static void m68k_run_1 (void)
1285     {
1286 cebix 1.4 for (;;) {
1287     uae_u32 opcode = GET_OPCODE;
1288 gbeauche 1.10 #if FLIGHT_RECORDER
1289     record_step(m68k_getpc());
1290     #endif
1291 cebix 1.4 (*cpufunctbl[opcode])(opcode);
1292     if (regs.spcflags) {
1293     if (do_specialties())
1294     return;
1295     }
1296 cebix 1.1 }
1297     }
1298    
1299     #define m68k_run1 m68k_run_1
1300    
1301     int in_m68k_go = 0;
1302    
1303     void m68k_go (int may_quit)
1304     {
1305     // m68k_go() must be reentrant for Execute68k() and Execute68kTrap() to work
1306     /*
1307     if (in_m68k_go || !may_quit) {
1308     write_log("Bug! m68k_go is not reentrant.\n");
1309     abort();
1310     }
1311     */
1312     in_m68k_go++;
1313     for (;;) {
1314     if (quit_program > 0) {
1315     if (quit_program == 1)
1316     break;
1317     quit_program = 0;
1318     m68k_reset ();
1319     }
1320     m68k_run1();
1321     }
1322     if (debugging) {
1323     uaecptr nextpc;
1324     m68k_dumpstate(&nextpc);
1325     exit(1);
1326     }
1327     in_m68k_go--;
1328     }
1329    
1330     static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1331     {
1332     uae_u32 opcode, val;
1333     struct instr *dp;
1334    
1335     opcode = get_iword_1(0);
1336     last_op_for_exception_3 = opcode;
1337     m68kpc_offset = 2;
1338    
1339     if (cpufunctbl[cft_map (opcode)] == op_illg_1) {
1340     opcode = 0x4AFC;
1341     }
1342     dp = table68k + opcode;
1343    
1344     if (dp->suse) {
1345     if (!verify_ea (dp->sreg, (amodes)dp->smode, (wordsizes)dp->size, &val)) {
1346     Exception (3, 0);
1347     return;
1348     }
1349     }
1350     if (dp->duse) {
1351     if (!verify_ea (dp->dreg, (amodes)dp->dmode, (wordsizes)dp->size, &val)) {
1352     Exception (3, 0);
1353     return;
1354     }
1355     }
1356     }
1357    
1358     void m68k_disasm (uaecptr addr, uaecptr *nextpc, int cnt)
1359     {
1360     uaecptr newpc = 0;
1361     m68kpc_offset = addr - m68k_getpc ();
1362     while (cnt-- > 0) {
1363     char instrname[20],*ccpt;
1364     int opwords;
1365     uae_u32 opcode;
1366     struct mnemolookup *lookup;
1367     struct instr *dp;
1368     printf ("%08lx: ", m68k_getpc () + m68kpc_offset);
1369     for (opwords = 0; opwords < 5; opwords++){
1370     printf ("%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1371     }
1372     opcode = get_iword_1 (m68kpc_offset);
1373     m68kpc_offset += 2;
1374     if (cpufunctbl[cft_map (opcode)] == op_illg_1) {
1375     opcode = 0x4AFC;
1376     }
1377     dp = table68k + opcode;
1378     for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1379     ;
1380    
1381     strcpy (instrname, lookup->name);
1382     ccpt = strstr (instrname, "cc");
1383     if (ccpt != 0) {
1384     strncpy (ccpt, ccnames[dp->cc], 2);
1385     }
1386     printf ("%s", instrname);
1387     switch (dp->size){
1388     case sz_byte: printf (".B "); break;
1389     case sz_word: printf (".W "); break;
1390     case sz_long: printf (".L "); break;
1391     default: printf (" "); break;
1392     }
1393    
1394     if (dp->suse) {
1395     newpc = m68k_getpc () + m68kpc_offset;
1396     newpc += ShowEA (dp->sreg, (amodes)dp->smode, (wordsizes)dp->size, 0);
1397     }
1398     if (dp->suse && dp->duse)
1399     printf (",");
1400     if (dp->duse) {
1401     newpc = m68k_getpc () + m68kpc_offset;
1402     newpc += ShowEA (dp->dreg, (amodes)dp->dmode, (wordsizes)dp->size, 0);
1403     }
1404     if (ccpt != 0) {
1405     if (cctrue(dp->cc))
1406     printf (" == %08lx (TRUE)", newpc);
1407     else
1408     printf (" == %08lx (FALSE)", newpc);
1409     } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1410     printf (" == %08lx", newpc);
1411     printf ("\n");
1412     }
1413     if (nextpc)
1414     *nextpc = m68k_getpc () + m68kpc_offset;
1415     }
1416    
1417     void m68k_dumpstate (uaecptr *nextpc)
1418     {
1419     int i;
1420     for (i = 0; i < 8; i++){
1421     printf ("D%d: %08lx ", i, m68k_dreg(regs, i));
1422     if ((i & 3) == 3) printf ("\n");
1423     }
1424     for (i = 0; i < 8; i++){
1425     printf ("A%d: %08lx ", i, m68k_areg(regs, i));
1426     if ((i & 3) == 3) printf ("\n");
1427     }
1428     if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1429     if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1430     if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1431     printf ("USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1432     regs.usp,regs.isp,regs.msp,regs.vbr);
1433     printf ("T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1434     regs.t1, regs.t0, regs.s, regs.m,
1435     GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1436     for (i = 0; i < 8; i++){
1437     printf ("FP%d: %g ", i, regs.fp[i]);
1438     if ((i & 3) == 3) printf ("\n");
1439     }
1440     printf ("N=%d Z=%d I=%d NAN=%d\n",
1441     (regs.fpsr & 0x8000000) != 0,
1442     (regs.fpsr & 0x4000000) != 0,
1443     (regs.fpsr & 0x2000000) != 0,
1444     (regs.fpsr & 0x1000000) != 0);
1445    
1446     m68k_disasm(m68k_getpc (), nextpc, 1);
1447     if (nextpc)
1448     printf ("next PC: %08lx\n", *nextpc);
1449     }