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#ifdef OPTIMIZED_FLAGS |
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#if defined(__i386__) && defined(X86_ASSEMBLY) |
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#if (defined(__i386__) && defined(X86_ASSEMBLY)) || (defined(__x86_64__) && defined(X86_64_ASSEMBLY)) |
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#ifndef SAHF_SETO_PROFITABLE |
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/* PUSH/POP instructions are naturally 64-bit sized on x86-64, thus |
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unsigned long hereunder is either 64-bit or 32-bit wide depending |
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on the target. */ |
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struct flag_struct { |
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uae_u32 cznv; |
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uae_u32 x; |
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unsigned long cznv; |
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unsigned long x; |
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}; |
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#define FLAGVAL_Z 0x40 |
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#define FLAGVAL_N 0x80 |
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#define SET_ZFLG(y) (regflags.cznv = (regflags.cznv & ~0x40) | (((y) & 1) << 6)) |
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#define SET_CFLG(y) (regflags.cznv = (regflags.cznv & ~1) | ((y) & 1)) |
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#define SET_VFLG(y) (regflags.cznv = (regflags.cznv & ~0x800) | (((y) & 1) << 11)) |
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#define SET_NFLG(y) (regflags.cznv = (regflags.cznv & ~0x80) | (((y) & 1) << 7)) |
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#define SET_ZFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~0x40) | (((y) & 1) << 6)) |
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#define SET_CFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~1) | ((y) & 1)) |
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#define SET_VFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~0x800) | (((y) & 1) << 11)) |
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#define SET_NFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~0x80) | (((y) & 1) << 7)) |
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#define SET_XFLG(y) (regflags.x = (y)) |
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#define GET_ZFLG ((regflags.cznv >> 6) & 1) |
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#define optflag_testl(v) \ |
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__asm__ __volatile__ ("andl %1,%1\n\t" \ |
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"pushfl\n\t" \ |
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"popl %0\n\t" \ |
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"pushf\n\t" \ |
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"pop %0\n\t" \ |
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: "=r" (regflags.cznv) : "r" (v) : "cc") |
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#define optflag_testw(v) \ |
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__asm__ __volatile__ ("andw %w1,%w1\n\t" \ |
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"pushfl\n\t" \ |
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"popl %0\n\t" \ |
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"pushf\n\t" \ |
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"pop %0\n\t" \ |
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: "=r" (regflags.cznv) : "r" (v) : "cc") |
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#define optflag_testb(v) \ |
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__asm__ __volatile__ ("andb %b1,%b1\n\t" \ |
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"pushfl\n\t" \ |
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"popl %0\n\t" \ |
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"pushf\n\t" \ |
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"pop %0\n\t" \ |
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: "=r" (regflags.cznv) : "q" (v) : "cc") |
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#define optflag_addl(v, s, d) do { \ |
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__asm__ __volatile__ ("addl %k2,%k1\n\t" \ |
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"pushfl\n\t" \ |
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"popl %0\n\t" \ |
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"pushf\n\t" \ |
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"pop %0\n\t" \ |
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: "=r" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "cc"); \ |
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COPY_CARRY; \ |
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} while (0) |
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#define optflag_addw(v, s, d) do { \ |
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__asm__ __volatile__ ("addw %w2,%w1\n\t" \ |
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"pushfl\n\t" \ |
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"popl %0\n\t" \ |
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"pushf\n\t" \ |
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"pop %0\n\t" \ |
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: "=r" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "cc"); \ |
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COPY_CARRY; \ |
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} while (0) |
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#define optflag_addb(v, s, d) do { \ |
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__asm__ __volatile__ ("addb %b2,%b1\n\t" \ |
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"pushfl\n\t" \ |
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"popl %0\n\t" \ |
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"pushf\n\t" \ |
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"pop %0\n\t" \ |
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: "=r" (regflags.cznv), "=q" (v) : "qmi" (s), "1" (d) : "cc"); \ |
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COPY_CARRY; \ |
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} while (0) |
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#define optflag_subl(v, s, d) do { \ |
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__asm__ __volatile__ ("subl %k2,%k1\n\t" \ |
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"pushfl\n\t" \ |
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"popl %0\n\t" \ |
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"pushf\n\t" \ |
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"pop %0\n\t" \ |
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: "=r" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "cc"); \ |
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COPY_CARRY; \ |
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} while (0) |
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#define optflag_subw(v, s, d) do { \ |
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__asm__ __volatile__ ("subw %w2,%w1\n\t" \ |
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"pushfl\n\t" \ |
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"popl %0\n\t" \ |
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"pushf\n\t" \ |
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"pop %0\n\t" \ |
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: "=r" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "cc"); \ |
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COPY_CARRY; \ |
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} while (0) |
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#define optflag_subb(v, s, d) do { \ |
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__asm__ __volatile__ ("subb %b2,%b1\n\t" \ |
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"pushfl\n\t" \ |
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"popl %0\n\t" \ |
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"pushf\n\t" \ |
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"pop %0\n\t" \ |
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: "=r" (regflags.cznv), "=q" (v) : "qmi" (s), "1" (d) : "cc"); \ |
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COPY_CARRY; \ |
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} while (0) |
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#define optflag_cmpl(s, d) \ |
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__asm__ __volatile__ ("cmpl %k1,%k2\n\t" \ |
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"pushfl\n\t" \ |
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"popl %0\n\t" \ |
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"pushf\n\t" \ |
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"pop %0\n\t" \ |
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: "=r" (regflags.cznv) : "rmi" (s), "r" (d) : "cc") |
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#define optflag_cmpw(s, d) \ |
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__asm__ __volatile__ ("cmpw %w1,%w2\n\t" \ |
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"pushfl\n\t" \ |
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"popl %0\n\t" \ |
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"pushf\n\t" \ |
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"pop %0\n\t" \ |
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: "=r" (regflags.cznv) : "rmi" (s), "r" (d) : "cc") |
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#define optflag_cmpb(s, d) \ |
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__asm__ __volatile__ ("cmpb %b1,%b2\n\t" \ |
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"pushfl\n\t" \ |
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"popl %0\n\t" \ |
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"pushf\n\t" \ |
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"pop %0\n\t" \ |
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: "=r" (regflags.cznv) : "qmi" (s), "q" (d) : "cc") |
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#else |