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root/cebix/BasiliskII/src/uae_cpu/gencpu.c

Comparing BasiliskII/src/uae_cpu/gencpu.c (file contents):
Revision 1.7 by cebix, 1999-10-28T16:00:23Z vs.
Revision 1.20 by gbeauche, 2002-11-02T18:13:27Z

#	Line 221 | Line 221 | static void sync_m68k_pc (void)
221		}
222
223		/* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
224	<	* the calling routine handles Apdi and Aipi modes. */
224	>	* the calling routine handles Apdi and Aipi modes.
225	>	* gb-- movem == 2 means the same thing but for a MOVE16 instruction */
226		static void genamode (amodes mode, char *reg, wordsizes size, char *name, int getv, int movem)
227		{
228		start_brace ();
#	Line 232 | Line 233 | static void genamode (amodes mode, char
233		if (getv == 1)
234		switch (size) {
235		case sz_byte:
236	<	#ifdef AMIGA
236	>	#if defined(AMIGA) && !defined(WARPUP)
237		/* sam: I don't know why gcc.2.7.2.1 produces a code worse */
238		/* if it is not done like that: */
239		printf ("\tuae_s8 %s = ((uae_u8*)&m68k_dreg(regs, %s))[3];\n", name, reg);
#	Line 241 | Line 242 | static void genamode (amodes mode, char
242		#endif
243		break;
244		case sz_word:
245	<	#ifdef AMIGA
245	>	#if defined(AMIGA) && !defined(WARPUP)
246		printf ("\tuae_s16 %s = ((uae_s16*)&m68k_dreg(regs, %s))[1];\n", name, reg);
247		#else
248		printf ("\tuae_s16 %s = m68k_dreg(regs, %s);\n", name, reg);
#	Line 714 | Line 715 | static void genflags_normal (flagtypes t
715
716		static void genflags (flagtypes type, wordsizes size, char *value, char *src, char *dst)
717		{
718	<	#ifdef SPARC_V8_ASSEMBLY
719	<	switch(type)
720	<	{
721	<	case flag_add:
721	<	start_brace();
722	<	printf("\tuae_u32 %s;\n", value);
723	<	switch(size)
724	<	{
725	<	case sz_byte:
726	<	printf("\t%s = sparc_v8_flag_add_8(M68K_FLAGS_ADDR, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
727	<	break;
728	<	case sz_word:
729	<	printf("\t%s = sparc_v8_flag_add_16(M68K_FLAGS_ADDR, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
730	<	break;
731	<	case sz_long:
732	<	printf("\t%s = sparc_v8_flag_add_32(M68K_FLAGS_ADDR, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
733	<	break;
734	<	}
735	<	return;
736	<	}
737	<	#elif defined(SPARC_V9_ASSEMBLY)
738	<	switch(type)
739	<	{
740	<	case flag_add:
741	<	start_brace();
742	<	printf("\tuae_u32 %s;\n", value);
743	<	switch(size)
744	<	{
745	<	case sz_byte:
746	<	printf("\t%s = sparc_v9_flag_add_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
747	<	break;
748	<	case sz_word:
749	<	printf("\t%s = sparc_v9_flag_add_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
750	<	break;
751	<	case sz_long:
752	<	printf("\t%s = sparc_v9_flag_add_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
753	<	break;
754	<	}
755	<	return;
756	<
757	<	case flag_sub:
758	<	start_brace();
759	<	printf("\tuae_u32 %s;\n", value);
760	<	switch(size)
761	<	{
762	<	case sz_byte:
763	<	printf("\t%s = sparc_v9_flag_sub_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
764	<	break;
765	<	case sz_word:
766	<	printf("\t%s = sparc_v9_flag_sub_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
767	<	break;
768	<	case sz_long:
769	<	printf("\t%s = sparc_v9_flag_sub_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
770	<	break;
771	<	}
772	<	return;
773	<
774	<	case flag_cmp:
775	<	switch(size)
776	<	{
777	<	case sz_byte:
778	<	printf("\tsparc_v9_flag_cmp_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
779	<	break;
780	<	case sz_word:
781	<	printf("\tsparc_v9_flag_cmp_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
782	<	break;
783	<	case sz_long:
784	<	printf("\tsparc_v9_flag_cmp_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
785	<	break;
786	<	}
787	<	return;
788	<
789	<	case flag_logical:
790	<	if (strcmp(value, "0") == 0) {
791	<	printf("\tregflags.nzvc = 0x04;\n");
792	<	} else {
793	<	switch(size) {
794	<	case sz_byte:
795	<	printf("\tsparc_v9_flag_test_8(&regflags, (uae_u32)(%s));\n", value);
796	<	break;
797	<	case sz_word:
798	<	printf("\tsparc_v9_flag_test_16(&regflags, (uae_u32)(%s));\n", value);
799	<	break;
800	<	case sz_long:
801	<	printf("\tsparc_v9_flag_test_32(&regflags, (uae_u32)(%s));\n", value);
802	<	break;
803	<	}
804	<	}
805	<	return;
806	<
807	<	#if 0
808	<	case flag_logical_noclobber:
809	<	printf("\t{uae_u32 old_flags = regflags.nzvc & ~0x0C;\n");
810	<	if (strcmp(value, "0") == 0) {
811	<	printf("\tregflags.nzvc = old_flags | 0x04;\n");
812	<	} else {
813	<	switch(size) {
814	<	case sz_byte:
815	<	printf("\tsparc_v9_flag_test_8(&regflags, (uae_u32)(%s));\n", value);
816	<	break;
817	<	case sz_word:
818	<	printf("\tsparc_v9_flag_test_16(&regflags, (uae_u32)(%s));\n", value);
819	<	break;
820	<	case sz_long:
821	<	printf("\tsparc_v9_flag_test_32(&regflags, (uae_u32)(%s));\n", value);
822	<	break;
823	<	}
824	<	printf("\tregflags.nzvc |= old_flags;\n");
825	<	}
826	<	printf("\t}\n");
827	<	return;
828	<	#endif
829	<	}
830	<	#elif defined(X86_ASSEMBLY)
718	>	/* Temporarily deleted 68k/ARM flag optimizations.  I'd prefer to have
719	>	them in the appropriate m68k.h files and use just one copy of this
720	>	code here.  The API can be changed if necessary.  */
721	>	#ifdef OPTIMIZED_FLAGS
722		switch (type) {
723		case flag_add:
724		case flag_sub:
725		start_brace ();
726		printf ("\tuae_u32 %s;\n", value);
727		break;
837	–
728		default:
729		break;
730		}
#	Line 842 | Line 732 | static void genflags (flagtypes type, wo
732		/* At least some of those casts are fairly important! */
733		switch (type) {
734		case flag_logical_noclobber:
735	<	printf ("\t{uae_u32 oldcznv = regflags.cznv & ~0xC0;\n");
735	>	printf ("\t{uae_u32 oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
736		if (strcmp (value, "0") == 0) {
737	<	printf ("\tregflags.cznv = olcznv | 64;\n");
737	>	printf ("\tSET_CZNV (olcznv | FLAGVAL_Z);\n");
738		} else {
739		switch (size) {
740	<	case sz_byte: printf ("\tx86_flag_testb ((uae_s8)(%s));\n", value); break;
741	<	case sz_word: printf ("\tx86_flag_testw ((uae_s16)(%s));\n", value); break;
742	<	case sz_long: printf ("\tx86_flag_testl ((uae_s32)(%s));\n", value); break;
740	>	case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
741	>	case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
742	>	case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
743		}
744	<	printf ("\tregflags.cznv |= oldcznv;\n");
744	>	printf ("\tIOR_CZNV (oldcznv);\n");
745		}
746		printf ("\t}\n");
747		return;
748	+
749		case flag_logical:
750		if (strcmp (value, "0") == 0) {
751	<	printf ("\tregflags.cznv = 64;\n");
751	>	printf ("\tSET_CZNV (FLAGVAL_Z);\n");
752		} else {
753		switch (size) {
754	<	case sz_byte: printf ("\tx86_flag_testb ((uae_s8)(%s));\n", value); break;
755	<	case sz_word: printf ("\tx86_flag_testw ((uae_s16)(%s));\n", value); break;
756	<	case sz_long: printf ("\tx86_flag_testl ((uae_s32)(%s));\n", value); break;
754	>	case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
755	>	case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
756	>	case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
757		}
758		}
759		return;
760
761		case flag_add:
762		switch (size) {
763	<	case sz_byte: printf ("\tx86_flag_addb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
764	<	case sz_word: printf ("\tx86_flag_addw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
765	<	case sz_long: printf ("\tx86_flag_addl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
763	>	case sz_byte: printf ("\toptflag_addb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
764	>	case sz_word: printf ("\toptflag_addw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
765	>	case sz_long: printf ("\toptflag_addl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
766		}
767		return;
768
769		case flag_sub:
770		switch (size) {
771	<	case sz_byte: printf ("\tx86_flag_subb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
772	<	case sz_word: printf ("\tx86_flag_subw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
773	<	case sz_long: printf ("\tx86_flag_subl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
771	>	case sz_byte: printf ("\toptflag_subb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
772	>	case sz_word: printf ("\toptflag_subw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
773	>	case sz_long: printf ("\toptflag_subl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
774		}
775		return;
776
777		case flag_cmp:
778		switch (size) {
779	<	case sz_byte: printf ("\tx86_flag_cmpb ((uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
780	<	case sz_word: printf ("\tx86_flag_cmpw ((uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
781	<	case sz_long: printf ("\tx86_flag_cmpl ((uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
779	>	case sz_byte: printf ("\toptflag_cmpb ((uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
780	>	case sz_word: printf ("\toptflag_cmpw ((uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
781	>	case sz_long: printf ("\toptflag_cmpl ((uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
782		}
783		return;
784
785		default:
786		break;
787		}
897	–	#elif defined(M68K_FLAG_OPT)
898	–	/* sam: here I'm cloning what X86_ASSEMBLY does */
899	–	#define EXT(size)  (size==sz_byte?"b":(size==sz_word?"w":"l"))
900	–	#define CAST(size) (size==sz_byte?"uae_s8":(size==sz_word?"uae_s16":"uae_s32"))
901	–	switch (type) {
902	–	case flag_add:
903	–	case flag_sub:
904	–	start_brace ();
905	–	printf ("\tuae_u32 %s;\n", value);
906	–	break;
907	–
908	–	default:
909	–	break;
910	–	}
911	–
912	–	switch (type) {
913	–	case flag_logical:
914	–	if (strcmp (value, "0") == 0) {
915	–	printf ("\t*(uae_u16 *)&regflags = 4;\n");  /* Z = 1 */
916	–	} else {
917	–	printf ("\tm68k_flag_tst (%s, (%s)(%s));\n",
918	–	EXT (size), CAST (size), value);
919	–	}
920	–	return;
921	–
922	–	case flag_add:
923	–	printf ("\t{uae_u16 ccr;\n");
924	–	printf ("\tm68k_flag_add (%s, (%s)%s, (%s)(%s), (%s)(%s));\n",
925	–	EXT (size), CAST (size), value, CAST (size), src, CAST (size), dst);
926	–	printf ("\t((uae_u16*)&regflags)[1]=((uae_u16*)&regflags)[0]=ccr;}\n");
927	–	return;
928	–
929	–	case flag_sub:
930	–	printf ("\t{uae_u16 ccr;\n");
931	–	printf ("\tm68k_flag_sub (%s, (%s)%s, (%s)(%s), (%s)(%s));\n",
932	–	EXT (size), CAST (size), value, CAST (size), src, CAST (size), dst);
933	–	printf ("\t((uae_u16*)&regflags)[1]=((uae_u16*)&regflags)[0]=ccr;}\n");
934	–	return;
935	–
936	–	case flag_cmp:
937	–	printf ("\tm68k_flag_cmp (%s, (%s)(%s), (%s)(%s));\n",
938	–	EXT (size), CAST (size), src, CAST (size), dst);
939	–	return;
940	–
941	–	default:
942	–	break;
943	–	}
944	–	#elif defined(ACORN_FLAG_OPT) && defined(__GNUC_MINOR__)
945	–	/*
946	–	* This is new. Might be quite buggy.
947	–	*/
948	–	switch (type) {
949	–	case flag_av:
950	–	case flag_sv:
951	–	case flag_zn:
952	–	case flag_addx:
953	–	case flag_subx:
954	–	break;
955	–
956	–	case flag_logical:
957	–	if (strcmp (value, "0") == 0) {
958	–	/* v=c=n=0 z=1 */
959	–	printf ("\t*(ULONG*)&regflags = 0x40000000;\n");
960	–	return;
961	–	} else {
962	–	start_brace ();
963	–	switch (size) {
964	–	case sz_byte:
965	–	printf ("\tUBYTE ccr;\n");
966	–	printf ("\tULONG shift;\n");
967	–	printf ("\t__asm__(\"mov %%2,%%1,lsl#24\n\ttst %%2,%%2\n\tmov %%0,r15,lsr#24\n\tbic %%0,%%0,#0x30\"\n"
968	–	"\t: \"=r\" (ccr) : \"r\" (%s), \"r\" (shift) : \"cc\" );\n", value);
969	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
970	–	return;
971	–	case sz_word:
972	–	printf ("\tUBYTE ccr;\n");
973	–	printf ("\tULONG shift;\n");
974	–	printf ("\t__asm__(\"mov %%2,%%1,lsl#16\n\ttst %%2,%%2\n\tmov %%0,r15,lsr#24\n\tbic %%0,%%0,#0x30\"\n"
975	–	"\t: \"=r\" (ccr) : \"r\" ((WORD)%s), \"r\" (shift) : \"cc\" );\n", value);
976	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
977	–	return;
978	–	case sz_long:
979	–	printf ("\tUBYTE ccr;\n");
980	–	printf ("\t__asm__(\"tst %%1,%%1\n\tmov %%0,r15,lsr#24\n\tbic %%0,%%0,#0x30\"\n"
981	–	"\t: \"=r\" (ccr) : \"r\" ((LONG)%s) : \"cc\" );\n", value);
982	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
983	–	return;
984	–	}
985	–	}
986	–	break;
987	–	case flag_add:
988	–	if (strcmp (dst, "0") == 0) {
989	–	printf ("/* Error! Hier muss Peter noch was machen !!! (ADD-Flags) */");
990	–	} else {
991	–	start_brace ();
992	–	switch (size) {
993	–	case sz_byte:
994	–	printf ("\tULONG ccr, shift, %s;\n", value);
995	–	printf ("\t__asm__(\"mov %%4,%%3,lsl#24\n\tadds %%0,%%4,%%2,lsl#24\n\tmov %%0,%%0,asr#24\n\tmov %%1,r15\n\torr %%1,%%1,%%1,lsr#29\"\n"
996	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" (%s), \"r\" (%s), \"r\" (shift) : \"cc\" );\n", value, src, dst);
997	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
998	–	return;
999	–	case sz_word:
1000	–	printf ("\tULONG ccr, shift, %s;\n", value);
1001	–	printf ("\t__asm__(\"mov %%4,%%3,lsl#16\n\tadds %%0,%%4,%%2,lsl#16\n\tmov %%0,%%0,asr#16\n\tmov %%1,r15\n\torr %%1,%%1,%%1,lsr#29\"\n"
1002	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" ((WORD)%s), \"r\" ((WORD)%s), \"r\" (shift) : \"cc\" );\n", value, src, dst);
1003	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1004	–	return;
1005	–	case sz_long:
1006	–	printf ("\tULONG ccr, %s;\n", value);
1007	–	printf ("\t__asm__(\"adds %%0,%%3,%%2\n\tmov %%1,r15\n\torr %%1,%%1,%%1,lsr#29\"\n"
1008	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" ((LONG)%s), \"r\" ((LONG)%s) : \"cc\" );\n", value, src, dst);
1009	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1010	–	return;
1011	–	}
1012	–	}
1013	–	break;
1014	–	case flag_sub:
1015	–	if (strcmp (dst, "0") == 0) {
1016	–	printf ("/* Error! Hier muss Peter noch was machen !!! (SUB-Flags) */");
1017	–	} else {
1018	–	start_brace ();
1019	–	switch (size) {
1020	–	case sz_byte:
1021	–	printf ("\tULONG ccr, shift, %s;\n", value);
1022	–	printf ("\t__asm__(\"mov %%4,%%3,lsl#24\n\tsubs %%0,%%4,%%2,lsl#24\n\tmov %%0,%%0,asr#24\n\tmov %%1,r15\n\teor %%1,%%1,#0x20000000\n\torr %%1,%%1,%%1,lsr#29\"\n"
1023	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" (%s), \"r\" (%s), \"r\" (shift) : \"cc\" );\n", value, src, dst);
1024	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1025	–	return;
1026	–	case sz_word:
1027	–	printf ("\tULONG ccr, shift, %s;\n", value);
1028	–	printf ("\t__asm__(\"mov %%4,%%3,lsl#16\n\tsubs %%0,%%4,%%2,lsl#16\n\tmov %%0,%%0,asr#16\n\tmov %%1,r15\n\teor %%1,%%1,#0x20000000\n\torr %%1,%%1,%%1,lsr#29\"\n"
1029	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" ((WORD)%s), \"r\" ((WORD)%s), \"r\" (shift) : \"cc\" );\n", value, src, dst);
1030	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1031	–	return;
1032	–	case sz_long:
1033	–	printf ("\tULONG ccr, %s;\n", value);
1034	–	printf ("\t__asm__(\"subs %%0,%%3,%%2\n\tmov %%1,r15\n\teor %%1,%%1,#0x20000000\n\torr %%1,%%1,%%1,lsr#29\"\n"
1035	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" ((LONG)%s), \"r\" ((LONG)%s) : \"cc\" );\n", value, src, dst);
1036	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1037	–	return;
1038	–	}
1039	–	}
1040	–	break;
1041	–	case flag_cmp:
1042	–	if (strcmp (dst, "0") == 0) {
1043	–	printf ("/*Error! Hier muss Peter noch was machen !!! (CMP-Flags)*/");
1044	–	} else {
1045	–	start_brace ();
1046	–	switch (size) {
1047	–	case sz_byte:
1048	–	printf ("\tULONG shift, ccr;\n");
1049	–	printf ("\t__asm__(\"mov %%3,%%2,lsl#24\n\tcmp %%3,%%1,lsl#24\n\tmov %%0,r15,lsr#24\n\teor %%0,%%0,#0x20\"\n"
1050	–	"\t: \"=r\" (ccr) : \"r\" (%s), \"r\" (%s), \"r\" (shift) : \"cc\" );\n", src, dst);
1051	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1052	–	return;
1053	–	case sz_word:
1054	–	printf ("\tULONG shift, ccr;\n");
1055	–	printf ("\t__asm__(\"mov %%3,%%2,lsl#16\n\tcmp %%3,%%1,lsl#16\n\tmov %%0,r15,lsr#24\n\teor %%0,%%0,#0x20\"\n"
1056	–	"\t: \"=r\" (ccr) : \"r\" ((WORD)%s), \"r\" ((WORD)%s), \"r\" (shift) : \"cc\" );\n", src, dst);
1057	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1058	–	return;
1059	–	case sz_long:
1060	–	printf ("\tULONG ccr;\n");
1061	–	printf ("\t__asm__(\"cmp %%2,%%1\n\tmov %%0,r15,lsr#24\n\teor %%0,%%0,#0x20\"\n"
1062	–	"\t: \"=r\" (ccr) : \"r\" ((LONG)%s), \"r\" ((LONG)%s) : \"cc\" );\n", src, dst);
1063	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1064	–	/*printf ("\tprintf (\"%%08x %%08x %%08x\\n\", %s, %s, *((ULONG*)&regflags));\n", src, dst); */
1065	–	return;
1066	–	}
1067	–	}
1068	–	break;
1069	–	}
788		#endif
789		genflags_normal (type, size, value, src, dst);
790		}
#	Line 1191 | Line 909 | static void gen_opcode (unsigned long in
909		genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
910		break;
911		case i_SBCD:
1194	–	/* Let's hope this works... */
912		genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
913		genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
914		start_brace ();
915		printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
916		printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
917	<	printf ("\tuae_u16 newv;\n");
918	<	printf ("\tint cflg;\n");
919	<	printf ("\tif (newv_lo > 9) { newv_lo-=6; newv_hi-=0x10; }\n");
920	<	printf ("\tnewv = newv_hi + (newv_lo & 0xF);");
921	<	printf ("\tSET_CFLG (cflg = (newv_hi & 0x1F0) > 0x90);\n");
917	>	printf ("\tuae_u16 newv, tmp_newv;\n");
918	>	printf ("\tint bcd = 0;\n");
919	>	printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
920	>	printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
921	>	printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
922	>	printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);\n");
923		duplicate_carry ();
1206	–	printf ("\tif (cflg) newv -= 0x60;\n");
924		genflags (flag_zn, curi->size, "newv", "", "");
925	<	genflags (flag_sv, curi->size, "newv", "src", "dst");
925	>	printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
926		genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
927		break;
928		case i_ADD:
#	Line 1237 | Line 954 | static void gen_opcode (unsigned long in
954		start_brace ();
955		printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);\n");
956		printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
957	<	printf ("\tuae_u16 newv;\n");
957	>	printf ("\tuae_u16 newv, tmp_newv;\n");
958		printf ("\tint cflg;\n");
959	<	printf ("\tif (newv_lo > 9) { newv_lo +=6; }\n");
960	<	printf ("\tnewv = newv_hi + newv_lo;");
961	<	printf ("\tSET_CFLG (cflg = (newv & 0x1F0) > 0x90);\n");
1245	<	duplicate_carry ();
959	>	printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
960	>	printf ("\tif (newv_lo > 9) { newv += 6; }\n");
961	>	printf ("\tcflg = (newv & 0x3F0) > 0x90;\n");
962		printf ("\tif (cflg) newv += 0x60;\n");
963	+	printf ("\tSET_CFLG (cflg);\n");
964	+	duplicate_carry ();
965		genflags (flag_zn, curi->size, "newv", "", "");
966	<	genflags (flag_sv, curi->size, "newv", "src", "dst");
966	>	printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
967		genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
968		break;
969		case i_NEG:
#	Line 1269 | Line 987 | static void gen_opcode (unsigned long in
987		printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n");
988		printf ("\tuae_u16 newv;\n");
989		printf ("\tint cflg;\n");
990	<	printf ("\tif (newv_lo > 9) { newv_lo-=6; newv_hi-=0x10; }\n");
991	<	printf ("\tnewv = newv_hi + (newv_lo & 0xF);");
992	<	printf ("\tSET_CFLG (cflg = (newv_hi & 0x1F0) > 0x90);\n");
1275	<	duplicate_carry();
990	>	printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
991	>	printf ("\tnewv = newv_hi + newv_lo;\n");
992	>	printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
993		printf ("\tif (cflg) newv -= 0x60;\n");
994	+	printf ("\tSET_CFLG (cflg);\n");
995	+	duplicate_carry();
996		genflags (flag_zn, curi->size, "newv", "", "");
997		genastore ("newv", curi->smode, "srcreg", curi->size, "src");
998		break;
#	Line 1310 | Line 1029 | static void gen_opcode (unsigned long in
1029		else
1030		printf ("\tsrc &= 31;\n");
1031		printf ("\tdst ^= (1 << src);\n");
1032	<	printf ("\tSET_ZFLG ((dst & (1 << src)) >> src);\n");
1032	>	printf ("\tSET_ZFLG (((uae_u32)dst & (1 << src)) >> src);\n");
1033		genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1034		break;
1035		case i_BCLR:
#	Line 1481 | Line 1200 | static void gen_opcode (unsigned long in
1200		printf ("\tif ((format & 0xF000) == 0x0000) { break; }\n");
1201		printf ("\telse if ((format & 0xF000) == 0x1000) { ; }\n");
1202		printf ("\telse if ((format & 0xF000) == 0x2000) { m68k_areg(regs, 7) += 4; break; }\n");
1203	+	/* gb-- the next two lines are deleted in Bernie's gencpu.c */
1204		printf ("\telse if ((format & 0xF000) == 0x3000) { m68k_areg(regs, 7) += 4; break; }\n");
1205		printf ("\telse if ((format & 0xF000) == 0x7000) { m68k_areg(regs, 7) += 52; break; }\n");
1206		printf ("\telse if ((format & 0xF000) == 0x8000) { m68k_areg(regs, 7) += 50; break; }\n");
#	Line 1499 | Line 1219 | static void gen_opcode (unsigned long in
1219		m68k_pc_offset = 0;
1220		break;
1221		case i_RTD:
1502	–	printf ("\tcompiler_flush_jsr_stack();\n");
1222		genamode (Aipi, "7", sz_long, "pc", 1, 0);
1223		genamode (curi->smode, "srcreg", curi->size, "offs", 1, 0);
1224		printf ("\tm68k_areg(regs, 7) += offs;\n");
#	Line 1533 | Line 1252 | static void gen_opcode (unsigned long in
1252		need_endlabel = 1;
1253		break;
1254		case i_RTR:
1536	–	printf ("\tcompiler_flush_jsr_stack();\n");
1255		printf ("\tMakeSR();\n");
1256		genamode (Aipi, "7", sz_word, "sr", 1, 0);
1257		genamode (Aipi, "7", sz_long, "pc", 1, 0);
#	Line 1571 | Line 1289 | static void gen_opcode (unsigned long in
1289		m68k_pc_offset = 0;
1290		break;
1291		case i_Bcc:
1292	+	if (0 && !using_prefetch && !using_exception_3 && (cpu_level >= 2)) {
1293	+	/* gb-- variant probably more favorable to compiler optimizations
1294	+	also assumes no prefetch buffer is used
1295	+	Hmm, that would make sense with processors capable of conditional moves */
1296	+	if (curi->size == sz_long && next_cpu_level < 1)
1297	+	next_cpu_level = 1;
1298	+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1299	+	printf ("\tm68k_incpc (cctrue(%d) ? ((uae_s32)src + 2) : %d);\n", curi->cc, m68k_pc_offset);
1300	+	m68k_pc_offset = 0;
1301	+	}
1302	+	else {
1303	+	/* original code for branch instructions */
1304		if (curi->size == sz_long) {
1305		if (cpu_level < 2) {
1306		printf ("\tm68k_incpc(2);\n");
#	Line 1594 | Line 1324 | static void gen_opcode (unsigned long in
1324		printf ("\t}\n");
1325		need_endlabel = 1;
1326		}
1597	–	#ifdef USE_COMPILER
1598	–	printf ("\tm68k_setpc_bcc(m68k_getpc() + 2 + (uae_s32)src);\n");
1599	–	#else
1327		printf ("\tm68k_incpc ((uae_s32)src + 2);\n");
1601	–	#endif
1328		fill_prefetch_0 ();
1329	<	printf ("\tgoto %s;\n", endlabelstr);
1329	>	printf ("return;\n");
1330		printf ("didnt_jump:;\n");
1331		need_endlabel = 1;
1332	+	}
1333		break;
1334		case i_LEA:
1335		genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
#	Line 1630 | Line 1357 | static void gen_opcode (unsigned long in
1357		printf ("\t\t}\n");
1358		need_endlabel = 1;
1359		}
1633	–	#ifdef USE_COMPILER
1634	–	printf ("\t\t\tm68k_setpc_bcc(m68k_getpc() + (uae_s32)offs + 2);\n");
1635	–	#else
1360		printf ("\t\t\tm68k_incpc((uae_s32)offs + 2);\n");
1637	–	#endif
1361		fill_prefetch_0 ();
1362	<	printf ("\t\tgoto %s;\n", endlabelstr);
1362	>	printf ("return;\n");
1363		printf ("\t\t}\n");
1364		printf ("\t}\n");
1365		need_endlabel = 1;
#	Line 1651 | Line 1374 | static void gen_opcode (unsigned long in
1374		printf ("\tuaecptr oldpc = m68k_getpc();\n");
1375		genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1376		genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1377	<	printf ("\tif(src == 0) { Exception(5,oldpc); goto %s; } else {\n", endlabelstr);
1377	>	sync_m68k_pc ();
1378	>	/* Clear V flag when dividing by zero - Alcatraz Odyssey demo depends
1379	>	* on this (actually, it's doing a DIVS).  */
1380	>	printf ("\tif (src == 0) { SET_VFLG (0); Exception (5, oldpc); goto %s; } else {\n", endlabelstr);
1381		printf ("\tuae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;\n");
1382		printf ("\tuae_u32 rem = (uae_u32)dst %% (uae_u32)(uae_u16)src;\n");
1383		/* The N flag appears to be set each time there is an overflow.
#	Line 1669 | Line 1395 | static void gen_opcode (unsigned long in
1395		printf ("\tuaecptr oldpc = m68k_getpc();\n");
1396		genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1397		genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1398	<	printf ("\tif(src == 0) { Exception(5,oldpc); goto %s; } else {\n", endlabelstr);
1398	>	sync_m68k_pc ();
1399	>	printf ("\tif (src == 0) { SET_VFLG (0); Exception(5,oldpc); goto %s; } else {\n", endlabelstr);
1400		printf ("\tuae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;\n");
1401		printf ("\tuae_u16 rem = (uae_s32)dst %% (uae_s32)(uae_s16)src;\n");
1402		printf ("\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n");
#	Line 1730 | Line 1457 | static void gen_opcode (unsigned long in
1457		abort ();
1458		}
1459		printf ("\tSET_ZFLG (upper == reg || lower == reg);\n");
1460	<	printf ("\tSET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
1460	>	printf ("\tSET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
1461		printf ("\tif ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc); goto %s; }\n}\n", endlabelstr);
1462		need_endlabel = 1;
1463		break;
#	Line 1929 | Line 1656 | static void gen_opcode (unsigned long in
1656		}
1657		printf ("\tcnt &= 63;\n");
1658		printf ("\tCLEAR_CZNV;\n");
1932	–	if (! source_is_imm1_8 (curi))
1933	–	force_range_for_rox ("cnt", curi->size);
1659		if (source_is_imm1_8 (curi))
1660		printf ("{");
1661	<	else
1661	>	else {
1662	>	force_range_for_rox ("cnt", curi->size);
1663		printf ("\tif (cnt > 0) {\n");
1664	+	}
1665		printf ("\tcnt--;\n");
1666		printf ("\t{\n\tuae_u32 carry;\n");
1667		printf ("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
#	Line 1959 | Line 1686 | static void gen_opcode (unsigned long in
1686		}
1687		printf ("\tcnt &= 63;\n");
1688		printf ("\tCLEAR_CZNV;\n");
1962	–	if (! source_is_imm1_8 (curi))
1963	–	force_range_for_rox ("cnt", curi->size);
1689		if (source_is_imm1_8 (curi))
1690		printf ("{");
1691	<	else
1691	>	else {
1692	>	force_range_for_rox ("cnt", curi->size);
1693		printf ("\tif (cnt > 0) {\n");
1694	+	}
1695		printf ("\tcnt--;\n");
1696		printf ("\t{\n\tuae_u32 carry;\n");
1697		printf ("\tuae_u32 hival = (val << 1) | GET_XFLG;\n");
#	Line 2120 | Line 1847 | static void gen_opcode (unsigned long in
1847		start_brace ();
1848		printf ("\tint regno = (src >> 12) & 15;\n");
1849		printf ("\tuae_u32 *regp = regs.regs + regno;\n");
1850	<	printf ("\tm68k_movec2(src & 0xFFF, regp);\n");
1850	>	printf ("\tif (! m68k_movec2(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
1851		break;
1852		case i_MOVE2C:
1853		genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1854		start_brace ();
1855		printf ("\tint regno = (src >> 12) & 15;\n");
1856		printf ("\tuae_u32 *regp = regs.regs + regno;\n");
1857	<	printf ("\tm68k_move2c(src & 0xFFF, regp);\n");
1857	>	printf ("\tif (! m68k_move2c(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
1858		break;
1859		case i_CAS:
1860		{
#	Line 2267 | Line 1994 | static void gen_opcode (unsigned long in
1994		printf ("\ttmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));\n");
1995		}
1996		printf ("\ttmp >>= (32 - width);\n");
1997	<	printf ("\tSET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);\n");
1997	>	printf ("\tSET_NFLG_ALWAYS (tmp & (1 << (width-1)) ? 1 : 0);\n");
1998		printf ("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
1999		switch (curi->mnemo) {
2000		case i_BFTST:
#	Line 2295 | Line 2022 | static void gen_opcode (unsigned long in
2022		break;
2023		case i_BFINS:
2024		printf ("\ttmp = m68k_dreg(regs, (extra >> 12) & 7);\n");
2025	+	printf ("\tSET_NFLG_ALWAYS (tmp & (1 << (width - 1)) ? 1 : 0);\n");
2026	+	printf ("\tSET_ZFLG (tmp == 0);\n");
2027		break;
2028		default:
2029		break;
#	Line 2365 | Line 2094 | static void gen_opcode (unsigned long in
2094		genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2095		sync_m68k_pc ();
2096		swap_opcode ();
2097	<	printf ("\tfpp_opp(opcode,extra);\n");
2097	>	printf ("\tfpuop_arithmetic(opcode, extra);\n");
2098		break;
2099		case i_FDBcc:
2100		genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2101		sync_m68k_pc ();
2102		swap_opcode ();
2103	<	printf ("\tfdbcc_opp(opcode,extra);\n");
2103	>	printf ("\tfpuop_dbcc(opcode, extra);\n");
2104		break;
2105		case i_FScc:
2106		genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2107		sync_m68k_pc ();
2108		swap_opcode ();
2109	<	printf ("\tfscc_opp(opcode,extra);\n");
2109	>	printf ("\tfpuop_scc(opcode,extra);\n");
2110		break;
2111		case i_FTRAPcc:
2112		sync_m68k_pc ();
#	Line 2387 | Line 2116 | static void gen_opcode (unsigned long in
2116		genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0);
2117		sync_m68k_pc ();
2118		swap_opcode ();
2119	<	printf ("\tftrapcc_opp(opcode,oldpc);\n");
2119	>	printf ("\tfpuop_trapcc(opcode,oldpc);\n");
2120		break;
2121		case i_FBcc:
2122		sync_m68k_pc ();
#	Line 2396 | Line 2125 | static void gen_opcode (unsigned long in
2125		genamode (curi->dmode, "srcreg", curi->size, "extra", 1, 0);
2126		sync_m68k_pc ();
2127		swap_opcode ();
2128	<	printf ("\tfbcc_opp(opcode,pc,extra);\n");
2128	>	printf ("\tfpuop_bcc(opcode,pc,extra);\n");
2129		break;
2130		case i_FSAVE:
2131		sync_m68k_pc ();
2132		swap_opcode ();
2133	<	printf ("\tfsave_opp(opcode);\n");
2133	>	printf ("\tfpuop_save(opcode);\n");
2134		break;
2135		case i_FRESTORE:
2136		sync_m68k_pc ();
2137		swap_opcode ();
2138	<	printf ("\tfrestore_opp(opcode);\n");
2138	>	printf ("\tfpuop_restore(opcode);\n");
2139		break;
2140		case i_CINVL:
2141		case i_CINVP:
2142		case i_CINVA:
2143	+	/* gb-- srcreg now contains the cache field */
2144	+	printf ("\tif (srcreg&0x2)\n");
2145	+	printf ("\t\tflush_icache(%d);\n", 30 + ((opcode >> 3) & 3));
2146	+	break;
2147		case i_CPUSHL:
2148		case i_CPUSHP:
2149		case i_CPUSHA:
2150	+	/* gb-- srcreg now contains the cache field */
2151	+	printf ("\tif (srcreg&0x2)\n");
2152	+	printf ("\t\tflush_icache(%d);\n", 40 + ((opcode >> 3) & 3));
2153		break;
2154		case i_MOVE16:
2155	<	printf ("\tuaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;\n");
2156	<	printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword());
2157	<	printf ("\tmemd = m68k_areg(regs, dstreg) & ~15;\n");
2158	<	printf ("\tput_long(memd, get_long(mems));\n");
2159	<	printf ("\tput_long(memd+4, get_long(mems+4));\n");
2160	<	printf ("\tput_long(memd+8, get_long(mems+8));\n");
2161	<	printf ("\tput_long(memd+12, get_long(mems+12));\n");
2162	<	printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2163	<	printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2155	>	if ((opcode & 0xfff8) == 0xf620) {
2156	>	/* MOVE16 (Ax)+,(Ay)+ */
2157	>	printf ("\tuaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;\n");
2158	>	printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword());
2159	>	printf ("\tmemd = m68k_areg(regs, dstreg) & ~15;\n");
2160	>	printf ("\tput_long(memd, get_long(mems));\n");
2161	>	printf ("\tput_long(memd+4, get_long(mems+4));\n");
2162	>	printf ("\tput_long(memd+8, get_long(mems+8));\n");
2163	>	printf ("\tput_long(memd+12, get_long(mems+12));\n");
2164	>	printf ("\tif (srcreg != dstreg)\n");
2165	>	printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2166	>	printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2167	>	}
2168	>	else {
2169	>	/* Other variants */
2170	>	genamode (curi->smode, "srcreg", curi->size, "mems", 0, 2);
2171	>	genamode (curi->dmode, "dstreg", curi->size, "memd", 0, 2);
2172	>	printf ("\tmemsa &= ~15;\n");
2173	>	printf ("\tmemda &= ~15;\n");
2174	>	printf ("\tput_long(memda, get_long(memsa));\n");
2175	>	printf ("\tput_long(memda+4, get_long(memsa+4));\n");
2176	>	printf ("\tput_long(memda+8, get_long(memsa+8));\n");
2177	>	printf ("\tput_long(memda+12, get_long(memsa+12));\n");
2178	>	if ((opcode & 0xfff8) == 0xf600)
2179	>	printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2180	>	else if ((opcode & 0xfff8) == 0xf608)
2181	>	printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2182	>	}
2183		break;
2184		case i_MMUOP:
2185		genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
#	Line 2432 | Line 2187 | static void gen_opcode (unsigned long in
2187		swap_opcode ();
2188		printf ("\tmmu_op(opcode,extra);\n");
2189		break;
2190	+
2191	+	case i_EMULOP_RETURN:
2192	+	printf ("\tm68k_emulop_return();\n");
2193	+	m68k_pc_offset = 0;
2194	+	break;
2195	+
2196	+	case i_EMULOP:
2197	+	printf ("\n");
2198	+	swap_opcode ();
2199	+	printf ("\tm68k_emulop(opcode);\n");
2200	+	break;
2201	+
2202		default:
2203		abort ();
2204		break;
#	Line 2443 | Line 2210 | static void gen_opcode (unsigned long in
2210		static void generate_includes (FILE * f)
2211		{
2212		fprintf (f, "#include \"sysdeps.h\"\n");
2213	+
2214		fprintf (f, "#include \"m68k.h\"\n");
2215		fprintf (f, "#include \"memory.h\"\n");
2216		fprintf (f, "#include \"readcpu.h\"\n");
2217		fprintf (f, "#include \"newcpu.h\"\n");
2218	<	fprintf (f, "#include \"compiler.h\"\n");
2218	>	fprintf (f, "#include \"compiler/compemu.h\"\n");
2219	>	fprintf (f, "#include \"fpu/fpu.h\"\n");
2220		fprintf (f, "#include \"cputbl.h\"\n");
2221	+
2222	+	fprintf (f, "#define SET_CFLG_ALWAYS(x) SET_CFLG(x)\n");
2223	+	fprintf (f, "#define SET_NFLG_ALWAYS(x) SET_NFLG(x)\n");
2224	+	fprintf (f, "#define CPUFUNC_FF(x) x##_ff\n");
2225	+	fprintf (f, "#define CPUFUNC_NF(x) x##_nf\n");
2226	+	fprintf (f, "#define CPUFUNC(x) CPUFUNC_FF(x)\n");
2227	+
2228	+	fprintf (f, "#ifdef NOFLAGS\n");
2229	+	fprintf (f, "# include \"noflags.h\"\n");
2230	+	fprintf (f, "#endif\n");
2231		}
2232
2233		static int postfix;
#	Line 2472 | Line 2251 | static void generate_one_opcode (int rp)
2251		return;
2252
2253		if (opcode_next_clev[rp] != cpu_level) {
2254	<	fprintf (stblfile, "{ op_%lx_%d, 0, %ld }, /* %s */\n", opcode, opcode_last_postfix[rp],
2254	>	fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, opcode_last_postfix[rp],
2255		opcode, lookuptab[i].name);
2256		return;
2257		}
2258	<	fprintf (stblfile, "{ op_%lx_%d, 0, %ld }, /* %s */\n", opcode, postfix, opcode, lookuptab[i].name);
2259	<	fprintf (headerfile, "extern cpuop_func op_%lx_%d;\n", opcode, postfix);
2260	<	printf ("unsigned long REGPARAM2 op_%lx_%d(uae_u32 opcode) /* %s */\n{\n", opcode, postfix, lookuptab[i].name);
2258	>
2259	>	if (table68k[opcode].flagdead == 0)
2260	>	/* force to the "ff" variant since the instruction doesn't set at all the condition codes */
2261	>	fprintf (stblfile, "{ CPUFUNC_FF(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, postfix, opcode, lookuptab[i].name);
2262	>	else
2263	>	fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, postfix, opcode, lookuptab[i].name);
2264	>
2265	>	fprintf (headerfile, "extern cpuop_func op_%lx_%d_nf;\n", opcode, postfix);
2266	>	fprintf (headerfile, "extern cpuop_func op_%lx_%d_ff;\n", opcode, postfix);
2267	>	printf ("void REGPARAM2 CPUFUNC(op_%lx_%d)(uae_u32 opcode) /* %s */\n{\n", opcode, postfix, lookuptab[i].name);
2268	>	printf ("\tcpuop_begin();\n");
2269	>
2270	>	/* gb-- The "nf" variant for an instruction that doesn't set the condition
2271	>	codes at all is the same as the "ff" variant, so we don't need the "nf"
2272	>	variant to be compiled since it is mapped to the "ff" variant in the
2273	>	smalltbl. */
2274	>	if (table68k[opcode].flagdead == 0)
2275	>	printf ("#ifndef NOFLAGS\n");
2276
2277		switch (table68k[opcode].stype) {
2278		case 0: smsk = 7; break;
#	Line 2487 | Line 2281 | static void generate_one_opcode (int rp)
2281		case 3: smsk = 7; break;
2282		case 4: smsk = 7; break;
2283		case 5: smsk = 63; break;
2284	+	case 6: smsk = 255; break;
2285	+	case 7: smsk = 3; break;
2286		default: abort ();
2287		}
2288		dmsk = 7;
#	Line 2496 | Line 2292 | static void generate_one_opcode (int rp)
2292		&& table68k[opcode].smode != imm && table68k[opcode].smode != imm0
2293		&& table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2
2294		&& table68k[opcode].smode != absw && table68k[opcode].smode != absl
2295	<	&& table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16)
2295	>	&& table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16
2296	>	/* gb-- We don't want to fetch the EmulOp code since the EmulOp()
2297	>	routine uses the whole opcode value. Maybe all the EmulOps
2298	>	could be expanded out but I don't think it is an improvement */
2299	>	&& table68k[opcode].stype != 6
2300	>	)
2301		{
2302		if (table68k[opcode].spos == -1) {
2303		if (((int) table68k[opcode].sreg) >= 128)
#	Line 2592 | Line 2393 | static void generate_one_opcode (int rp)
2393		gen_opcode (opcode);
2394		if (need_endlabel)
2395		printf ("%s: ;\n", endlabelstr);
2396	<	printf ("return %d;\n", insn_n_cycles);
2396	>	if (table68k[opcode].flagdead == 0)
2397	>	printf ("\n#endif\n");
2398	>	printf ("\tcpuop_end();\n");
2399		printf ("}\n");
2400		opcode_next_clev[rp] = next_cpu_level;
2401		opcode_last_postfix[rp] = postfix;
#	Line 2604 | Line 2407 | static void generate_func (void)
2407
2408		using_prefetch = 0;
2409		using_exception_3 = 0;
2410	+	#if !USE_PREFETCH_BUFFER
2411	+	/* gb-- No need for a prefetch buffer, nor exception 3 handling */
2412	+	/* Anyway, Basilisk2 does not use the op_smalltbl_5 table... */
2413	+	for (i = 0; i <= 4; i++) {
2414	+	#else
2415		for (i = 0; i < 6; i++) {
2416	+	#endif
2417		cpu_level = 4 - i;
2418		if (i == 5) {
2419		cpu_level = 0;
#	Line 2614 | Line 2423 | static void generate_func (void)
2423		opcode_next_clev[rp] = 0;
2424		}
2425		postfix = i;
2426	<	fprintf (stblfile, "struct cputbl op_smalltbl_%d[] = {\n", postfix);
2426	>	fprintf (stblfile, "struct cputbl CPUFUNC(op_smalltbl_%d)[] = {\n", postfix);
2427
2428		/* sam: this is for people with low memory (eg. me :)) */
2429		printf ("\n"

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