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root/cebix/BasiliskII/src/uae_cpu/gencpu.c

Comparing BasiliskII/src/uae_cpu/gencpu.c (file contents):
Revision 1.9 by cebix, 1999-10-31T23:18:40Z vs.
Revision 1.26 by asvitkine, 2012-03-30T01:25:46Z

#	Line 14 | Line 14
14		* take care of this.
15		*
16		* Copyright 1995, 1996 Bernd Schmidt
17	+	*
18	+	* This program is free software; you can redistribute it and/or modify
19	+	* it under the terms of the GNU General Public License as published by
20	+	* the Free Software Foundation; either version 2 of the License, or
21	+	* (at your option) any later version.
22	+	*
23	+	* This program is distributed in the hope that it will be useful,
24	+	* but WITHOUT ANY WARRANTY; without even the implied warranty of
25	+	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26	+	* GNU General Public License for more details.
27	+	*
28	+	* You should have received a copy of the GNU General Public License
29	+	* along with this program; if not, write to the Free Software
30	+	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
31	+	*
32		*/
33
34		#include <ctype.h>
#	Line 30 | Line 45
45
46		#define BOOL_TYPE "int"
47
48	+	/* Define the minimal 680x0 where NV flags are not affected by xBCD instructions.  */
49	+	#define xBCD_KEEPS_NV_FLAGS 4
50	+
51		static FILE *headerfile;
52		static FILE *stblfile;
53
#	Line 221 | Line 239 | static void sync_m68k_pc (void)
239		}
240
241		/* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
242	<	* the calling routine handles Apdi and Aipi modes. */
242	>	* the calling routine handles Apdi and Aipi modes.
243	>	* gb-- movem == 2 means the same thing but for a MOVE16 instruction */
244		static void genamode (amodes mode, char *reg, wordsizes size, char *name, int getv, int movem)
245		{
246		start_brace ();
#	Line 232 | Line 251 | static void genamode (amodes mode, char
251		if (getv == 1)
252		switch (size) {
253		case sz_byte:
254	<	#ifdef AMIGA
254	>	#if defined(AMIGA) && !defined(WARPUP)
255		/* sam: I don't know why gcc.2.7.2.1 produces a code worse */
256		/* if it is not done like that: */
257		printf ("\tuae_s8 %s = ((uae_u8*)&m68k_dreg(regs, %s))[3];\n", name, reg);
#	Line 241 | Line 260 | static void genamode (amodes mode, char
260		#endif
261		break;
262		case sz_word:
263	<	#ifdef AMIGA
263	>	#if defined(AMIGA) && !defined(WARPUP)
264		printf ("\tuae_s16 %s = ((uae_s16*)&m68k_dreg(regs, %s))[1];\n", name, reg);
265		#else
266		printf ("\tuae_s16 %s = m68k_dreg(regs, %s);\n", name, reg);
#	Line 567 | Line 586 | static void duplicate_carry (void)
586		}
587
588		typedef enum {
589	<	flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_zn,
589	>	flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_z, flag_zn,
590		flag_av, flag_sv
591		} flagtypes;
592
#	Line 621 | Line 640 | static void genflags_normal (flagtypes t
640		switch (type) {
641		case flag_logical_noclobber:
642		case flag_logical:
643	+	case flag_z:
644		case flag_zn:
645		case flag_av:
646		case flag_sv:
#	Line 642 | Line 662 | static void genflags_normal (flagtypes t
662		switch (type) {
663		case flag_logical_noclobber:
664		case flag_logical:
665	+	case flag_z:
666		case flag_zn:
667		break;
668
#	Line 675 | Line 696 | static void genflags_normal (flagtypes t
696		case flag_sv:
697		printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
698		break;
699	+	case flag_z:
700	+	printf ("\tSET_ZFLG (GET_ZFLG & (%s == 0));\n", vstr);
701	+	break;
702		case flag_zn:
703		printf ("\tSET_ZFLG (GET_ZFLG & (%s == 0));\n", vstr);
704		printf ("\tSET_NFLG (%s < 0);\n", vstr);
#	Line 714 | Line 738 | static void genflags_normal (flagtypes t
738
739		static void genflags (flagtypes type, wordsizes size, char *value, char *src, char *dst)
740		{
741	<	#ifdef SPARC_V8_ASSEMBLY
742	<	switch(type)
743	<	{
744	<	case flag_add:
721	<	start_brace();
722	<	printf("\tuae_u32 %s;\n", value);
723	<	switch(size)
724	<	{
725	<	case sz_byte:
726	<	printf("\t%s = sparc_v8_flag_add_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
727	<	break;
728	<	case sz_word:
729	<	printf("\t%s = sparc_v8_flag_add_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
730	<	break;
731	<	case sz_long:
732	<	printf("\t%s = sparc_v8_flag_add_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
733	<	break;
734	<	}
735	<	return;
736	<
737	<	case flag_sub:
738	<	start_brace();
739	<	printf("\tuae_u32 %s;\n", value);
740	<	switch(size)
741	<	{
742	<	case sz_byte:
743	<	printf("\t%s = sparc_v8_flag_sub_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
744	<	break;
745	<	case sz_word:
746	<	printf("\t%s = sparc_v8_flag_sub_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
747	<	break;
748	<	case sz_long:
749	<	printf("\t%s = sparc_v8_flag_sub_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
750	<	break;
751	<	}
752	<	return;
753	<
754	<	case flag_cmp:
755	<	switch(size)
756	<	{
757	<	case sz_byte:
758	<	//                                      printf("\tsparc_v8_flag_cmp_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
759	<	break;
760	<	case sz_word:
761	<	//                                      printf("\tsparc_v8_flag_cmp_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
762	<	break;
763	<	case sz_long:
764	<	#if 1
765	<	printf("\tsparc_v8_flag_cmp_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
766	<	return;
767	<	#endif
768	<	break;
769	<	}
770	<	//                      return;
771	<	break;
772	<	}
773	<	#elif defined(SPARC_V9_ASSEMBLY)
774	<	switch(type)
775	<	{
776	<	case flag_add:
777	<	start_brace();
778	<	printf("\tuae_u32 %s;\n", value);
779	<	switch(size)
780	<	{
781	<	case sz_byte:
782	<	printf("\t%s = sparc_v9_flag_add_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
783	<	break;
784	<	case sz_word:
785	<	printf("\t%s = sparc_v9_flag_add_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
786	<	break;
787	<	case sz_long:
788	<	printf("\t%s = sparc_v9_flag_add_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
789	<	break;
790	<	}
791	<	return;
792	<
793	<	case flag_sub:
794	<	start_brace();
795	<	printf("\tuae_u32 %s;\n", value);
796	<	switch(size)
797	<	{
798	<	case sz_byte:
799	<	printf("\t%s = sparc_v9_flag_sub_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
800	<	break;
801	<	case sz_word:
802	<	printf("\t%s = sparc_v9_flag_sub_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
803	<	break;
804	<	case sz_long:
805	<	printf("\t%s = sparc_v9_flag_sub_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
806	<	break;
807	<	}
808	<	return;
809	<
810	<	case flag_cmp:
811	<	switch(size)
812	<	{
813	<	case sz_byte:
814	<	printf("\tsparc_v9_flag_cmp_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
815	<	break;
816	<	case sz_word:
817	<	printf("\tsparc_v9_flag_cmp_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
818	<	break;
819	<	case sz_long:
820	<	printf("\tsparc_v9_flag_cmp_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
821	<	break;
822	<	}
823	<	return;
824	<
825	<	case flag_logical:
826	<	if (strcmp(value, "0") == 0) {
827	<	printf("\tregflags.nzvc = 0x04;\n");
828	<	} else {
829	<	switch(size) {
830	<	case sz_byte:
831	<	printf("\tsparc_v9_flag_test_8(&regflags, (uae_u32)(%s));\n", value);
832	<	break;
833	<	case sz_word:
834	<	printf("\tsparc_v9_flag_test_16(&regflags, (uae_u32)(%s));\n", value);
835	<	break;
836	<	case sz_long:
837	<	printf("\tsparc_v9_flag_test_32(&regflags, (uae_u32)(%s));\n", value);
838	<	break;
839	<	}
840	<	}
841	<	return;
842	<
843	<	#if 0
844	<	case flag_logical_noclobber:
845	<	printf("\t{uae_u32 old_flags = regflags.nzvc & ~0x0C;\n");
846	<	if (strcmp(value, "0") == 0) {
847	<	printf("\tregflags.nzvc = old_flags | 0x04;\n");
848	<	} else {
849	<	switch(size) {
850	<	case sz_byte:
851	<	printf("\tsparc_v9_flag_test_8(&regflags, (uae_u32)(%s));\n", value);
852	<	break;
853	<	case sz_word:
854	<	printf("\tsparc_v9_flag_test_16(&regflags, (uae_u32)(%s));\n", value);
855	<	break;
856	<	case sz_long:
857	<	printf("\tsparc_v9_flag_test_32(&regflags, (uae_u32)(%s));\n", value);
858	<	break;
859	<	}
860	<	printf("\tregflags.nzvc |= old_flags;\n");
861	<	}
862	<	printf("\t}\n");
863	<	return;
864	<	#endif
865	<	}
866	<	#elif defined(X86_ASSEMBLY)
741	>	/* Temporarily deleted 68k/ARM flag optimizations.  I'd prefer to have
742	>	them in the appropriate m68k.h files and use just one copy of this
743	>	code here.  The API can be changed if necessary.  */
744	>	#ifdef OPTIMIZED_FLAGS
745		switch (type) {
746		case flag_add:
747		case flag_sub:
748		start_brace ();
749		printf ("\tuae_u32 %s;\n", value);
750		break;
873	–
751		default:
752		break;
753		}
#	Line 878 | Line 755 | static void genflags (flagtypes type, wo
755		/* At least some of those casts are fairly important! */
756		switch (type) {
757		case flag_logical_noclobber:
758	<	printf ("\t{uae_u32 oldcznv = regflags.cznv & ~0xC0;\n");
758	>	printf ("\t{uae_u32 oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
759		if (strcmp (value, "0") == 0) {
760	<	printf ("\tregflags.cznv = olcznv | 64;\n");
760	>	printf ("\tSET_CZNV (olcznv | FLAGVAL_Z);\n");
761		} else {
762		switch (size) {
763	<	case sz_byte: printf ("\tx86_flag_testb ((uae_s8)(%s));\n", value); break;
764	<	case sz_word: printf ("\tx86_flag_testw ((uae_s16)(%s));\n", value); break;
765	<	case sz_long: printf ("\tx86_flag_testl ((uae_s32)(%s));\n", value); break;
763	>	case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
764	>	case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
765	>	case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
766		}
767	<	printf ("\tregflags.cznv |= oldcznv;\n");
767	>	printf ("\tIOR_CZNV (oldcznv);\n");
768		}
769		printf ("\t}\n");
770		return;
771	+
772		case flag_logical:
773		if (strcmp (value, "0") == 0) {
774	<	printf ("\tregflags.cznv = 64;\n");
774	>	printf ("\tSET_CZNV (FLAGVAL_Z);\n");
775		} else {
776		switch (size) {
777	<	case sz_byte: printf ("\tx86_flag_testb ((uae_s8)(%s));\n", value); break;
778	<	case sz_word: printf ("\tx86_flag_testw ((uae_s16)(%s));\n", value); break;
779	<	case sz_long: printf ("\tx86_flag_testl ((uae_s32)(%s));\n", value); break;
777	>	case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
778	>	case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
779	>	case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
780		}
781		}
782		return;
783
784		case flag_add:
785		switch (size) {
786	<	case sz_byte: printf ("\tx86_flag_addb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
787	<	case sz_word: printf ("\tx86_flag_addw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
788	<	case sz_long: printf ("\tx86_flag_addl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
786	>	case sz_byte: printf ("\toptflag_addb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
787	>	case sz_word: printf ("\toptflag_addw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
788	>	case sz_long: printf ("\toptflag_addl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
789		}
790		return;
791
792		case flag_sub:
793		switch (size) {
794	<	case sz_byte: printf ("\tx86_flag_subb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
795	<	case sz_word: printf ("\tx86_flag_subw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
796	<	case sz_long: printf ("\tx86_flag_subl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
794	>	case sz_byte: printf ("\toptflag_subb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
795	>	case sz_word: printf ("\toptflag_subw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
796	>	case sz_long: printf ("\toptflag_subl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
797		}
798		return;
799
800		case flag_cmp:
801		switch (size) {
802	<	case sz_byte: printf ("\tx86_flag_cmpb ((uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
803	<	case sz_word: printf ("\tx86_flag_cmpw ((uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
804	<	case sz_long: printf ("\tx86_flag_cmpl ((uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
802	>	case sz_byte: printf ("\toptflag_cmpb ((uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
803	>	case sz_word: printf ("\toptflag_cmpw ((uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
804	>	case sz_long: printf ("\toptflag_cmpl ((uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
805		}
806		return;
807
808		default:
809		break;
810		}
933	–	#elif defined(M68K_FLAG_OPT)
934	–	/* sam: here I'm cloning what X86_ASSEMBLY does */
935	–	#define EXT(size)  (size==sz_byte?"b":(size==sz_word?"w":"l"))
936	–	#define CAST(size) (size==sz_byte?"uae_s8":(size==sz_word?"uae_s16":"uae_s32"))
937	–	switch (type) {
938	–	case flag_add:
939	–	case flag_sub:
940	–	start_brace ();
941	–	printf ("\tuae_u32 %s;\n", value);
942	–	break;
943	–
944	–	default:
945	–	break;
946	–	}
947	–
948	–	switch (type) {
949	–	case flag_logical:
950	–	if (strcmp (value, "0") == 0) {
951	–	printf ("\t*(uae_u16 *)&regflags = 4;\n");  /* Z = 1 */
952	–	} else {
953	–	printf ("\tm68k_flag_tst (%s, (%s)(%s));\n",
954	–	EXT (size), CAST (size), value);
955	–	}
956	–	return;
957	–
958	–	case flag_add:
959	–	printf ("\t{uae_u16 ccr;\n");
960	–	printf ("\tm68k_flag_add (%s, (%s)%s, (%s)(%s), (%s)(%s));\n",
961	–	EXT (size), CAST (size), value, CAST (size), src, CAST (size), dst);
962	–	printf ("\t((uae_u16*)&regflags)[1]=((uae_u16*)&regflags)[0]=ccr;}\n");
963	–	return;
964	–
965	–	case flag_sub:
966	–	printf ("\t{uae_u16 ccr;\n");
967	–	printf ("\tm68k_flag_sub (%s, (%s)%s, (%s)(%s), (%s)(%s));\n",
968	–	EXT (size), CAST (size), value, CAST (size), src, CAST (size), dst);
969	–	printf ("\t((uae_u16*)&regflags)[1]=((uae_u16*)&regflags)[0]=ccr;}\n");
970	–	return;
971	–
972	–	case flag_cmp:
973	–	printf ("\tm68k_flag_cmp (%s, (%s)(%s), (%s)(%s));\n",
974	–	EXT (size), CAST (size), src, CAST (size), dst);
975	–	return;
976	–
977	–	default:
978	–	break;
979	–	}
980	–	#elif defined(ACORN_FLAG_OPT) && defined(__GNUC_MINOR__)
981	–	/*
982	–	* This is new. Might be quite buggy.
983	–	*/
984	–	switch (type) {
985	–	case flag_av:
986	–	case flag_sv:
987	–	case flag_zn:
988	–	case flag_addx:
989	–	case flag_subx:
990	–	break;
991	–
992	–	case flag_logical:
993	–	if (strcmp (value, "0") == 0) {
994	–	/* v=c=n=0 z=1 */
995	–	printf ("\t*(ULONG*)&regflags = 0x40000000;\n");
996	–	return;
997	–	} else {
998	–	start_brace ();
999	–	switch (size) {
1000	–	case sz_byte:
1001	–	printf ("\tUBYTE ccr;\n");
1002	–	printf ("\tULONG shift;\n");
1003	–	printf ("\t__asm__(\"mov %%2,%%1,lsl#24\n\ttst %%2,%%2\n\tmov %%0,r15,lsr#24\n\tbic %%0,%%0,#0x30\"\n"
1004	–	"\t: \"=r\" (ccr) : \"r\" (%s), \"r\" (shift) : \"cc\" );\n", value);
1005	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1006	–	return;
1007	–	case sz_word:
1008	–	printf ("\tUBYTE ccr;\n");
1009	–	printf ("\tULONG shift;\n");
1010	–	printf ("\t__asm__(\"mov %%2,%%1,lsl#16\n\ttst %%2,%%2\n\tmov %%0,r15,lsr#24\n\tbic %%0,%%0,#0x30\"\n"
1011	–	"\t: \"=r\" (ccr) : \"r\" ((WORD)%s), \"r\" (shift) : \"cc\" );\n", value);
1012	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1013	–	return;
1014	–	case sz_long:
1015	–	printf ("\tUBYTE ccr;\n");
1016	–	printf ("\t__asm__(\"tst %%1,%%1\n\tmov %%0,r15,lsr#24\n\tbic %%0,%%0,#0x30\"\n"
1017	–	"\t: \"=r\" (ccr) : \"r\" ((LONG)%s) : \"cc\" );\n", value);
1018	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1019	–	return;
1020	–	}
1021	–	}
1022	–	break;
1023	–	case flag_add:
1024	–	if (strcmp (dst, "0") == 0) {
1025	–	printf ("/* Error! Hier muss Peter noch was machen !!! (ADD-Flags) */");
1026	–	} else {
1027	–	start_brace ();
1028	–	switch (size) {
1029	–	case sz_byte:
1030	–	printf ("\tULONG ccr, shift, %s;\n", value);
1031	–	printf ("\t__asm__(\"mov %%4,%%3,lsl#24\n\tadds %%0,%%4,%%2,lsl#24\n\tmov %%0,%%0,asr#24\n\tmov %%1,r15\n\torr %%1,%%1,%%1,lsr#29\"\n"
1032	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" (%s), \"r\" (%s), \"r\" (shift) : \"cc\" );\n", value, src, dst);
1033	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1034	–	return;
1035	–	case sz_word:
1036	–	printf ("\tULONG ccr, shift, %s;\n", value);
1037	–	printf ("\t__asm__(\"mov %%4,%%3,lsl#16\n\tadds %%0,%%4,%%2,lsl#16\n\tmov %%0,%%0,asr#16\n\tmov %%1,r15\n\torr %%1,%%1,%%1,lsr#29\"\n"
1038	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" ((WORD)%s), \"r\" ((WORD)%s), \"r\" (shift) : \"cc\" );\n", value, src, dst);
1039	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1040	–	return;
1041	–	case sz_long:
1042	–	printf ("\tULONG ccr, %s;\n", value);
1043	–	printf ("\t__asm__(\"adds %%0,%%3,%%2\n\tmov %%1,r15\n\torr %%1,%%1,%%1,lsr#29\"\n"
1044	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" ((LONG)%s), \"r\" ((LONG)%s) : \"cc\" );\n", value, src, dst);
1045	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1046	–	return;
1047	–	}
1048	–	}
1049	–	break;
1050	–	case flag_sub:
1051	–	if (strcmp (dst, "0") == 0) {
1052	–	printf ("/* Error! Hier muss Peter noch was machen !!! (SUB-Flags) */");
1053	–	} else {
1054	–	start_brace ();
1055	–	switch (size) {
1056	–	case sz_byte:
1057	–	printf ("\tULONG ccr, shift, %s;\n", value);
1058	–	printf ("\t__asm__(\"mov %%4,%%3,lsl#24\n\tsubs %%0,%%4,%%2,lsl#24\n\tmov %%0,%%0,asr#24\n\tmov %%1,r15\n\teor %%1,%%1,#0x20000000\n\torr %%1,%%1,%%1,lsr#29\"\n"
1059	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" (%s), \"r\" (%s), \"r\" (shift) : \"cc\" );\n", value, src, dst);
1060	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1061	–	return;
1062	–	case sz_word:
1063	–	printf ("\tULONG ccr, shift, %s;\n", value);
1064	–	printf ("\t__asm__(\"mov %%4,%%3,lsl#16\n\tsubs %%0,%%4,%%2,lsl#16\n\tmov %%0,%%0,asr#16\n\tmov %%1,r15\n\teor %%1,%%1,#0x20000000\n\torr %%1,%%1,%%1,lsr#29\"\n"
1065	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" ((WORD)%s), \"r\" ((WORD)%s), \"r\" (shift) : \"cc\" );\n", value, src, dst);
1066	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1067	–	return;
1068	–	case sz_long:
1069	–	printf ("\tULONG ccr, %s;\n", value);
1070	–	printf ("\t__asm__(\"subs %%0,%%3,%%2\n\tmov %%1,r15\n\teor %%1,%%1,#0x20000000\n\torr %%1,%%1,%%1,lsr#29\"\n"
1071	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" ((LONG)%s), \"r\" ((LONG)%s) : \"cc\" );\n", value, src, dst);
1072	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1073	–	return;
1074	–	}
1075	–	}
1076	–	break;
1077	–	case flag_cmp:
1078	–	if (strcmp (dst, "0") == 0) {
1079	–	printf ("/*Error! Hier muss Peter noch was machen !!! (CMP-Flags)*/");
1080	–	} else {
1081	–	start_brace ();
1082	–	switch (size) {
1083	–	case sz_byte:
1084	–	printf ("\tULONG shift, ccr;\n");
1085	–	printf ("\t__asm__(\"mov %%3,%%2,lsl#24\n\tcmp %%3,%%1,lsl#24\n\tmov %%0,r15,lsr#24\n\teor %%0,%%0,#0x20\"\n"
1086	–	"\t: \"=r\" (ccr) : \"r\" (%s), \"r\" (%s), \"r\" (shift) : \"cc\" );\n", src, dst);
1087	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1088	–	return;
1089	–	case sz_word:
1090	–	printf ("\tULONG shift, ccr;\n");
1091	–	printf ("\t__asm__(\"mov %%3,%%2,lsl#16\n\tcmp %%3,%%1,lsl#16\n\tmov %%0,r15,lsr#24\n\teor %%0,%%0,#0x20\"\n"
1092	–	"\t: \"=r\" (ccr) : \"r\" ((WORD)%s), \"r\" ((WORD)%s), \"r\" (shift) : \"cc\" );\n", src, dst);
1093	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1094	–	return;
1095	–	case sz_long:
1096	–	printf ("\tULONG ccr;\n");
1097	–	printf ("\t__asm__(\"cmp %%2,%%1\n\tmov %%0,r15,lsr#24\n\teor %%0,%%0,#0x20\"\n"
1098	–	"\t: \"=r\" (ccr) : \"r\" ((LONG)%s), \"r\" ((LONG)%s) : \"cc\" );\n", src, dst);
1099	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1100	–	/*printf ("\tprintf (\"%%08x %%08x %%08x\\n\", %s, %s, *((ULONG*)&regflags));\n", src, dst); */
1101	–	return;
1102	–	}
1103	–	}
1104	–	break;
1105	–	}
811		#endif
812		genflags_normal (type, size, value, src, dst);
813		}
#	Line 1227 | Line 932 | static void gen_opcode (unsigned long in
932		genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
933		break;
934		case i_SBCD:
1230	–	/* Let's hope this works... */
935		genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
936		genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
937		start_brace ();
938		printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
939		printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
940	<	printf ("\tuae_u16 newv;\n");
941	<	printf ("\tint cflg;\n");
942	<	printf ("\tif (newv_lo > 9) { newv_lo-=6; newv_hi-=0x10; }\n");
943	<	printf ("\tnewv = newv_hi + (newv_lo & 0xF);");
944	<	printf ("\tSET_CFLG (cflg = (newv_hi & 0x1F0) > 0x90);\n");
940	>	printf ("\tuae_u16 newv, tmp_newv;\n");
941	>	printf ("\tint bcd = 0;\n");
942	>	printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
943	>	printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
944	>	printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
945	>	printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);\n");
946		duplicate_carry ();
947	<	printf ("\tif (cflg) newv -= 0x60;\n");
948	<	genflags (flag_zn, curi->size, "newv", "", "");
949	<	genflags (flag_sv, curi->size, "newv", "src", "dst");
947	>	/* Manual says bits NV are undefined though a real 68040 don't change them */
948	>	if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
949	>	if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
950	>	next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
951	>	genflags (flag_z, curi->size, "newv", "", "");
952	>	}
953	>	else {
954	>	genflags (flag_zn, curi->size, "newv", "", "");
955	>	printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
956	>	}
957		genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
958		break;
959		case i_ADD:
#	Line 1273 | Line 985 | static void gen_opcode (unsigned long in
985		start_brace ();
986		printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);\n");
987		printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
988	<	printf ("\tuae_u16 newv;\n");
988	>	printf ("\tuae_u16 newv, tmp_newv;\n");
989		printf ("\tint cflg;\n");
990	<	printf ("\tif (newv_lo > 9) { newv_lo +=6; }\n");
991	<	printf ("\tnewv = newv_hi + newv_lo;");
992	<	printf ("\tSET_CFLG (cflg = (newv & 0x1F0) > 0x90);\n");
1281	<	duplicate_carry ();
990	>	printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
991	>	printf ("\tif (newv_lo > 9) { newv += 6; }\n");
992	>	printf ("\tcflg = (newv & 0x3F0) > 0x90;\n");
993		printf ("\tif (cflg) newv += 0x60;\n");
994	<	genflags (flag_zn, curi->size, "newv", "", "");
995	<	genflags (flag_sv, curi->size, "newv", "src", "dst");
994	>	printf ("\tSET_CFLG (cflg);\n");
995	>	duplicate_carry ();
996	>	/* Manual says bits NV are undefined though a real 68040 don't change them */
997	>	if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
998	>	if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
999	>	next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
1000	>	genflags (flag_z, curi->size, "newv", "", "");
1001	>	}
1002	>	else {
1003	>	genflags (flag_zn, curi->size, "newv", "", "");
1004	>	printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
1005	>	}
1006		genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1007		break;
1008		case i_NEG:
#	Line 1305 | Line 1026 | static void gen_opcode (unsigned long in
1026		printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n");
1027		printf ("\tuae_u16 newv;\n");
1028		printf ("\tint cflg;\n");
1029	<	printf ("\tif (newv_lo > 9) { newv_lo-=6; newv_hi-=0x10; }\n");
1030	<	printf ("\tnewv = newv_hi + (newv_lo & 0xF);");
1031	<	printf ("\tSET_CFLG (cflg = (newv_hi & 0x1F0) > 0x90);\n");
1311	<	duplicate_carry();
1029	>	printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
1030	>	printf ("\tnewv = newv_hi + newv_lo;\n");
1031	>	printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
1032		printf ("\tif (cflg) newv -= 0x60;\n");
1033	<	genflags (flag_zn, curi->size, "newv", "", "");
1033	>	printf ("\tSET_CFLG (cflg);\n");
1034	>	duplicate_carry();
1035	>	/* Manual says bits NV are undefined though a real 68040 don't change them */
1036	>	if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
1037	>	if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
1038	>	next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
1039	>	genflags (flag_z, curi->size, "newv", "", "");
1040	>	}
1041	>	else {
1042	>	genflags (flag_zn, curi->size, "newv", "", "");
1043	>	}
1044		genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1045		break;
1046		case i_CLR:
#	Line 1346 | Line 1076 | static void gen_opcode (unsigned long in
1076		else
1077		printf ("\tsrc &= 31;\n");
1078		printf ("\tdst ^= (1 << src);\n");
1079	<	printf ("\tSET_ZFLG ((dst & (1 << src)) >> src);\n");
1079	>	printf ("\tSET_ZFLG (((uae_u32)dst & (1 << src)) >> src);\n");
1080		genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1081		break;
1082		case i_BCLR:
#	Line 1517 | Line 1247 | static void gen_opcode (unsigned long in
1247		printf ("\tif ((format & 0xF000) == 0x0000) { break; }\n");
1248		printf ("\telse if ((format & 0xF000) == 0x1000) { ; }\n");
1249		printf ("\telse if ((format & 0xF000) == 0x2000) { m68k_areg(regs, 7) += 4; break; }\n");
1250	+	/* gb-- the next two lines are deleted in Bernie's gencpu.c */
1251		printf ("\telse if ((format & 0xF000) == 0x3000) { m68k_areg(regs, 7) += 4; break; }\n");
1252		printf ("\telse if ((format & 0xF000) == 0x7000) { m68k_areg(regs, 7) += 52; break; }\n");
1253		printf ("\telse if ((format & 0xF000) == 0x8000) { m68k_areg(regs, 7) += 50; break; }\n");
#	Line 1535 | Line 1266 | static void gen_opcode (unsigned long in
1266		m68k_pc_offset = 0;
1267		break;
1268		case i_RTD:
1538	–	printf ("\tcompiler_flush_jsr_stack();\n");
1269		genamode (Aipi, "7", sz_long, "pc", 1, 0);
1270		genamode (curi->smode, "srcreg", curi->size, "offs", 1, 0);
1271		printf ("\tm68k_areg(regs, 7) += offs;\n");
#	Line 1569 | Line 1299 | static void gen_opcode (unsigned long in
1299		need_endlabel = 1;
1300		break;
1301		case i_RTR:
1572	–	printf ("\tcompiler_flush_jsr_stack();\n");
1302		printf ("\tMakeSR();\n");
1303		genamode (Aipi, "7", sz_word, "sr", 1, 0);
1304		genamode (Aipi, "7", sz_long, "pc", 1, 0);
#	Line 1607 | Line 1336 | static void gen_opcode (unsigned long in
1336		m68k_pc_offset = 0;
1337		break;
1338		case i_Bcc:
1339	+	if (0 && !using_prefetch && !using_exception_3 && (cpu_level >= 2)) {
1340	+	/* gb-- variant probably more favorable to compiler optimizations
1341	+	also assumes no prefetch buffer is used
1342	+	Hmm, that would make sense with processors capable of conditional moves */
1343	+	if (curi->size == sz_long && next_cpu_level < 1)
1344	+	next_cpu_level = 1;
1345	+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1346	+	printf ("\tm68k_incpc (cctrue(%d) ? ((uae_s32)src + 2) : %d);\n", curi->cc, m68k_pc_offset);
1347	+	m68k_pc_offset = 0;
1348	+	}
1349	+	else {
1350	+	/* original code for branch instructions */
1351		if (curi->size == sz_long) {
1352		if (cpu_level < 2) {
1353		printf ("\tm68k_incpc(2);\n");
#	Line 1630 | Line 1371 | static void gen_opcode (unsigned long in
1371		printf ("\t}\n");
1372		need_endlabel = 1;
1373		}
1633	–	#ifdef USE_COMPILER
1634	–	printf ("\tm68k_setpc_bcc(m68k_getpc() + 2 + (uae_s32)src);\n");
1635	–	#else
1374		printf ("\tm68k_incpc ((uae_s32)src + 2);\n");
1637	–	#endif
1375		fill_prefetch_0 ();
1376	<	printf ("\tgoto %s;\n", endlabelstr);
1376	>	printf ("return;\n");
1377		printf ("didnt_jump:;\n");
1378		need_endlabel = 1;
1379	+	}
1380		break;
1381		case i_LEA:
1382		genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
#	Line 1666 | Line 1404 | static void gen_opcode (unsigned long in
1404		printf ("\t\t}\n");
1405		need_endlabel = 1;
1406		}
1669	–	#ifdef USE_COMPILER
1670	–	printf ("\t\t\tm68k_setpc_bcc(m68k_getpc() + (uae_s32)offs + 2);\n");
1671	–	#else
1407		printf ("\t\t\tm68k_incpc((uae_s32)offs + 2);\n");
1673	–	#endif
1408		fill_prefetch_0 ();
1409	<	printf ("\t\tgoto %s;\n", endlabelstr);
1409	>	printf ("return;\n");
1410		printf ("\t\t}\n");
1411		printf ("\t}\n");
1412		need_endlabel = 1;
#	Line 1687 | Line 1421 | static void gen_opcode (unsigned long in
1421		printf ("\tuaecptr oldpc = m68k_getpc();\n");
1422		genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1423		genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1424	<	printf ("\tif(src == 0) { Exception(5,oldpc); goto %s; } else {\n", endlabelstr);
1424	>	sync_m68k_pc ();
1425	>	/* Clear V flag when dividing by zero - Alcatraz Odyssey demo depends
1426	>	* on this (actually, it's doing a DIVS).  */
1427	>	printf ("\tif (src == 0) { SET_VFLG (0); Exception (5, oldpc); goto %s; } else {\n", endlabelstr);
1428		printf ("\tuae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;\n");
1429		printf ("\tuae_u32 rem = (uae_u32)dst %% (uae_u32)(uae_u16)src;\n");
1430		/* The N flag appears to be set each time there is an overflow.
#	Line 1705 | Line 1442 | static void gen_opcode (unsigned long in
1442		printf ("\tuaecptr oldpc = m68k_getpc();\n");
1443		genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1444		genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1445	<	printf ("\tif(src == 0) { Exception(5,oldpc); goto %s; } else {\n", endlabelstr);
1445	>	sync_m68k_pc ();
1446	>	printf ("\tif (src == 0) { SET_VFLG (0); Exception(5,oldpc); goto %s; } else {\n", endlabelstr);
1447		printf ("\tuae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;\n");
1448		printf ("\tuae_u16 rem = (uae_s32)dst %% (uae_s32)(uae_s16)src;\n");
1449		printf ("\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n");
#	Line 1766 | Line 1504 | static void gen_opcode (unsigned long in
1504		abort ();
1505		}
1506		printf ("\tSET_ZFLG (upper == reg || lower == reg);\n");
1507	<	printf ("\tSET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
1507	>	printf ("\tSET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
1508		printf ("\tif ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc); goto %s; }\n}\n", endlabelstr);
1509		need_endlabel = 1;
1510		break;
#	Line 1965 | Line 1703 | static void gen_opcode (unsigned long in
1703		}
1704		printf ("\tcnt &= 63;\n");
1705		printf ("\tCLEAR_CZNV;\n");
1968	–	if (! source_is_imm1_8 (curi))
1969	–	force_range_for_rox ("cnt", curi->size);
1706		if (source_is_imm1_8 (curi))
1707		printf ("{");
1708	<	else
1708	>	else {
1709	>	force_range_for_rox ("cnt", curi->size);
1710		printf ("\tif (cnt > 0) {\n");
1711	+	}
1712		printf ("\tcnt--;\n");
1713		printf ("\t{\n\tuae_u32 carry;\n");
1714		printf ("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
#	Line 1995 | Line 1733 | static void gen_opcode (unsigned long in
1733		}
1734		printf ("\tcnt &= 63;\n");
1735		printf ("\tCLEAR_CZNV;\n");
1998	–	if (! source_is_imm1_8 (curi))
1999	–	force_range_for_rox ("cnt", curi->size);
1736		if (source_is_imm1_8 (curi))
1737		printf ("{");
1738	<	else
1738	>	else {
1739	>	force_range_for_rox ("cnt", curi->size);
1740		printf ("\tif (cnt > 0) {\n");
1741	+	}
1742		printf ("\tcnt--;\n");
1743		printf ("\t{\n\tuae_u32 carry;\n");
1744		printf ("\tuae_u32 hival = (val << 1) | GET_XFLG;\n");
#	Line 2156 | Line 1894 | static void gen_opcode (unsigned long in
1894		start_brace ();
1895		printf ("\tint regno = (src >> 12) & 15;\n");
1896		printf ("\tuae_u32 *regp = regs.regs + regno;\n");
1897	<	printf ("\tm68k_movec2(src & 0xFFF, regp);\n");
1897	>	printf ("\tif (! m68k_movec2(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
1898		break;
1899		case i_MOVE2C:
1900		genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1901		start_brace ();
1902		printf ("\tint regno = (src >> 12) & 15;\n");
1903		printf ("\tuae_u32 *regp = regs.regs + regno;\n");
1904	<	printf ("\tm68k_move2c(src & 0xFFF, regp);\n");
1904	>	printf ("\tif (! m68k_move2c(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
1905		break;
1906		case i_CAS:
1907		{
#	Line 2303 | Line 2041 | static void gen_opcode (unsigned long in
2041		printf ("\ttmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));\n");
2042		}
2043		printf ("\ttmp >>= (32 - width);\n");
2044	<	printf ("\tSET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);\n");
2044	>	printf ("\tSET_NFLG_ALWAYS (tmp & (1 << (width-1)) ? 1 : 0);\n");
2045		printf ("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
2046		switch (curi->mnemo) {
2047		case i_BFTST:
#	Line 2331 | Line 2069 | static void gen_opcode (unsigned long in
2069		break;
2070		case i_BFINS:
2071		printf ("\ttmp = m68k_dreg(regs, (extra >> 12) & 7);\n");
2072	+	printf ("\tSET_NFLG_ALWAYS (tmp & (1 << (width - 1)) ? 1 : 0);\n");
2073	+	printf ("\tSET_ZFLG (tmp == 0);\n");
2074		break;
2075		default:
2076		break;
#	Line 2401 | Line 2141 | static void gen_opcode (unsigned long in
2141		genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2142		sync_m68k_pc ();
2143		swap_opcode ();
2144	<	printf ("\tfpp_opp(opcode,extra);\n");
2144	>	printf ("\tfpuop_arithmetic(opcode, extra);\n");
2145		break;
2146		case i_FDBcc:
2147		genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2148		sync_m68k_pc ();
2149		swap_opcode ();
2150	<	printf ("\tfdbcc_opp(opcode,extra);\n");
2150	>	printf ("\tfpuop_dbcc(opcode, extra);\n");
2151		break;
2152		case i_FScc:
2153		genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2154		sync_m68k_pc ();
2155		swap_opcode ();
2156	<	printf ("\tfscc_opp(opcode,extra);\n");
2156	>	printf ("\tfpuop_scc(opcode,extra);\n");
2157		break;
2158		case i_FTRAPcc:
2159		sync_m68k_pc ();
#	Line 2423 | Line 2163 | static void gen_opcode (unsigned long in
2163		genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0);
2164		sync_m68k_pc ();
2165		swap_opcode ();
2166	<	printf ("\tftrapcc_opp(opcode,oldpc);\n");
2166	>	printf ("\tfpuop_trapcc(opcode,oldpc);\n");
2167		break;
2168		case i_FBcc:
2169		sync_m68k_pc ();
#	Line 2432 | Line 2172 | static void gen_opcode (unsigned long in
2172		genamode (curi->dmode, "srcreg", curi->size, "extra", 1, 0);
2173		sync_m68k_pc ();
2174		swap_opcode ();
2175	<	printf ("\tfbcc_opp(opcode,pc,extra);\n");
2175	>	printf ("\tfpuop_bcc(opcode,pc,extra);\n");
2176		break;
2177		case i_FSAVE:
2178		sync_m68k_pc ();
2179		swap_opcode ();
2180	<	printf ("\tfsave_opp(opcode);\n");
2180	>	printf ("\tfpuop_save(opcode);\n");
2181		break;
2182		case i_FRESTORE:
2183		sync_m68k_pc ();
2184		swap_opcode ();
2185	<	printf ("\tfrestore_opp(opcode);\n");
2185	>	printf ("\tfpuop_restore(opcode);\n");
2186		break;
2187		case i_CINVL:
2188		case i_CINVP:
2189		case i_CINVA:
2190	+	/* gb-- srcreg now contains the cache field */
2191	+	printf ("\tif (srcreg&0x2)\n");
2192	+	printf ("\t\tflush_icache(%d);\n", 30 + ((opcode >> 3) & 3));
2193	+	break;
2194		case i_CPUSHL:
2195		case i_CPUSHP:
2196		case i_CPUSHA:
2197	+	/* gb-- srcreg now contains the cache field */
2198	+	printf ("\tif (srcreg&0x2)\n");
2199	+	printf ("\t\tflush_icache(%d);\n", 40 + ((opcode >> 3) & 3));
2200		break;
2201		case i_MOVE16:
2202	<	printf ("\tuaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;\n");
2203	<	printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword());
2204	<	printf ("\tmemd = m68k_areg(regs, dstreg) & ~15;\n");
2205	<	printf ("\tput_long(memd, get_long(mems));\n");
2206	<	printf ("\tput_long(memd+4, get_long(mems+4));\n");
2207	<	printf ("\tput_long(memd+8, get_long(mems+8));\n");
2208	<	printf ("\tput_long(memd+12, get_long(mems+12));\n");
2209	<	printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2210	<	printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2202	>	if ((opcode & 0xfff8) == 0xf620) {
2203	>	/* MOVE16 (Ax)+,(Ay)+ */
2204	>	printf ("\tuaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;\n");
2205	>	printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword());
2206	>	printf ("\tmemd = m68k_areg(regs, dstreg) & ~15;\n");
2207	>	printf ("\tput_long(memd, get_long(mems));\n");
2208	>	printf ("\tput_long(memd+4, get_long(mems+4));\n");
2209	>	printf ("\tput_long(memd+8, get_long(mems+8));\n");
2210	>	printf ("\tput_long(memd+12, get_long(mems+12));\n");
2211	>	printf ("\tif (srcreg != dstreg)\n");
2212	>	printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2213	>	printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2214	>	}
2215	>	else {
2216	>	/* Other variants */
2217	>	genamode (curi->smode, "srcreg", curi->size, "mems", 0, 2);
2218	>	genamode (curi->dmode, "dstreg", curi->size, "memd", 0, 2);
2219	>	printf ("\tmemsa &= ~15;\n");
2220	>	printf ("\tmemda &= ~15;\n");
2221	>	printf ("\tput_long(memda, get_long(memsa));\n");
2222	>	printf ("\tput_long(memda+4, get_long(memsa+4));\n");
2223	>	printf ("\tput_long(memda+8, get_long(memsa+8));\n");
2224	>	printf ("\tput_long(memda+12, get_long(memsa+12));\n");
2225	>	if ((opcode & 0xfff8) == 0xf600)
2226	>	printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2227	>	else if ((opcode & 0xfff8) == 0xf608)
2228	>	printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2229	>	}
2230		break;
2231		case i_MMUOP:
2232		genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
#	Line 2468 | Line 2234 | static void gen_opcode (unsigned long in
2234		swap_opcode ();
2235		printf ("\tmmu_op(opcode,extra);\n");
2236		break;
2237	+
2238	+	case i_EMULOP_RETURN:
2239	+	printf ("\tm68k_emulop_return();\n");
2240	+	m68k_pc_offset = 0;
2241	+	break;
2242	+
2243	+	case i_EMULOP:
2244	+	printf ("\n");
2245	+	swap_opcode ();
2246	+	printf ("\tm68k_emulop(opcode);\n");
2247	+	break;
2248	+
2249		default:
2250		abort ();
2251		break;
#	Line 2479 | Line 2257 | static void gen_opcode (unsigned long in
2257		static void generate_includes (FILE * f)
2258		{
2259		fprintf (f, "#include \"sysdeps.h\"\n");
2260	+
2261		fprintf (f, "#include \"m68k.h\"\n");
2262		fprintf (f, "#include \"memory.h\"\n");
2263		fprintf (f, "#include \"readcpu.h\"\n");
2264		fprintf (f, "#include \"newcpu.h\"\n");
2265	<	fprintf (f, "#include \"compiler.h\"\n");
2265	>	fprintf (f, "#include \"compiler/compemu.h\"\n");
2266	>	fprintf (f, "#include \"fpu/fpu.h\"\n");
2267		fprintf (f, "#include \"cputbl.h\"\n");
2268	+
2269	+	fprintf (f, "#define SET_CFLG_ALWAYS(x) SET_CFLG(x)\n");
2270	+	fprintf (f, "#define SET_NFLG_ALWAYS(x) SET_NFLG(x)\n");
2271	+	fprintf (f, "#define CPUFUNC_FF(x) x##_ff\n");
2272	+	fprintf (f, "#define CPUFUNC_NF(x) x##_nf\n");
2273	+	fprintf (f, "#define CPUFUNC(x) CPUFUNC_FF(x)\n");
2274	+
2275	+	fprintf (f, "#ifdef NOFLAGS\n");
2276	+	fprintf (f, "# include \"noflags.h\"\n");
2277	+	fprintf (f, "#endif\n");
2278		}
2279
2280		static int postfix;
2281
2282		static void generate_one_opcode (int rp)
2283		{
2494	–	int i;
2284		uae_u16 smsk, dmsk;
2285		long int opcode = opcode_map[rp];
2286	+	const char *opcode_str;
2287
2288		if (table68k[opcode].mnemo == i_ILLG
2289		|| table68k[opcode].clev > cpu_level)
2290		return;
2291
2502	–	for (i = 0; lookuptab[i].name[0]; i++) {
2503	–	if (table68k[opcode].mnemo == lookuptab[i].mnemo)
2504	–	break;
2505	–	}
2506	–
2292		if (table68k[opcode].handler != -1)
2293		return;
2294
2295	+	opcode_str = get_instruction_string (opcode);
2296	+
2297		if (opcode_next_clev[rp] != cpu_level) {
2298	<	fprintf (stblfile, "{ op_%lx_%d, 0, %ld }, /* %s */\n", opcode, opcode_last_postfix[rp],
2299	<	opcode, lookuptab[i].name);
2298	>	if (table68k[opcode].flagdead == 0)
2299	>	/* force to the "ff" variant since the instruction doesn't set at all the condition codes */
2300	>	fprintf (stblfile, "{ CPUFUNC_FF(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, opcode_last_postfix[rp],
2301	>	opcode, opcode_str);
2302	>	else
2303	>	fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, opcode_last_postfix[rp],
2304	>	opcode, opcode_str);
2305		return;
2306		}
2307	<	fprintf (stblfile, "{ op_%lx_%d, 0, %ld }, /* %s */\n", opcode, postfix, opcode, lookuptab[i].name);
2308	<	fprintf (headerfile, "extern cpuop_func op_%lx_%d;\n", opcode, postfix);
2309	<	printf ("void REGPARAM2 op_%lx_%d(uae_u32 opcode) /* %s */\n{\n", opcode, postfix, lookuptab[i].name);
2307	>
2308	>	if (table68k[opcode].flagdead == 0)
2309	>	/* force to the "ff" variant since the instruction doesn't set at all the condition codes */
2310	>	fprintf (stblfile, "{ CPUFUNC_FF(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, postfix, opcode, opcode_str);
2311	>	else
2312	>	fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, postfix, opcode, opcode_str);
2313	>
2314	>	fprintf (headerfile, "extern cpuop_func op_%lx_%d_nf;\n", opcode, postfix);
2315	>	fprintf (headerfile, "extern cpuop_func op_%lx_%d_ff;\n", opcode, postfix);
2316	>
2317	>	/* gb-- The "nf" variant for an instruction that doesn't set the condition
2318	>	codes at all is the same as the "ff" variant, so we don't need the "nf"
2319	>	variant to be compiled since it is mapped to the "ff" variant in the
2320	>	smalltbl. */
2321	>	if (table68k[opcode].flagdead == 0)
2322	>	printf ("#ifndef NOFLAGS\n");
2323	>
2324	>	printf ("void REGPARAM2 CPUFUNC(op_%lx_%d)(uae_u32 opcode) /* %s */\n{\n", opcode, postfix, opcode_str);
2325	>	printf ("\tcpuop_begin();\n");
2326
2327		switch (table68k[opcode].stype) {
2328		case 0: smsk = 7; break;
#	Line 2523 | Line 2331 | static void generate_one_opcode (int rp)
2331		case 3: smsk = 7; break;
2332		case 4: smsk = 7; break;
2333		case 5: smsk = 63; break;
2334	+	case 6: smsk = 255; break;
2335	+	case 7: smsk = 3; break;
2336		default: abort ();
2337		}
2338		dmsk = 7;
#	Line 2532 | Line 2342 | static void generate_one_opcode (int rp)
2342		&& table68k[opcode].smode != imm && table68k[opcode].smode != imm0
2343		&& table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2
2344		&& table68k[opcode].smode != absw && table68k[opcode].smode != absl
2345	<	&& table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16)
2345	>	&& table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16
2346	>	/* gb-- We don't want to fetch the EmulOp code since the EmulOp()
2347	>	routine uses the whole opcode value. Maybe all the EmulOps
2348	>	could be expanded out but I don't think it is an improvement */
2349	>	&& table68k[opcode].stype != 6
2350	>	)
2351		{
2352		if (table68k[opcode].spos == -1) {
2353		if (((int) table68k[opcode].sreg) >= 128)
#	Line 2628 | Line 2443 | static void generate_one_opcode (int rp)
2443		gen_opcode (opcode);
2444		if (need_endlabel)
2445		printf ("%s: ;\n", endlabelstr);
2446	+	printf ("\tcpuop_end();\n");
2447		printf ("}\n");
2448	+	if (table68k[opcode].flagdead == 0)
2449	+	printf ("\n#endif\n");
2450		opcode_next_clev[rp] = next_cpu_level;
2451		opcode_last_postfix[rp] = postfix;
2452		}
#	Line 2639 | Line 2457 | static void generate_func (void)
2457
2458		using_prefetch = 0;
2459		using_exception_3 = 0;
2460	+	#if !USE_PREFETCH_BUFFER
2461	+	/* gb-- No need for a prefetch buffer, nor exception 3 handling */
2462	+	/* Anyway, Basilisk2 does not use the op_smalltbl_5 table... */
2463	+	for (i = 0; i <= 4; i++) {
2464	+	#else
2465		for (i = 0; i < 6; i++) {
2466	+	#endif
2467		cpu_level = 4 - i;
2468		if (i == 5) {
2469		cpu_level = 0;
#	Line 2649 | Line 2473 | static void generate_func (void)
2473		opcode_next_clev[rp] = 0;
2474		}
2475		postfix = i;
2476	<	fprintf (stblfile, "struct cputbl op_smalltbl_%d[] = {\n", postfix);
2476	>	fprintf (stblfile, "struct cputbl CPUFUNC(op_smalltbl_%d)[] = {\n", postfix);
2477
2478		/* sam: this is for people with low memory (eg. me :)) */
2479		printf ("\n"
#	Line 2683 | Line 2507 | static void generate_func (void)
2507
2508		int main (int argc, char **argv)
2509		{
2510	+	FILE *out;
2511		read_table68k ();
2512		do_merges ();
2513
#	Line 2696 | Line 2521 | int main (int argc, char **argv)
2521		* cputbl.h that way), but cpuopti can't cope.  That could be fixed, but
2522		* I don't dare to touch the 68k version.  */
2523
2524	<	headerfile = fopen ("cputbl.h", "wb");
2525	<	stblfile = fopen ("cpustbl.cpp", "wb");
2526	<	freopen ("cpuemu.cpp", "wb", stdout);
2524	>	headerfile = fopen ("cputbl.h", "w");
2525	>	stblfile = fopen ("cpustbl.cpp", "w");
2526	>	out = freopen ("cpuemu.cpp", "w", stdout);
2527
2528		generate_includes (stdout);
2529		generate_includes (stblfile);
#	Line 2706 | Line 2531 | int main (int argc, char **argv)
2531		generate_func ();
2532
2533		free (table68k);
2534	+	fclose (headerfile);
2535	+	fclose (stblfile);
2536	+	fflush (out);
2537		return 0;
2538		}

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