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root/cebix/BasiliskII/src/uae_cpu/gencpu.c

Comparing BasiliskII/src/uae_cpu/gencpu.c (file contents):
Revision 1.9 by cebix, 1999-10-31T23:18:40Z vs.
Revision 1.19 by gbeauche, 2002-09-17T16:05:39Z

#	Line 221 | Line 221 | static void sync_m68k_pc (void)
221		}
222
223		/* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
224	<	* the calling routine handles Apdi and Aipi modes. */
224	>	* the calling routine handles Apdi and Aipi modes.
225	>	* gb-- movem == 2 means the same thing but for a MOVE16 instruction */
226		static void genamode (amodes mode, char *reg, wordsizes size, char *name, int getv, int movem)
227		{
228		start_brace ();
#	Line 232 | Line 233 | static void genamode (amodes mode, char
233		if (getv == 1)
234		switch (size) {
235		case sz_byte:
236	<	#ifdef AMIGA
236	>	#if defined(AMIGA) && !defined(WARPUP)
237		/* sam: I don't know why gcc.2.7.2.1 produces a code worse */
238		/* if it is not done like that: */
239		printf ("\tuae_s8 %s = ((uae_u8*)&m68k_dreg(regs, %s))[3];\n", name, reg);
#	Line 241 | Line 242 | static void genamode (amodes mode, char
242		#endif
243		break;
244		case sz_word:
245	<	#ifdef AMIGA
245	>	#if defined(AMIGA) && !defined(WARPUP)
246		printf ("\tuae_s16 %s = ((uae_s16*)&m68k_dreg(regs, %s))[1];\n", name, reg);
247		#else
248		printf ("\tuae_s16 %s = m68k_dreg(regs, %s);\n", name, reg);
#	Line 714 | Line 715 | static void genflags_normal (flagtypes t
715
716		static void genflags (flagtypes type, wordsizes size, char *value, char *src, char *dst)
717		{
718	<	#ifdef SPARC_V8_ASSEMBLY
719	<	switch(type)
720	<	{
721	<	case flag_add:
721	<	start_brace();
722	<	printf("\tuae_u32 %s;\n", value);
723	<	switch(size)
724	<	{
725	<	case sz_byte:
726	<	printf("\t%s = sparc_v8_flag_add_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
727	<	break;
728	<	case sz_word:
729	<	printf("\t%s = sparc_v8_flag_add_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
730	<	break;
731	<	case sz_long:
732	<	printf("\t%s = sparc_v8_flag_add_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
733	<	break;
734	<	}
735	<	return;
736	<
737	<	case flag_sub:
738	<	start_brace();
739	<	printf("\tuae_u32 %s;\n", value);
740	<	switch(size)
741	<	{
742	<	case sz_byte:
743	<	printf("\t%s = sparc_v8_flag_sub_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
744	<	break;
745	<	case sz_word:
746	<	printf("\t%s = sparc_v8_flag_sub_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
747	<	break;
748	<	case sz_long:
749	<	printf("\t%s = sparc_v8_flag_sub_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
750	<	break;
751	<	}
752	<	return;
753	<
754	<	case flag_cmp:
755	<	switch(size)
756	<	{
757	<	case sz_byte:
758	<	//                                      printf("\tsparc_v8_flag_cmp_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
759	<	break;
760	<	case sz_word:
761	<	//                                      printf("\tsparc_v8_flag_cmp_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
762	<	break;
763	<	case sz_long:
764	<	#if 1
765	<	printf("\tsparc_v8_flag_cmp_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
766	<	return;
767	<	#endif
768	<	break;
769	<	}
770	<	//                      return;
771	<	break;
772	<	}
773	<	#elif defined(SPARC_V9_ASSEMBLY)
774	<	switch(type)
775	<	{
776	<	case flag_add:
777	<	start_brace();
778	<	printf("\tuae_u32 %s;\n", value);
779	<	switch(size)
780	<	{
781	<	case sz_byte:
782	<	printf("\t%s = sparc_v9_flag_add_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
783	<	break;
784	<	case sz_word:
785	<	printf("\t%s = sparc_v9_flag_add_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
786	<	break;
787	<	case sz_long:
788	<	printf("\t%s = sparc_v9_flag_add_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
789	<	break;
790	<	}
791	<	return;
792	<
793	<	case flag_sub:
794	<	start_brace();
795	<	printf("\tuae_u32 %s;\n", value);
796	<	switch(size)
797	<	{
798	<	case sz_byte:
799	<	printf("\t%s = sparc_v9_flag_sub_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
800	<	break;
801	<	case sz_word:
802	<	printf("\t%s = sparc_v9_flag_sub_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
803	<	break;
804	<	case sz_long:
805	<	printf("\t%s = sparc_v9_flag_sub_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
806	<	break;
807	<	}
808	<	return;
809	<
810	<	case flag_cmp:
811	<	switch(size)
812	<	{
813	<	case sz_byte:
814	<	printf("\tsparc_v9_flag_cmp_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
815	<	break;
816	<	case sz_word:
817	<	printf("\tsparc_v9_flag_cmp_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
818	<	break;
819	<	case sz_long:
820	<	printf("\tsparc_v9_flag_cmp_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
821	<	break;
822	<	}
823	<	return;
824	<
825	<	case flag_logical:
826	<	if (strcmp(value, "0") == 0) {
827	<	printf("\tregflags.nzvc = 0x04;\n");
828	<	} else {
829	<	switch(size) {
830	<	case sz_byte:
831	<	printf("\tsparc_v9_flag_test_8(&regflags, (uae_u32)(%s));\n", value);
832	<	break;
833	<	case sz_word:
834	<	printf("\tsparc_v9_flag_test_16(&regflags, (uae_u32)(%s));\n", value);
835	<	break;
836	<	case sz_long:
837	<	printf("\tsparc_v9_flag_test_32(&regflags, (uae_u32)(%s));\n", value);
838	<	break;
839	<	}
840	<	}
841	<	return;
842	<
843	<	#if 0
844	<	case flag_logical_noclobber:
845	<	printf("\t{uae_u32 old_flags = regflags.nzvc & ~0x0C;\n");
846	<	if (strcmp(value, "0") == 0) {
847	<	printf("\tregflags.nzvc = old_flags | 0x04;\n");
848	<	} else {
849	<	switch(size) {
850	<	case sz_byte:
851	<	printf("\tsparc_v9_flag_test_8(&regflags, (uae_u32)(%s));\n", value);
852	<	break;
853	<	case sz_word:
854	<	printf("\tsparc_v9_flag_test_16(&regflags, (uae_u32)(%s));\n", value);
855	<	break;
856	<	case sz_long:
857	<	printf("\tsparc_v9_flag_test_32(&regflags, (uae_u32)(%s));\n", value);
858	<	break;
859	<	}
860	<	printf("\tregflags.nzvc |= old_flags;\n");
861	<	}
862	<	printf("\t}\n");
863	<	return;
864	<	#endif
865	<	}
866	<	#elif defined(X86_ASSEMBLY)
718	>	/* Temporarily deleted 68k/ARM flag optimizations.  I'd prefer to have
719	>	them in the appropriate m68k.h files and use just one copy of this
720	>	code here.  The API can be changed if necessary.  */
721	>	#ifdef OPTIMIZED_FLAGS
722		switch (type) {
723		case flag_add:
724		case flag_sub:
725		start_brace ();
726		printf ("\tuae_u32 %s;\n", value);
727		break;
873	–
728		default:
729		break;
730		}
#	Line 878 | Line 732 | static void genflags (flagtypes type, wo
732		/* At least some of those casts are fairly important! */
733		switch (type) {
734		case flag_logical_noclobber:
735	<	printf ("\t{uae_u32 oldcznv = regflags.cznv & ~0xC0;\n");
735	>	printf ("\t{uae_u32 oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
736		if (strcmp (value, "0") == 0) {
737	<	printf ("\tregflags.cznv = olcznv | 64;\n");
737	>	printf ("\tSET_CZNV (olcznv | FLAGVAL_Z);\n");
738		} else {
739		switch (size) {
740	<	case sz_byte: printf ("\tx86_flag_testb ((uae_s8)(%s));\n", value); break;
741	<	case sz_word: printf ("\tx86_flag_testw ((uae_s16)(%s));\n", value); break;
742	<	case sz_long: printf ("\tx86_flag_testl ((uae_s32)(%s));\n", value); break;
740	>	case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
741	>	case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
742	>	case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
743		}
744	<	printf ("\tregflags.cznv |= oldcznv;\n");
744	>	printf ("\tIOR_CZNV (oldcznv);\n");
745		}
746		printf ("\t}\n");
747		return;
748	+
749		case flag_logical:
750		if (strcmp (value, "0") == 0) {
751	<	printf ("\tregflags.cznv = 64;\n");
751	>	printf ("\tSET_CZNV (FLAGVAL_Z);\n");
752		} else {
753		switch (size) {
754	<	case sz_byte: printf ("\tx86_flag_testb ((uae_s8)(%s));\n", value); break;
755	<	case sz_word: printf ("\tx86_flag_testw ((uae_s16)(%s));\n", value); break;
756	<	case sz_long: printf ("\tx86_flag_testl ((uae_s32)(%s));\n", value); break;
754	>	case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
755	>	case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
756	>	case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
757		}
758		}
759		return;
760
761		case flag_add:
762		switch (size) {
763	<	case sz_byte: printf ("\tx86_flag_addb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
764	<	case sz_word: printf ("\tx86_flag_addw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
765	<	case sz_long: printf ("\tx86_flag_addl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
763	>	case sz_byte: printf ("\toptflag_addb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
764	>	case sz_word: printf ("\toptflag_addw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
765	>	case sz_long: printf ("\toptflag_addl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
766		}
767		return;
768
769		case flag_sub:
770		switch (size) {
771	<	case sz_byte: printf ("\tx86_flag_subb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
772	<	case sz_word: printf ("\tx86_flag_subw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
773	<	case sz_long: printf ("\tx86_flag_subl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
771	>	case sz_byte: printf ("\toptflag_subb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
772	>	case sz_word: printf ("\toptflag_subw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
773	>	case sz_long: printf ("\toptflag_subl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
774		}
775		return;
776
777		case flag_cmp:
778		switch (size) {
779	<	case sz_byte: printf ("\tx86_flag_cmpb ((uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
780	<	case sz_word: printf ("\tx86_flag_cmpw ((uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
781	<	case sz_long: printf ("\tx86_flag_cmpl ((uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
779	>	case sz_byte: printf ("\toptflag_cmpb ((uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
780	>	case sz_word: printf ("\toptflag_cmpw ((uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
781	>	case sz_long: printf ("\toptflag_cmpl ((uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
782		}
783		return;
784
785		default:
786		break;
787		}
933	–	#elif defined(M68K_FLAG_OPT)
934	–	/* sam: here I'm cloning what X86_ASSEMBLY does */
935	–	#define EXT(size)  (size==sz_byte?"b":(size==sz_word?"w":"l"))
936	–	#define CAST(size) (size==sz_byte?"uae_s8":(size==sz_word?"uae_s16":"uae_s32"))
937	–	switch (type) {
938	–	case flag_add:
939	–	case flag_sub:
940	–	start_brace ();
941	–	printf ("\tuae_u32 %s;\n", value);
942	–	break;
943	–
944	–	default:
945	–	break;
946	–	}
947	–
948	–	switch (type) {
949	–	case flag_logical:
950	–	if (strcmp (value, "0") == 0) {
951	–	printf ("\t*(uae_u16 *)&regflags = 4;\n");  /* Z = 1 */
952	–	} else {
953	–	printf ("\tm68k_flag_tst (%s, (%s)(%s));\n",
954	–	EXT (size), CAST (size), value);
955	–	}
956	–	return;
957	–
958	–	case flag_add:
959	–	printf ("\t{uae_u16 ccr;\n");
960	–	printf ("\tm68k_flag_add (%s, (%s)%s, (%s)(%s), (%s)(%s));\n",
961	–	EXT (size), CAST (size), value, CAST (size), src, CAST (size), dst);
962	–	printf ("\t((uae_u16*)&regflags)[1]=((uae_u16*)&regflags)[0]=ccr;}\n");
963	–	return;
964	–
965	–	case flag_sub:
966	–	printf ("\t{uae_u16 ccr;\n");
967	–	printf ("\tm68k_flag_sub (%s, (%s)%s, (%s)(%s), (%s)(%s));\n",
968	–	EXT (size), CAST (size), value, CAST (size), src, CAST (size), dst);
969	–	printf ("\t((uae_u16*)&regflags)[1]=((uae_u16*)&regflags)[0]=ccr;}\n");
970	–	return;
971	–
972	–	case flag_cmp:
973	–	printf ("\tm68k_flag_cmp (%s, (%s)(%s), (%s)(%s));\n",
974	–	EXT (size), CAST (size), src, CAST (size), dst);
975	–	return;
976	–
977	–	default:
978	–	break;
979	–	}
980	–	#elif defined(ACORN_FLAG_OPT) && defined(__GNUC_MINOR__)
981	–	/*
982	–	* This is new. Might be quite buggy.
983	–	*/
984	–	switch (type) {
985	–	case flag_av:
986	–	case flag_sv:
987	–	case flag_zn:
988	–	case flag_addx:
989	–	case flag_subx:
990	–	break;
991	–
992	–	case flag_logical:
993	–	if (strcmp (value, "0") == 0) {
994	–	/* v=c=n=0 z=1 */
995	–	printf ("\t*(ULONG*)&regflags = 0x40000000;\n");
996	–	return;
997	–	} else {
998	–	start_brace ();
999	–	switch (size) {
1000	–	case sz_byte:
1001	–	printf ("\tUBYTE ccr;\n");
1002	–	printf ("\tULONG shift;\n");
1003	–	printf ("\t__asm__(\"mov %%2,%%1,lsl#24\n\ttst %%2,%%2\n\tmov %%0,r15,lsr#24\n\tbic %%0,%%0,#0x30\"\n"
1004	–	"\t: \"=r\" (ccr) : \"r\" (%s), \"r\" (shift) : \"cc\" );\n", value);
1005	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1006	–	return;
1007	–	case sz_word:
1008	–	printf ("\tUBYTE ccr;\n");
1009	–	printf ("\tULONG shift;\n");
1010	–	printf ("\t__asm__(\"mov %%2,%%1,lsl#16\n\ttst %%2,%%2\n\tmov %%0,r15,lsr#24\n\tbic %%0,%%0,#0x30\"\n"
1011	–	"\t: \"=r\" (ccr) : \"r\" ((WORD)%s), \"r\" (shift) : \"cc\" );\n", value);
1012	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1013	–	return;
1014	–	case sz_long:
1015	–	printf ("\tUBYTE ccr;\n");
1016	–	printf ("\t__asm__(\"tst %%1,%%1\n\tmov %%0,r15,lsr#24\n\tbic %%0,%%0,#0x30\"\n"
1017	–	"\t: \"=r\" (ccr) : \"r\" ((LONG)%s) : \"cc\" );\n", value);
1018	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1019	–	return;
1020	–	}
1021	–	}
1022	–	break;
1023	–	case flag_add:
1024	–	if (strcmp (dst, "0") == 0) {
1025	–	printf ("/* Error! Hier muss Peter noch was machen !!! (ADD-Flags) */");
1026	–	} else {
1027	–	start_brace ();
1028	–	switch (size) {
1029	–	case sz_byte:
1030	–	printf ("\tULONG ccr, shift, %s;\n", value);
1031	–	printf ("\t__asm__(\"mov %%4,%%3,lsl#24\n\tadds %%0,%%4,%%2,lsl#24\n\tmov %%0,%%0,asr#24\n\tmov %%1,r15\n\torr %%1,%%1,%%1,lsr#29\"\n"
1032	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" (%s), \"r\" (%s), \"r\" (shift) : \"cc\" );\n", value, src, dst);
1033	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1034	–	return;
1035	–	case sz_word:
1036	–	printf ("\tULONG ccr, shift, %s;\n", value);
1037	–	printf ("\t__asm__(\"mov %%4,%%3,lsl#16\n\tadds %%0,%%4,%%2,lsl#16\n\tmov %%0,%%0,asr#16\n\tmov %%1,r15\n\torr %%1,%%1,%%1,lsr#29\"\n"
1038	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" ((WORD)%s), \"r\" ((WORD)%s), \"r\" (shift) : \"cc\" );\n", value, src, dst);
1039	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1040	–	return;
1041	–	case sz_long:
1042	–	printf ("\tULONG ccr, %s;\n", value);
1043	–	printf ("\t__asm__(\"adds %%0,%%3,%%2\n\tmov %%1,r15\n\torr %%1,%%1,%%1,lsr#29\"\n"
1044	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" ((LONG)%s), \"r\" ((LONG)%s) : \"cc\" );\n", value, src, dst);
1045	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1046	–	return;
1047	–	}
1048	–	}
1049	–	break;
1050	–	case flag_sub:
1051	–	if (strcmp (dst, "0") == 0) {
1052	–	printf ("/* Error! Hier muss Peter noch was machen !!! (SUB-Flags) */");
1053	–	} else {
1054	–	start_brace ();
1055	–	switch (size) {
1056	–	case sz_byte:
1057	–	printf ("\tULONG ccr, shift, %s;\n", value);
1058	–	printf ("\t__asm__(\"mov %%4,%%3,lsl#24\n\tsubs %%0,%%4,%%2,lsl#24\n\tmov %%0,%%0,asr#24\n\tmov %%1,r15\n\teor %%1,%%1,#0x20000000\n\torr %%1,%%1,%%1,lsr#29\"\n"
1059	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" (%s), \"r\" (%s), \"r\" (shift) : \"cc\" );\n", value, src, dst);
1060	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1061	–	return;
1062	–	case sz_word:
1063	–	printf ("\tULONG ccr, shift, %s;\n", value);
1064	–	printf ("\t__asm__(\"mov %%4,%%3,lsl#16\n\tsubs %%0,%%4,%%2,lsl#16\n\tmov %%0,%%0,asr#16\n\tmov %%1,r15\n\teor %%1,%%1,#0x20000000\n\torr %%1,%%1,%%1,lsr#29\"\n"
1065	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" ((WORD)%s), \"r\" ((WORD)%s), \"r\" (shift) : \"cc\" );\n", value, src, dst);
1066	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1067	–	return;
1068	–	case sz_long:
1069	–	printf ("\tULONG ccr, %s;\n", value);
1070	–	printf ("\t__asm__(\"subs %%0,%%3,%%2\n\tmov %%1,r15\n\teor %%1,%%1,#0x20000000\n\torr %%1,%%1,%%1,lsr#29\"\n"
1071	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" ((LONG)%s), \"r\" ((LONG)%s) : \"cc\" );\n", value, src, dst);
1072	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1073	–	return;
1074	–	}
1075	–	}
1076	–	break;
1077	–	case flag_cmp:
1078	–	if (strcmp (dst, "0") == 0) {
1079	–	printf ("/*Error! Hier muss Peter noch was machen !!! (CMP-Flags)*/");
1080	–	} else {
1081	–	start_brace ();
1082	–	switch (size) {
1083	–	case sz_byte:
1084	–	printf ("\tULONG shift, ccr;\n");
1085	–	printf ("\t__asm__(\"mov %%3,%%2,lsl#24\n\tcmp %%3,%%1,lsl#24\n\tmov %%0,r15,lsr#24\n\teor %%0,%%0,#0x20\"\n"
1086	–	"\t: \"=r\" (ccr) : \"r\" (%s), \"r\" (%s), \"r\" (shift) : \"cc\" );\n", src, dst);
1087	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1088	–	return;
1089	–	case sz_word:
1090	–	printf ("\tULONG shift, ccr;\n");
1091	–	printf ("\t__asm__(\"mov %%3,%%2,lsl#16\n\tcmp %%3,%%1,lsl#16\n\tmov %%0,r15,lsr#24\n\teor %%0,%%0,#0x20\"\n"
1092	–	"\t: \"=r\" (ccr) : \"r\" ((WORD)%s), \"r\" ((WORD)%s), \"r\" (shift) : \"cc\" );\n", src, dst);
1093	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1094	–	return;
1095	–	case sz_long:
1096	–	printf ("\tULONG ccr;\n");
1097	–	printf ("\t__asm__(\"cmp %%2,%%1\n\tmov %%0,r15,lsr#24\n\teor %%0,%%0,#0x20\"\n"
1098	–	"\t: \"=r\" (ccr) : \"r\" ((LONG)%s), \"r\" ((LONG)%s) : \"cc\" );\n", src, dst);
1099	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1100	–	/*printf ("\tprintf (\"%%08x %%08x %%08x\\n\", %s, %s, *((ULONG*)&regflags));\n", src, dst); */
1101	–	return;
1102	–	}
1103	–	}
1104	–	break;
1105	–	}
788		#endif
789		genflags_normal (type, size, value, src, dst);
790		}
#	Line 1141 | Line 823 | static int source_is_imm1_8 (struct inst
823		return i->stype == 3;
824		}
825
826	+	static const char * cflow_string_of(uae_u32 opcode)
827	+	{
828	+	const char * cflow_type_str;
829	+
830	+	int cflow_type = table68k[opcode].cflow & ~fl_trap;
831	+	switch (cflow_type) {
832	+	case fl_branch:         cflow_type_str = "CFLOW_BRANCH";                break;
833	+	case fl_jump:           cflow_type_str = "CFLOW_JUMP";                  break;
834	+	case fl_return:         cflow_type_str = "CFLOW_RETURN";                break;
835	+	default:                        cflow_type_str = "CFLOW_NORMAL";
836	+	}
837	+
838	+	/* Patch M68K_EXEC_RETURN instruction */
839	+	if (table68k[opcode].mnemo == i_EMULOP_RETURN)
840	+	cflow_type_str = "CFLOW_EXEC_RETURN";
841	+
842	+	return cflow_type_str;
843	+	}
844	+
845		static void gen_opcode (unsigned long int opcode)
846		{
847		struct instr *curi = table68k + opcode;
#	Line 1227 | Line 928 | static void gen_opcode (unsigned long in
928		genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
929		break;
930		case i_SBCD:
1230	–	/* Let's hope this works... */
931		genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
932		genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
933		start_brace ();
934		printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
935		printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
936	<	printf ("\tuae_u16 newv;\n");
937	<	printf ("\tint cflg;\n");
938	<	printf ("\tif (newv_lo > 9) { newv_lo-=6; newv_hi-=0x10; }\n");
939	<	printf ("\tnewv = newv_hi + (newv_lo & 0xF);");
940	<	printf ("\tSET_CFLG (cflg = (newv_hi & 0x1F0) > 0x90);\n");
936	>	printf ("\tuae_u16 newv, tmp_newv;\n");
937	>	printf ("\tint bcd = 0;\n");
938	>	printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
939	>	printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
940	>	printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
941	>	printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);\n");
942		duplicate_carry ();
1242	–	printf ("\tif (cflg) newv -= 0x60;\n");
943		genflags (flag_zn, curi->size, "newv", "", "");
944	<	genflags (flag_sv, curi->size, "newv", "src", "dst");
944	>	printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
945		genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
946		break;
947		case i_ADD:
#	Line 1273 | Line 973 | static void gen_opcode (unsigned long in
973		start_brace ();
974		printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);\n");
975		printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
976	<	printf ("\tuae_u16 newv;\n");
976	>	printf ("\tuae_u16 newv, tmp_newv;\n");
977		printf ("\tint cflg;\n");
978	<	printf ("\tif (newv_lo > 9) { newv_lo +=6; }\n");
979	<	printf ("\tnewv = newv_hi + newv_lo;");
980	<	printf ("\tSET_CFLG (cflg = (newv & 0x1F0) > 0x90);\n");
1281	<	duplicate_carry ();
978	>	printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
979	>	printf ("\tif (newv_lo > 9) { newv += 6; }\n");
980	>	printf ("\tcflg = (newv & 0x3F0) > 0x90;\n");
981		printf ("\tif (cflg) newv += 0x60;\n");
982	+	printf ("\tSET_CFLG (cflg);\n");
983	+	duplicate_carry ();
984		genflags (flag_zn, curi->size, "newv", "", "");
985	<	genflags (flag_sv, curi->size, "newv", "src", "dst");
985	>	printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
986		genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
987		break;
988		case i_NEG:
#	Line 1305 | Line 1006 | static void gen_opcode (unsigned long in
1006		printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n");
1007		printf ("\tuae_u16 newv;\n");
1008		printf ("\tint cflg;\n");
1009	<	printf ("\tif (newv_lo > 9) { newv_lo-=6; newv_hi-=0x10; }\n");
1010	<	printf ("\tnewv = newv_hi + (newv_lo & 0xF);");
1011	<	printf ("\tSET_CFLG (cflg = (newv_hi & 0x1F0) > 0x90);\n");
1311	<	duplicate_carry();
1009	>	printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
1010	>	printf ("\tnewv = newv_hi + newv_lo;\n");
1011	>	printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
1012		printf ("\tif (cflg) newv -= 0x60;\n");
1013	+	printf ("\tSET_CFLG (cflg);\n");
1014	+	duplicate_carry();
1015		genflags (flag_zn, curi->size, "newv", "", "");
1016		genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1017		break;
#	Line 1346 | Line 1048 | static void gen_opcode (unsigned long in
1048		else
1049		printf ("\tsrc &= 31;\n");
1050		printf ("\tdst ^= (1 << src);\n");
1051	<	printf ("\tSET_ZFLG ((dst & (1 << src)) >> src);\n");
1051	>	printf ("\tSET_ZFLG (((uae_u32)dst & (1 << src)) >> src);\n");
1052		genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1053		break;
1054		case i_BCLR:
#	Line 1517 | Line 1219 | static void gen_opcode (unsigned long in
1219		printf ("\tif ((format & 0xF000) == 0x0000) { break; }\n");
1220		printf ("\telse if ((format & 0xF000) == 0x1000) { ; }\n");
1221		printf ("\telse if ((format & 0xF000) == 0x2000) { m68k_areg(regs, 7) += 4; break; }\n");
1222	+	/* gb-- the next two lines are deleted in Bernie's gencpu.c */
1223		printf ("\telse if ((format & 0xF000) == 0x3000) { m68k_areg(regs, 7) += 4; break; }\n");
1224		printf ("\telse if ((format & 0xF000) == 0x7000) { m68k_areg(regs, 7) += 52; break; }\n");
1225		printf ("\telse if ((format & 0xF000) == 0x8000) { m68k_areg(regs, 7) += 50; break; }\n");
#	Line 1535 | Line 1238 | static void gen_opcode (unsigned long in
1238		m68k_pc_offset = 0;
1239		break;
1240		case i_RTD:
1538	–	printf ("\tcompiler_flush_jsr_stack();\n");
1241		genamode (Aipi, "7", sz_long, "pc", 1, 0);
1242		genamode (curi->smode, "srcreg", curi->size, "offs", 1, 0);
1243		printf ("\tm68k_areg(regs, 7) += offs;\n");
#	Line 1569 | Line 1271 | static void gen_opcode (unsigned long in
1271		need_endlabel = 1;
1272		break;
1273		case i_RTR:
1572	–	printf ("\tcompiler_flush_jsr_stack();\n");
1274		printf ("\tMakeSR();\n");
1275		genamode (Aipi, "7", sz_word, "sr", 1, 0);
1276		genamode (Aipi, "7", sz_long, "pc", 1, 0);
#	Line 1607 | Line 1308 | static void gen_opcode (unsigned long in
1308		m68k_pc_offset = 0;
1309		break;
1310		case i_Bcc:
1311	+	if (0 && !using_prefetch && !using_exception_3 && (cpu_level >= 2)) {
1312	+	/* gb-- variant probably more favorable to compiler optimizations
1313	+	also assumes no prefetch buffer is used
1314	+	Hmm, that would make sense with processors capable of conditional moves */
1315	+	if (curi->size == sz_long && next_cpu_level < 1)
1316	+	next_cpu_level = 1;
1317	+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1318	+	printf ("\tm68k_incpc (cctrue(%d) ? ((uae_s32)src + 2) : %d);\n", curi->cc, m68k_pc_offset);
1319	+	m68k_pc_offset = 0;
1320	+	}
1321	+	else {
1322	+	/* original code for branch instructions */
1323		if (curi->size == sz_long) {
1324		if (cpu_level < 2) {
1325		printf ("\tm68k_incpc(2);\n");
#	Line 1630 | Line 1343 | static void gen_opcode (unsigned long in
1343		printf ("\t}\n");
1344		need_endlabel = 1;
1345		}
1633	–	#ifdef USE_COMPILER
1634	–	printf ("\tm68k_setpc_bcc(m68k_getpc() + 2 + (uae_s32)src);\n");
1635	–	#else
1346		printf ("\tm68k_incpc ((uae_s32)src + 2);\n");
1637	–	#endif
1347		fill_prefetch_0 ();
1348	<	printf ("\tgoto %s;\n", endlabelstr);
1348	>	printf ("cpuop_return(%s);\n", cflow_string_of(opcode));
1349		printf ("didnt_jump:;\n");
1350		need_endlabel = 1;
1351	+	}
1352		break;
1353		case i_LEA:
1354		genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
#	Line 1666 | Line 1376 | static void gen_opcode (unsigned long in
1376		printf ("\t\t}\n");
1377		need_endlabel = 1;
1378		}
1669	–	#ifdef USE_COMPILER
1670	–	printf ("\t\t\tm68k_setpc_bcc(m68k_getpc() + (uae_s32)offs + 2);\n");
1671	–	#else
1379		printf ("\t\t\tm68k_incpc((uae_s32)offs + 2);\n");
1673	–	#endif
1380		fill_prefetch_0 ();
1381	<	printf ("\t\tgoto %s;\n", endlabelstr);
1381	>	printf ("cpuop_return(%s);\n", cflow_string_of(opcode));
1382		printf ("\t\t}\n");
1383		printf ("\t}\n");
1384		need_endlabel = 1;
#	Line 1687 | Line 1393 | static void gen_opcode (unsigned long in
1393		printf ("\tuaecptr oldpc = m68k_getpc();\n");
1394		genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1395		genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1396	<	printf ("\tif(src == 0) { Exception(5,oldpc); goto %s; } else {\n", endlabelstr);
1396	>	sync_m68k_pc ();
1397	>	/* Clear V flag when dividing by zero - Alcatraz Odyssey demo depends
1398	>	* on this (actually, it's doing a DIVS).  */
1399	>	printf ("\tif (src == 0) { SET_VFLG (0); Exception (5, oldpc); goto %s; } else {\n", endlabelstr);
1400		printf ("\tuae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;\n");
1401		printf ("\tuae_u32 rem = (uae_u32)dst %% (uae_u32)(uae_u16)src;\n");
1402		/* The N flag appears to be set each time there is an overflow.
#	Line 1705 | Line 1414 | static void gen_opcode (unsigned long in
1414		printf ("\tuaecptr oldpc = m68k_getpc();\n");
1415		genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1416		genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1417	<	printf ("\tif(src == 0) { Exception(5,oldpc); goto %s; } else {\n", endlabelstr);
1417	>	sync_m68k_pc ();
1418	>	printf ("\tif (src == 0) { SET_VFLG (0); Exception(5,oldpc); goto %s; } else {\n", endlabelstr);
1419		printf ("\tuae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;\n");
1420		printf ("\tuae_u16 rem = (uae_s32)dst %% (uae_s32)(uae_s16)src;\n");
1421		printf ("\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n");
#	Line 1766 | Line 1476 | static void gen_opcode (unsigned long in
1476		abort ();
1477		}
1478		printf ("\tSET_ZFLG (upper == reg || lower == reg);\n");
1479	<	printf ("\tSET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
1479	>	printf ("\tSET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
1480		printf ("\tif ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc); goto %s; }\n}\n", endlabelstr);
1481		need_endlabel = 1;
1482		break;
#	Line 1965 | Line 1675 | static void gen_opcode (unsigned long in
1675		}
1676		printf ("\tcnt &= 63;\n");
1677		printf ("\tCLEAR_CZNV;\n");
1968	–	if (! source_is_imm1_8 (curi))
1969	–	force_range_for_rox ("cnt", curi->size);
1678		if (source_is_imm1_8 (curi))
1679		printf ("{");
1680	<	else
1680	>	else {
1681	>	force_range_for_rox ("cnt", curi->size);
1682		printf ("\tif (cnt > 0) {\n");
1683	+	}
1684		printf ("\tcnt--;\n");
1685		printf ("\t{\n\tuae_u32 carry;\n");
1686		printf ("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
#	Line 1995 | Line 1705 | static void gen_opcode (unsigned long in
1705		}
1706		printf ("\tcnt &= 63;\n");
1707		printf ("\tCLEAR_CZNV;\n");
1998	–	if (! source_is_imm1_8 (curi))
1999	–	force_range_for_rox ("cnt", curi->size);
1708		if (source_is_imm1_8 (curi))
1709		printf ("{");
1710	<	else
1710	>	else {
1711	>	force_range_for_rox ("cnt", curi->size);
1712		printf ("\tif (cnt > 0) {\n");
1713	+	}
1714		printf ("\tcnt--;\n");
1715		printf ("\t{\n\tuae_u32 carry;\n");
1716		printf ("\tuae_u32 hival = (val << 1) | GET_XFLG;\n");
#	Line 2156 | Line 1866 | static void gen_opcode (unsigned long in
1866		start_brace ();
1867		printf ("\tint regno = (src >> 12) & 15;\n");
1868		printf ("\tuae_u32 *regp = regs.regs + regno;\n");
1869	<	printf ("\tm68k_movec2(src & 0xFFF, regp);\n");
1869	>	printf ("\tif (! m68k_movec2(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
1870		break;
1871		case i_MOVE2C:
1872		genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1873		start_brace ();
1874		printf ("\tint regno = (src >> 12) & 15;\n");
1875		printf ("\tuae_u32 *regp = regs.regs + regno;\n");
1876	<	printf ("\tm68k_move2c(src & 0xFFF, regp);\n");
1876	>	printf ("\tif (! m68k_move2c(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
1877		break;
1878		case i_CAS:
1879		{
#	Line 2303 | Line 2013 | static void gen_opcode (unsigned long in
2013		printf ("\ttmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));\n");
2014		}
2015		printf ("\ttmp >>= (32 - width);\n");
2016	<	printf ("\tSET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);\n");
2016	>	printf ("\tSET_NFLG_ALWAYS (tmp & (1 << (width-1)) ? 1 : 0);\n");
2017		printf ("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
2018		switch (curi->mnemo) {
2019		case i_BFTST:
#	Line 2331 | Line 2041 | static void gen_opcode (unsigned long in
2041		break;
2042		case i_BFINS:
2043		printf ("\ttmp = m68k_dreg(regs, (extra >> 12) & 7);\n");
2044	+	printf ("\tSET_NFLG_ALWAYS (tmp & (1 << (width - 1)) ? 1 : 0);\n");
2045	+	printf ("\tSET_ZFLG (tmp == 0);\n");
2046		break;
2047		default:
2048		break;
#	Line 2401 | Line 2113 | static void gen_opcode (unsigned long in
2113		genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2114		sync_m68k_pc ();
2115		swap_opcode ();
2116	<	printf ("\tfpp_opp(opcode,extra);\n");
2116	>	printf ("\tfpuop_arithmetic(opcode, extra);\n");
2117		break;
2118		case i_FDBcc:
2119		genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2120		sync_m68k_pc ();
2121		swap_opcode ();
2122	<	printf ("\tfdbcc_opp(opcode,extra);\n");
2122	>	printf ("\tfpuop_dbcc(opcode, extra);\n");
2123		break;
2124		case i_FScc:
2125		genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2126		sync_m68k_pc ();
2127		swap_opcode ();
2128	<	printf ("\tfscc_opp(opcode,extra);\n");
2128	>	printf ("\tfpuop_scc(opcode,extra);\n");
2129		break;
2130		case i_FTRAPcc:
2131		sync_m68k_pc ();
#	Line 2423 | Line 2135 | static void gen_opcode (unsigned long in
2135		genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0);
2136		sync_m68k_pc ();
2137		swap_opcode ();
2138	<	printf ("\tftrapcc_opp(opcode,oldpc);\n");
2138	>	printf ("\tfpuop_trapcc(opcode,oldpc);\n");
2139		break;
2140		case i_FBcc:
2141		sync_m68k_pc ();
#	Line 2432 | Line 2144 | static void gen_opcode (unsigned long in
2144		genamode (curi->dmode, "srcreg", curi->size, "extra", 1, 0);
2145		sync_m68k_pc ();
2146		swap_opcode ();
2147	<	printf ("\tfbcc_opp(opcode,pc,extra);\n");
2147	>	printf ("\tfpuop_bcc(opcode,pc,extra);\n");
2148		break;
2149		case i_FSAVE:
2150		sync_m68k_pc ();
2151		swap_opcode ();
2152	<	printf ("\tfsave_opp(opcode);\n");
2152	>	printf ("\tfpuop_save(opcode);\n");
2153		break;
2154		case i_FRESTORE:
2155		sync_m68k_pc ();
2156		swap_opcode ();
2157	<	printf ("\tfrestore_opp(opcode);\n");
2157	>	printf ("\tfpuop_restore(opcode);\n");
2158		break;
2159		case i_CINVL:
2160		case i_CINVP:
2161		case i_CINVA:
2162	+	/* gb-- srcreg now contains the cache field */
2163	+	printf ("\tif (srcreg&0x2)\n");
2164	+	printf ("\t\tflush_icache(%d);\n", 30 + ((opcode >> 3) & 3));
2165	+	break;
2166		case i_CPUSHL:
2167		case i_CPUSHP:
2168		case i_CPUSHA:
2169	+	/* gb-- srcreg now contains the cache field */
2170	+	printf ("\tif (srcreg&0x2)\n");
2171	+	printf ("\t\tflush_icache(%d);\n", 40 + ((opcode >> 3) & 3));
2172		break;
2173		case i_MOVE16:
2174	<	printf ("\tuaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;\n");
2175	<	printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword());
2176	<	printf ("\tmemd = m68k_areg(regs, dstreg) & ~15;\n");
2177	<	printf ("\tput_long(memd, get_long(mems));\n");
2178	<	printf ("\tput_long(memd+4, get_long(mems+4));\n");
2179	<	printf ("\tput_long(memd+8, get_long(mems+8));\n");
2180	<	printf ("\tput_long(memd+12, get_long(mems+12));\n");
2181	<	printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2182	<	printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2174	>	if ((opcode & 0xfff8) == 0xf620) {
2175	>	/* MOVE16 (Ax)+,(Ay)+ */
2176	>	printf ("\tuaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;\n");
2177	>	printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword());
2178	>	printf ("\tmemd = m68k_areg(regs, dstreg) & ~15;\n");
2179	>	printf ("\tput_long(memd, get_long(mems));\n");
2180	>	printf ("\tput_long(memd+4, get_long(mems+4));\n");
2181	>	printf ("\tput_long(memd+8, get_long(mems+8));\n");
2182	>	printf ("\tput_long(memd+12, get_long(mems+12));\n");
2183	>	printf ("\tif (srcreg != dstreg)\n");
2184	>	printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2185	>	printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2186	>	}
2187	>	else {
2188	>	/* Other variants */
2189	>	genamode (curi->smode, "srcreg", curi->size, "mems", 0, 2);
2190	>	genamode (curi->dmode, "dstreg", curi->size, "memd", 0, 2);
2191	>	printf ("\tmemsa &= ~15;\n");
2192	>	printf ("\tmemda &= ~15;\n");
2193	>	printf ("\tput_long(memda, get_long(memsa));\n");
2194	>	printf ("\tput_long(memda+4, get_long(memsa+4));\n");
2195	>	printf ("\tput_long(memda+8, get_long(memsa+8));\n");
2196	>	printf ("\tput_long(memda+12, get_long(memsa+12));\n");
2197	>	if ((opcode & 0xfff8) == 0xf600)
2198	>	printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2199	>	else if ((opcode & 0xfff8) == 0xf608)
2200	>	printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2201	>	}
2202		break;
2203		case i_MMUOP:
2204		genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
#	Line 2468 | Line 2206 | static void gen_opcode (unsigned long in
2206		swap_opcode ();
2207		printf ("\tmmu_op(opcode,extra);\n");
2208		break;
2209	+
2210	+	case i_EMULOP_RETURN:
2211	+	printf ("\tm68k_emulop_return();\n");
2212	+	m68k_pc_offset = 0;
2213	+	break;
2214	+
2215	+	case i_EMULOP:
2216	+	printf ("\n");
2217	+	swap_opcode ();
2218	+	printf ("\tm68k_emulop(opcode);\n");
2219	+	break;
2220	+
2221		default:
2222		abort ();
2223		break;
#	Line 2479 | Line 2229 | static void gen_opcode (unsigned long in
2229		static void generate_includes (FILE * f)
2230		{
2231		fprintf (f, "#include \"sysdeps.h\"\n");
2232	+
2233		fprintf (f, "#include \"m68k.h\"\n");
2234		fprintf (f, "#include \"memory.h\"\n");
2235		fprintf (f, "#include \"readcpu.h\"\n");
2236		fprintf (f, "#include \"newcpu.h\"\n");
2237	<	fprintf (f, "#include \"compiler.h\"\n");
2237	>	fprintf (f, "#include \"compiler/compemu.h\"\n");
2238	>	fprintf (f, "#include \"fpu/fpu.h\"\n");
2239		fprintf (f, "#include \"cputbl.h\"\n");
2240	+
2241	+	fprintf (f, "#define SET_CFLG_ALWAYS(x) SET_CFLG(x)\n");
2242	+	fprintf (f, "#define SET_NFLG_ALWAYS(x) SET_NFLG(x)\n");
2243	+	fprintf (f, "#define CPUFUNC_FF(x) x##_ff\n");
2244	+	fprintf (f, "#define CPUFUNC_NF(x) x##_nf\n");
2245	+	fprintf (f, "#define CPUFUNC(x) CPUFUNC_FF(x)\n");
2246	+
2247	+	fprintf (f, "#ifdef NOFLAGS\n");
2248	+	fprintf (f, "# include \"noflags.h\"\n");
2249	+	fprintf (f, "#endif\n");
2250		}
2251
2252		static int postfix;
#	Line 2508 | Line 2270 | static void generate_one_opcode (int rp)
2270		return;
2271
2272		if (opcode_next_clev[rp] != cpu_level) {
2273	<	fprintf (stblfile, "{ op_%lx_%d, 0, %ld }, /* %s */\n", opcode, opcode_last_postfix[rp],
2273	>	fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, opcode_last_postfix[rp],
2274		opcode, lookuptab[i].name);
2275		return;
2276		}
2277	<	fprintf (stblfile, "{ op_%lx_%d, 0, %ld }, /* %s */\n", opcode, postfix, opcode, lookuptab[i].name);
2278	<	fprintf (headerfile, "extern cpuop_func op_%lx_%d;\n", opcode, postfix);
2279	<	printf ("void REGPARAM2 op_%lx_%d(uae_u32 opcode) /* %s */\n{\n", opcode, postfix, lookuptab[i].name);
2277	>
2278	>	if (table68k[opcode].flagdead == 0)
2279	>	/* force to the "ff" variant since the instruction doesn't set at all the condition codes */
2280	>	fprintf (stblfile, "{ CPUFUNC_FF(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, postfix, opcode, lookuptab[i].name);
2281	>	else
2282	>	fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, postfix, opcode, lookuptab[i].name);
2283	>
2284	>	fprintf (headerfile, "extern cpuop_func op_%lx_%d_nf;\n", opcode, postfix);
2285	>	fprintf (headerfile, "extern cpuop_func op_%lx_%d_ff;\n", opcode, postfix);
2286	>	printf ("cpuop_rettype REGPARAM2 CPUFUNC(op_%lx_%d)(uae_u32 opcode) /* %s */\n{\n", opcode, postfix, lookuptab[i].name);
2287	>	printf ("\tcpuop_begin();\n");
2288	>
2289	>	/* gb-- The "nf" variant for an instruction that doesn't set the condition
2290	>	codes at all is the same as the "ff" variant, so we don't need the "nf"
2291	>	variant to be compiled since it is mapped to the "ff" variant in the
2292	>	smalltbl. */
2293	>	if (table68k[opcode].flagdead == 0)
2294	>	printf ("#ifndef NOFLAGS\n");
2295
2296		switch (table68k[opcode].stype) {
2297		case 0: smsk = 7; break;
#	Line 2523 | Line 2300 | static void generate_one_opcode (int rp)
2300		case 3: smsk = 7; break;
2301		case 4: smsk = 7; break;
2302		case 5: smsk = 63; break;
2303	+	case 6: smsk = 255; break;
2304	+	case 7: smsk = 3; break;
2305		default: abort ();
2306		}
2307		dmsk = 7;
#	Line 2532 | Line 2311 | static void generate_one_opcode (int rp)
2311		&& table68k[opcode].smode != imm && table68k[opcode].smode != imm0
2312		&& table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2
2313		&& table68k[opcode].smode != absw && table68k[opcode].smode != absl
2314	<	&& table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16)
2314	>	&& table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16
2315	>	/* gb-- We don't want to fetch the EmulOp code since the EmulOp()
2316	>	routine uses the whole opcode value. Maybe all the EmulOps
2317	>	could be expanded out but I don't think it is an improvement */
2318	>	&& table68k[opcode].stype != 6
2319	>	)
2320		{
2321		if (table68k[opcode].spos == -1) {
2322		if (((int) table68k[opcode].sreg) >= 128)
#	Line 2628 | Line 2412 | static void generate_one_opcode (int rp)
2412		gen_opcode (opcode);
2413		if (need_endlabel)
2414		printf ("%s: ;\n", endlabelstr);
2415	+	if (table68k[opcode].flagdead == 0)
2416	+	printf ("\n#endif\n");
2417	+	printf ("\tcpuop_end(%s);\n", cflow_string_of(opcode));
2418		printf ("}\n");
2419		opcode_next_clev[rp] = next_cpu_level;
2420		opcode_last_postfix[rp] = postfix;
#	Line 2639 | Line 2426 | static void generate_func (void)
2426
2427		using_prefetch = 0;
2428		using_exception_3 = 0;
2429	+	#if !USE_PREFETCH_BUFFER
2430	+	/* gb-- No need for a prefetch buffer, nor exception 3 handling */
2431	+	/* Anyway, Basilisk2 does not use the op_smalltbl_5 table... */
2432	+	for (i = 0; i <= 4; i++) {
2433	+	#else
2434		for (i = 0; i < 6; i++) {
2435	+	#endif
2436		cpu_level = 4 - i;
2437		if (i == 5) {
2438		cpu_level = 0;
#	Line 2649 | Line 2442 | static void generate_func (void)
2442		opcode_next_clev[rp] = 0;
2443		}
2444		postfix = i;
2445	<	fprintf (stblfile, "struct cputbl op_smalltbl_%d[] = {\n", postfix);
2445	>	fprintf (stblfile, "struct cputbl CPUFUNC(op_smalltbl_%d)[] = {\n", postfix);
2446
2447		/* sam: this is for people with low memory (eg. me :)) */
2448		printf ("\n"

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