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/* |
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* fpu_x86.h - 68881/68040 fpu code for x86/Windows and Linux/x86. |
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* |
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* Basilisk II (C) 1997-2001 Christian Bauer |
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* |
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* MC68881 emulation |
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* |
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* Based on UAE FPU, original copyright 1996 Herman ten Brugge, |
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* rewritten by Lauri Pesonen 1999-2000, |
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* accomodated to GCC's Extended Asm syntax by Gwenole Beauchesne 2000. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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*/ |
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|
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/* gb-- defined in newcpu.h |
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// is_integral: true == 68040, false == 68881 |
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void fpu_set_integral_fpu( bool is_integral ); |
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|
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// MUST be called before the cpu starts up. |
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void fpu_init( void ); |
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|
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// Finalize. |
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void fpu_exit( void ); |
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|
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// Soft reset. |
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void fpu_reset( void ); |
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*/ |
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|
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// The same as original. "ftrapcc_opp" is bound to change soon. |
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/* gb-- defined in newcpu.h |
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void REGPARAM2 fpp_opp (uae_u32, uae_u16); |
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void REGPARAM2 fdbcc_opp (uae_u32, uae_u16); |
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void REGPARAM2 fscc_opp (uae_u32, uae_u16); |
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void REGPARAM2 ftrapcc_opp (uae_u32,uaecptr); |
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void REGPARAM2 fbcc_opp (uae_u32, uaecptr, uae_u32); |
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void REGPARAM2 fsave_opp (uae_u32); |
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void REGPARAM2 frestore_opp (uae_u32); |
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*/ |
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|
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/* ---------------------------- Motorola ---------------------------- */ |
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|
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// Exception byte |
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#define BSUN 0x00008000 |
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#define SNAN 0x00004000 |
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#define OPERR 0x00002000 |
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#define OVFL 0x00001000 |
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#define UNFL 0x00000800 |
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#define DZ 0x00000400 |
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#define INEX2 0x00000200 |
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#define INEX1 0x00000100 |
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|
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// Accrued exception byte |
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#define ACCR_IOP 0x80 |
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#define ACCR_OVFL 0x40 |
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#define ACCR_UNFL 0x20 |
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#define ACCR_DZ 0x10 |
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#define ACCR_INEX 0x08 |
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|
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// fpcr rounding modes |
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#define ROUND_CONTROL_MASK 0x30 |
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#define ROUND_TO_NEAREST 0 |
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#define ROUND_TO_ZERO 0x10 |
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#define ROUND_TO_NEGATIVE_INFINITY 0x20 |
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#define ROUND_TO_POSITIVE_INFINITY 0x30 |
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|
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// fpcr precision control |
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#define PRECISION_CONTROL_MASK 0xC0 |
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#define PRECISION_CONTROL_EXTENDED 0 |
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#define PRECISION_CONTROL_DOUBLE 0x80 |
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#define PRECISION_CONTROL_SINGLE 0x40 |
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#define PRECISION_CONTROL_UNDEFINED 0xC0 |
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|
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|
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/* ---------------------------- Intel ---------------------------- */ |
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|
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#define CW_RESET 0x0040 // initial CW value after RESET |
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#define CW_FINIT 0x037F // initial CW value after FINIT |
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#define SW_RESET 0x0000 // initial SW value after RESET |
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#define SW_FINIT 0x0000 // initial SW value after FINIT |
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#define TW_RESET 0x5555 // initial TW value after RESET |
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#define TW_FINIT 0x0FFF // initial TW value after FINIT |
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|
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#define CW_X 0x1000 // infinity control |
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#define CW_RC_ZERO 0x0C00 // rounding control toward zero |
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#define CW_RC_UP 0x0800 // rounding control toward + |
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#define CW_RC_DOWN 0x0400 // rounding control toward - |
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#define CW_RC_NEAR 0x0000 // rounding control toward even |
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#define CW_PC_EXTENDED 0x0300 // precision control 64bit |
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#define CW_PC_DOUBLE 0x0200 // precision control 53bit |
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#define CW_PC_RESERVED 0x0100 // precision control reserved |
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#define CW_PC_SINGLE 0x0000 // precision control 24bit |
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#define CW_PM 0x0020 // precision exception mask |
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#define CW_UM 0x0010 // underflow exception mask |
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#define CW_OM 0x0008 // overflow exception mask |
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#define CW_ZM 0x0004 // zero divide exception mask |
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#define CW_DM 0x0002 // denormalized operand exception mask |
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#define CW_IM 0x0001 // invalid operation exception mask |
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|
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#define SW_B 0x8000 // busy flag |
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#define SW_C3 0x4000 // condition code flag 3 |
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#define SW_TOP_7 0x3800 // top of stack = ST(7) |
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#define SW_TOP_6 0x3000 // top of stack = ST(6) |
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#define SW_TOP_5 0x2800 // top of stack = ST(5) |
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#define SW_TOP_4 0x2000 // top of stack = ST(4) |
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#define SW_TOP_3 0x1800 // top of stack = ST(3) |
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#define SW_TOP_2 0x1000 // top of stack = ST(2) |
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#define SW_TOP_1 0x0800 // top of stack = ST(1) |
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#define SW_TOP_0 0x0000 // top of stack = ST(0) |
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#define SW_C2 0x0400 // condition code flag 2 |
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#define SW_C1 0x0200 // condition code flag 1 |
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#define SW_C0 0x0100 // condition code flag 0 |
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#define SW_ES 0x0080 // error summary status flag |
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#define SW_SF 0x0040 // stack fault flag |
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#define SW_PE 0x0020 // precision exception flag |
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#define SW_UE 0x0010 // underflow exception flag |
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#define SW_OE 0x0008 // overflow exception flag |
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#define SW_ZE 0x0004 // zero divide exception flag |
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#define SW_DE 0x0002 // denormalized operand exception flag |
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#define SW_IE 0x0001 // invalid operation exception flag |
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|
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#define X86_ROUND_CONTROL_MASK 0x0C00 |
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#define X86_PRECISION_CONTROL_MASK 0x0300 |
