uae_cpu/fpu/fpu_x86.h

/*
 *  fpu_x86.h - 68881/68040 fpu code for x86/Windows and Linux/x86.
 *
 *  Basilisk II (C) 1997-2001 Christian Bauer
 *
 *  MC68881 emulation
 *
 *  Based on UAE FPU, original copyright 1996 Herman ten Brugge,
 *  rewritten by Lauri Pesonen 1999-2000,
 *  accomodated to GCC's Extended Asm syntax by Gwenole Beauchesne 2000.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/* gb-- defined in newcpu.h
// is_integral: true == 68040, false == 68881
void fpu_set_integral_fpu( bool is_integral );

// MUST be called before the cpu starts up.
void fpu_init( void );

// Finalize.
void fpu_exit( void );

// Soft reset.
void fpu_reset( void );
*/

// The same as original. "ftrapcc_opp" is bound to change soon.
/* gb-- defined in newcpu.h
void REGPARAM2 fpp_opp (uae_u32, uae_u16);
void REGPARAM2 fdbcc_opp (uae_u32, uae_u16);
void REGPARAM2 fscc_opp (uae_u32, uae_u16);
void REGPARAM2 ftrapcc_opp (uae_u32,uaecptr);
void REGPARAM2 fbcc_opp (uae_u32, uaecptr, uae_u32);
void REGPARAM2 fsave_opp (uae_u32);
void REGPARAM2 frestore_opp (uae_u32);
*/

/* ---------------------------- Motorola ---------------------------- */

// Exception byte
#define BSUN            0x00008000
#define SNAN            0x00004000
#define OPERR           0x00002000
#define OVFL            0x00001000
#define UNFL            0x00000800
#define DZ                      0x00000400
#define INEX2           0x00000200
#define INEX1           0x00000100

// Accrued exception byte
#define ACCR_IOP        0x80
#define ACCR_OVFL       0x40
#define ACCR_UNFL       0x20
#define ACCR_DZ         0x10
#define ACCR_INEX       0x08

// fpcr rounding modes
#define ROUND_CONTROL_MASK                              0x30
#define ROUND_TO_NEAREST                                0
#define ROUND_TO_ZERO                                   0x10
#define ROUND_TO_NEGATIVE_INFINITY              0x20
#define ROUND_TO_POSITIVE_INFINITY              0x30

// fpcr precision control
#define PRECISION_CONTROL_MASK                  0xC0
#define PRECISION_CONTROL_EXTENDED              0
#define PRECISION_CONTROL_DOUBLE                0x80
#define PRECISION_CONTROL_SINGLE                0x40
#define PRECISION_CONTROL_UNDEFINED             0xC0


/* ---------------------------- Intel ---------------------------- */

#define CW_RESET                0x0040           // initial CW value after RESET
#define CW_FINIT                0x037F           // initial CW value after FINIT
#define SW_RESET                0x0000           // initial SW value after RESET
#define SW_FINIT                0x0000           // initial SW value after FINIT
#define TW_RESET                0x5555           // initial TW value after RESET
#define TW_FINIT                0x0FFF           // initial TW value after FINIT

#define CW_X                    0x1000           // infinity control
#define CW_RC_ZERO              0x0C00           // rounding control toward zero
#define CW_RC_UP                0x0800           // rounding control toward +
#define CW_RC_DOWN              0x0400           // rounding control toward -
#define CW_RC_NEAR              0x0000           // rounding control toward even
#define CW_PC_EXTENDED          0x0300           // precision control 64bit
#define CW_PC_DOUBLE            0x0200           // precision control 53bit
#define CW_PC_RESERVED          0x0100           // precision control reserved
#define CW_PC_SINGLE            0x0000           // precision control 24bit
#define CW_PM                   0x0020           // precision exception mask
#define CW_UM                   0x0010           // underflow exception mask
#define CW_OM                   0x0008           // overflow exception mask
#define CW_ZM                   0x0004           // zero divide exception mask
#define CW_DM                   0x0002           // denormalized operand exception mask
#define CW_IM                   0x0001           // invalid operation exception mask

#define SW_B                    0x8000           // busy flag
#define SW_C3                   0x4000           // condition code flag 3
#define SW_TOP_7                0x3800           // top of stack = ST(7)
#define SW_TOP_6                0x3000           // top of stack = ST(6)
#define SW_TOP_5                0x2800           // top of stack = ST(5)
#define SW_TOP_4                0x2000           // top of stack = ST(4)
#define SW_TOP_3                0x1800           // top of stack = ST(3)
#define SW_TOP_2                0x1000           // top of stack = ST(2)
#define SW_TOP_1                0x0800           // top of stack = ST(1)
#define SW_TOP_0                0x0000           // top of stack = ST(0)
#define SW_C2                   0x0400           // condition code flag 2
#define SW_C1                   0x0200           // condition code flag 1
#define SW_C0                   0x0100           // condition code flag 0
#define SW_ES                   0x0080           // error summary status flag
#define SW_SF                   0x0040           // stack fault flag
#define SW_PE                   0x0020           // precision exception flag
#define SW_UE                   0x0010           // underflow exception flag
#define SW_OE                   0x0008           // overflow exception flag
#define SW_ZE                   0x0004           // zero divide exception flag
#define SW_DE                   0x0002           // denormalized operand exception flag
#define SW_IE                   0x0001           // invalid operation exception flag

#define X86_ROUND_CONTROL_MASK                  0x0C00
#define X86_PRECISION_CONTROL_MASK              0x0300
Revision:	1.1
Committed:	2001-03-20T18:05:36Z (23 years, 8 months ago) by gbeauche
Content type:	text/plain
Branch:	MAIN
CVS Tags:	snapshot-15012002, snapshot-29052001, release-0_9-1
Log Message:	Moved FPU emulation code sources to uae_cpu/fpu/
#	User	Rev	Content
1	gbeauche	1.1	/*
2			* fpu_x86.h - 68881/68040 fpu code for x86/Windows and Linux/x86.
3			*
4			* Basilisk II (C) 1997-2001 Christian Bauer
5			*
6			* MC68881 emulation
7			*
8			* Based on UAE FPU, original copyright 1996 Herman ten Brugge,
9			* rewritten by Lauri Pesonen 1999-2000,
10			* accomodated to GCC's Extended Asm syntax by Gwenole Beauchesne 2000.
11			*
12			* This program is free software; you can redistribute it and/or modify
13			* it under the terms of the GNU General Public License as published by
14			* the Free Software Foundation; either version 2 of the License, or
15			* (at your option) any later version.
16			*
17			* This program is distributed in the hope that it will be useful,
18			* but WITHOUT ANY WARRANTY; without even the implied warranty of
19			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20			* GNU General Public License for more details.
21			*
22			* You should have received a copy of the GNU General Public License
23			* along with this program; if not, write to the Free Software
24			* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25			*/
26
27			/* gb-- defined in newcpu.h
28			// is_integral: true == 68040, false == 68881
29			void fpu_set_integral_fpu( bool is_integral );
30
31			// MUST be called before the cpu starts up.
32			void fpu_init( void );
33
34			// Finalize.
35			void fpu_exit( void );
36
37			// Soft reset.
38			void fpu_reset( void );
39			*/
40
41			// The same as original. "ftrapcc_opp" is bound to change soon.
42			/* gb-- defined in newcpu.h
43			void REGPARAM2 fpp_opp (uae_u32, uae_u16);
44			void REGPARAM2 fdbcc_opp (uae_u32, uae_u16);
45			void REGPARAM2 fscc_opp (uae_u32, uae_u16);
46			void REGPARAM2 ftrapcc_opp (uae_u32,uaecptr);
47			void REGPARAM2 fbcc_opp (uae_u32, uaecptr, uae_u32);
48			void REGPARAM2 fsave_opp (uae_u32);
49			void REGPARAM2 frestore_opp (uae_u32);
50			*/
51
52			/* ---------------------------- Motorola ---------------------------- */
53
54			// Exception byte
55			#define BSUN 0x00008000
56			#define SNAN 0x00004000
57			#define OPERR 0x00002000
58			#define OVFL 0x00001000
59			#define UNFL 0x00000800
60			#define DZ 0x00000400
61			#define INEX2 0x00000200
62			#define INEX1 0x00000100
63
64			// Accrued exception byte
65			#define ACCR_IOP 0x80
66			#define ACCR_OVFL 0x40
67			#define ACCR_UNFL 0x20
68			#define ACCR_DZ 0x10
69			#define ACCR_INEX 0x08
70
71			// fpcr rounding modes
72			#define ROUND_CONTROL_MASK 0x30
73			#define ROUND_TO_NEAREST 0
74			#define ROUND_TO_ZERO 0x10
75			#define ROUND_TO_NEGATIVE_INFINITY 0x20
76			#define ROUND_TO_POSITIVE_INFINITY 0x30
77
78			// fpcr precision control
79			#define PRECISION_CONTROL_MASK 0xC0
80			#define PRECISION_CONTROL_EXTENDED 0
81			#define PRECISION_CONTROL_DOUBLE 0x80
82			#define PRECISION_CONTROL_SINGLE 0x40
83			#define PRECISION_CONTROL_UNDEFINED 0xC0
84
85
86			/* ---------------------------- Intel ---------------------------- */
87
88			#define CW_RESET 0x0040 // initial CW value after RESET
89			#define CW_FINIT 0x037F // initial CW value after FINIT
90			#define SW_RESET 0x0000 // initial SW value after RESET
91			#define SW_FINIT 0x0000 // initial SW value after FINIT
92			#define TW_RESET 0x5555 // initial TW value after RESET
93			#define TW_FINIT 0x0FFF // initial TW value after FINIT
94
95			#define CW_X 0x1000 // infinity control
96			#define CW_RC_ZERO 0x0C00 // rounding control toward zero
97			#define CW_RC_UP 0x0800 // rounding control toward +
98			#define CW_RC_DOWN 0x0400 // rounding control toward -
99			#define CW_RC_NEAR 0x0000 // rounding control toward even
100			#define CW_PC_EXTENDED 0x0300 // precision control 64bit
101			#define CW_PC_DOUBLE 0x0200 // precision control 53bit
102			#define CW_PC_RESERVED 0x0100 // precision control reserved
103			#define CW_PC_SINGLE 0x0000 // precision control 24bit
104			#define CW_PM 0x0020 // precision exception mask
105			#define CW_UM 0x0010 // underflow exception mask
106			#define CW_OM 0x0008 // overflow exception mask
107			#define CW_ZM 0x0004 // zero divide exception mask
108			#define CW_DM 0x0002 // denormalized operand exception mask
109			#define CW_IM 0x0001 // invalid operation exception mask
110
111			#define SW_B 0x8000 // busy flag
112			#define SW_C3 0x4000 // condition code flag 3
113			#define SW_TOP_7 0x3800 // top of stack = ST(7)
114			#define SW_TOP_6 0x3000 // top of stack = ST(6)
115			#define SW_TOP_5 0x2800 // top of stack = ST(5)
116			#define SW_TOP_4 0x2000 // top of stack = ST(4)
117			#define SW_TOP_3 0x1800 // top of stack = ST(3)
118			#define SW_TOP_2 0x1000 // top of stack = ST(2)
119			#define SW_TOP_1 0x0800 // top of stack = ST(1)
120			#define SW_TOP_0 0x0000 // top of stack = ST(0)
121			#define SW_C2 0x0400 // condition code flag 2
122			#define SW_C1 0x0200 // condition code flag 1
123			#define SW_C0 0x0100 // condition code flag 0
124			#define SW_ES 0x0080 // error summary status flag
125			#define SW_SF 0x0040 // stack fault flag
126			#define SW_PE 0x0020 // precision exception flag
127			#define SW_UE 0x0010 // underflow exception flag
128			#define SW_OE 0x0008 // overflow exception flag
129			#define SW_ZE 0x0004 // zero divide exception flag
130			#define SW_DE 0x0002 // denormalized operand exception flag
131			#define SW_IE 0x0001 // invalid operation exception flag
132
133			#define X86_ROUND_CONTROL_MASK 0x0C00
134			#define X86_PRECISION_CONTROL_MASK 0x0300