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gbeauche |
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/* |
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* fpu/exceptions.cpp - system-dependant FPU exceptions management |
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* |
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gbeauche |
1.3 |
* Basilisk II (C) 1997-2005 Christian Bauer |
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gbeauche |
1.1 |
* |
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* MC68881/68040 fpu emulation |
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* |
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* Original UAE FPU, copyright 1996 Herman ten Brugge |
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* Rewrite for x86, copyright 1999-2000 Lauri Pesonen |
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* New framework, copyright 2000 Gwenole Beauchesne |
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* Adapted for JIT compilation (c) Bernd Meyer, 2000 |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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*/ |
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#undef PRIVATE |
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#define PRIVATE /**/ |
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#undef PUBLIC |
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#define PUBLIC /**/ |
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#undef FFPU |
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#define FFPU /**/ |
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#undef FPU |
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#define FPU fpu. |
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/* -------------------------------------------------------------------------- */ |
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/* --- Native X86 exceptions --- */ |
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/* -------------------------------------------------------------------------- */ |
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#ifdef FPU_USE_X86_EXCEPTIONS |
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void FFPU fpu_init_native_exceptions(void) |
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{ |
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// Mapping for "sw" -> fpsr exception byte |
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for (uae_u32 i = 0; i < 0x80; i++) { |
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exception_host2mac[i] = 0; |
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if(i & SW_FAKE_BSUN) { |
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exception_host2mac[i] |= FPSR_EXCEPTION_BSUN; |
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} |
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// precision exception |
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if(i & SW_PE) { |
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exception_host2mac[i] |= FPSR_EXCEPTION_INEX2; |
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} |
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// underflow exception |
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if(i & SW_UE) { |
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exception_host2mac[i] |= FPSR_EXCEPTION_UNFL; |
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} |
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// overflow exception |
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if(i & SW_OE) { |
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exception_host2mac[i] |= FPSR_EXCEPTION_OVFL; |
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} |
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// zero divide exception |
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if(i & SW_ZE) { |
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exception_host2mac[i] |= FPSR_EXCEPTION_DZ; |
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} |
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// denormalized operand exception. |
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// wrong, but should not get here, normalization is done in elsewhere |
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if(i & SW_DE) { |
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exception_host2mac[i] |= FPSR_EXCEPTION_SNAN; |
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} |
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// invalid operation exception |
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if(i & SW_IE) { |
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exception_host2mac[i] |= FPSR_EXCEPTION_OPERR; |
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} |
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} |
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// Mapping for fpsr exception byte -> "sw" |
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for (uae_u32 i = 0; i < 0x100; i++) { |
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uae_u32 fpsr = (i << 8); |
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exception_mac2host[i] = 0; |
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// BSUN; make sure that you don't generate FPU stack faults. |
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if(fpsr & FPSR_EXCEPTION_BSUN) { |
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exception_mac2host[i] |= SW_FAKE_BSUN; |
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} |
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// precision exception |
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if(fpsr & FPSR_EXCEPTION_INEX2) { |
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exception_mac2host[i] |= SW_PE; |
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} |
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// underflow exception |
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if(fpsr & FPSR_EXCEPTION_UNFL) { |
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exception_mac2host[i] |= SW_UE; |
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} |
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// overflow exception |
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if(fpsr & FPSR_EXCEPTION_OVFL) { |
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exception_mac2host[i] |= SW_OE; |
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} |
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// zero divide exception |
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if(fpsr & FPSR_EXCEPTION_DZ) { |
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exception_mac2host[i] |= SW_ZE; |
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} |
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// denormalized operand exception |
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if(fpsr & FPSR_EXCEPTION_SNAN) { |
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exception_mac2host[i] |= SW_DE; //Wrong |
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} |
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// invalid operation exception |
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if(fpsr & FPSR_EXCEPTION_OPERR) { |
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exception_mac2host[i] |= SW_IE; |
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} |
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} |
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} |
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#endif |
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#ifdef FPU_USE_X86_ACCRUED_EXCEPTIONS |
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void FFPU fpu_init_native_accrued_exceptions(void) |
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{ |
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/* |
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68881/68040 accrued exceptions accumulate as follows: |
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Accrued.IOP |= (Exception.SNAN | Exception.OPERR) |
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Accrued.OVFL |= (Exception.OVFL) |
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Accrued.UNFL |= (Exception.UNFL | Exception.INEX2) |
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Accrued.DZ |= (Exception.DZ) |
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Accrued.INEX |= (Exception.INEX1 | Exception.INEX2 | Exception.OVFL) |
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*/ |
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// Mapping for "fpsr.accrued_exception" -> fpsr accrued exception byte |
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for (uae_u32 i = 0; i < 0x40; i++ ) { |
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accrued_exception_host2mac[i] = 0; |
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// precision exception |
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if(i & SW_PE) { |
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accrued_exception_host2mac[i] |= FPSR_ACCR_INEX; |
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} |
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// underflow exception |
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if(i & SW_UE) { |
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accrued_exception_host2mac[i] |= FPSR_ACCR_UNFL; |
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} |
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// overflow exception |
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if(i & SW_OE) { |
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accrued_exception_host2mac[i] |= FPSR_ACCR_OVFL; |
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} |
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// zero divide exception |
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if(i & SW_ZE) { |
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accrued_exception_host2mac[i] |= FPSR_ACCR_DZ; |
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} |
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// denormalized operand exception |
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if(i & SW_DE) { |
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accrued_exception_host2mac[i] |= FPSR_ACCR_IOP; //?????? |
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} |
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// invalid operation exception |
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if(i & SW_IE) { |
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accrued_exception_host2mac[i] |= FPSR_ACCR_IOP; |
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} |
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} |
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// Mapping for fpsr accrued exception byte -> "fpsr.accrued_exception" |
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for (uae_u32 i = 0; i < 0x20; i++) { |
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int fpsr = (i << 3); |
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accrued_exception_mac2host[i] = 0; |
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// precision exception |
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if(fpsr & FPSR_ACCR_INEX) { |
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accrued_exception_mac2host[i] |= SW_PE; |
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} |
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// underflow exception |
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if(fpsr & FPSR_ACCR_UNFL) { |
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accrued_exception_mac2host[i] |= SW_UE; |
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} |
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// overflow exception |
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if(fpsr & FPSR_ACCR_OVFL) { |
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accrued_exception_mac2host[i] |= SW_OE; |
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} |
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// zero divide exception |
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if(fpsr & FPSR_ACCR_DZ) { |
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accrued_exception_mac2host[i] |= SW_ZE; |
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} |
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// What about SW_DE; //?????? |
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// invalid operation exception |
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if(fpsr & FPSR_ACCR_IOP) { |
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accrued_exception_mac2host[i] |= SW_IE; |
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} |
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} |
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} |
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#endif |
