Revision 1.12 - (view) (annotate) - [select for diffs]
2007-06-29T16:53:04Z (17 years, 4 months ago) by gbeauche
Branch: MAIN
CVS Tags: HEAD
Changes since 1.11: +101 -95 lines
Diff to previous 1.11 , to selected 1.2

Fix LSL & LSR instructions so that they preserve the X flags when the
shift count is 0. Likewise for ASR + another improvement to avoid shifting
by halves (propagated bit is reset to original's when necessary).

More human readable instruction names (from e-uae).

Revision 1.10 - (view) (annotate) - [select for diffs]
2005-04-24T23:00:08Z (19 years, 6 months ago) by gbeauche
Branch: MAIN
CVS Tags: nigel-build-17, nigel-build-19
Changes since 1.9: +11 -11 lines
Diff to previous 1.9 , to selected 1.2

Fix build with gcc4 on x86-64: ignore errors when casting pointers to int
from regs & fpu members + code cache. This is possible because data is
allocated in 32-bit space and we force allocation of translation cache to
those bounds too.

close opened files and make sure to flush stdout on exit, this used to
cause weird results on windows otherwise

Revision 1.8 - (view) (annotate) - [select for diffs]
2005-01-30T21:42:16Z (19 years, 9 months ago) by gbeauche
Branch: MAIN
Changes since 1.7: +2 -2 lines
Diff to previous 1.7 , to selected 1.2

Happy New Year!

Merge BSF simulation on P4 from Amithlon. Use 33-bit memory addressing model.

Revision 1.6 - (view) (annotate) - [select for diffs]
2004-01-12T15:29:30Z (20 years, 10 months ago) by cebix
Branch: MAIN
CVS Tags: nigel-build-15, nigel-build-16
Changes since 1.5: +2 -2 lines
Diff to previous 1.5 , to selected 1.2

Happy New Year! :)

Implement a generic setzflg_l() for P4, thus permitting to re-enable
translation of ADDX/SUBX/BCLR/BTST/BSET/BCHG instructions. i.e. make
it faster. ;-)

Revision 1.4 - (view) (annotate) - [select for diffs]
2003-03-13T15:57:01Z (21 years, 8 months ago) by gbeauche
Branch: MAIN
Changes since 1.3: +15 -9 lines
Diff to previous 1.3 , to selected 1.2

Workaround change in flags handling for BSF instruction on Pentium 4.
i.e. currently disable translation of ADDX/SUBX/B<CHG,CLR,SET,TST> instructions
in that case. That is to say, better (much?) slower than inaccurate. :-(

JIT add copyright notices just to notify people that's real derivative
work from GPL code (UAE-JIT). Additions and improvements are from B2
developers.

Revision 1.2 - (view) (annotate) - [selected]
2002-10-03T14:59:35Z (22 years, 1 month ago) by gbeauche
Branch: MAIN
Changes since 1.1: +0 -2 lines
Diff to previous 1.1

Do translate BSR.L, we don't have any issue with that even if we are
doing block inlining since we have a complete chain of information about
the blocks to checksum.

Import JIT compiler