Fix LSL & LSR instructions so that they preserve the X flags when the shift count is 0. Likewise for ASR + another improvement to avoid shifting by halves (propagated bit is reset to original's when necessary).
More human readable instruction names (from e-uae).
Fix build with gcc4 on x86-64: ignore errors when casting pointers to int from regs & fpu members + code cache. This is possible because data is allocated in 32-bit space and we force allocation of translation cache to those bounds too.
close opened files and make sure to flush stdout on exit, this used to cause weird results on windows otherwise
Happy New Year!
Merge BSF simulation on P4 from Amithlon. Use 33-bit memory addressing model.
Happy New Year! :)
Implement a generic setzflg_l() for P4, thus permitting to re-enable translation of ADDX/SUBX/BCLR/BTST/BSET/BCHG instructions. i.e. make it faster. ;-)
Workaround change in flags handling for BSF instruction on Pentium 4. i.e. currently disable translation of ADDX/SUBX/B<CHG,CLR,SET,TST> instructions in that case. That is to say, better (much?) slower than inaccurate. :-(
JIT add copyright notices just to notify people that's real derivative work from GPL code (UAE-JIT). Additions and improvements are from B2 developers.
Do translate BSR.L, we don't have any issue with that even if we are doing block inlining since we have a complete chain of information about the blocks to checksum.
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