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root/cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.73 by gbeauche, 2008-01-06T16:10:30Z vs.
Revision 1.81 by gbeauche, 2008-01-19T22:25:27Z

#	Line 49 | Line 49 | using std::list;
49		#define RETSIGTYPE void
50		#endif
51
52	+	// Size of an unsigned integer large enough to hold all bits of a pointer
53	+	// NOTE: this can be different than SIGSEGV_REGISTER_TYPE. In
54	+	// particular, on ILP32 systems with a 64-bit kernel (HP-UX/ia64?)
55	+	#ifdef HAVE_WIN32_VM
56	+	// Windows is either ILP32 or LLP64
57	+	typedef UINT_PTR sigsegv_uintptr_t;
58	+	#else
59	+	// Other systems are sane enough to follow ILP32 or LP64 models
60	+	typedef unsigned long sigsegv_uintptr_t;
61	+	#endif
62	+
63		// Type of the system signal handler
64		typedef RETSIGTYPE (*signal_handler)(int);
65
#	Line 264 | Line 275 | static void powerpc_decode_instruction(i
275		#include <sys/regset.h>
276		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
277		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[EIP]
278	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
278	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
279		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
280		#endif
281		#endif
282		#if defined(__FreeBSD__) || defined(__OpenBSD__)
283		#if (defined(i386) || defined(__i386__))
284		#define SIGSEGV_FAULT_INSTRUCTION               (((struct sigcontext *)scp)->sc_eip)
285	<	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&(((struct sigcontext *)scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
285	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&(((struct sigcontext *)scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
286		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
287		#endif
288		#endif
#	Line 280 | Line 291 | static void powerpc_decode_instruction(i
291		#include <sys/ucontext.h>
292		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.__gregs)
293		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[_REG_EIP]
294	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
294	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
295		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
296		#endif
297		#if (defined(powerpc) || defined(__powerpc__))
#	Line 296 | Line 307 | static void powerpc_decode_instruction(i
307		#include <sys/ucontext.h>
308		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
309		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[14] /* should use REG_EIP instead */
310	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
310	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
311		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
312		#endif
313		#if (defined(x86_64) || defined(__x86_64__))
314		#include <sys/ucontext.h>
315		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
316		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[16] /* should use REG_RIP instead */
317	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
317	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
318		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
319		#endif
320		#if (defined(ia64) || defined(__ia64__))
321	<	#define SIGSEGV_FAULT_INSTRUCTION               (((struct sigcontext *)scp)->sc_ip & ~0x3ULL) /* slot number is in bits 0 and 1 */
321	>	#define SIGSEGV_CONTEXT_REGS                    ((struct sigcontext *)scp)
322	>	#define SIGSEGV_FAULT_INSTRUCTION               (SIGSEGV_CONTEXT_REGS->sc_ip & ~0x3ULL) /* slot number is in bits 0 and 1 */
323	>	#define SIGSEGV_REGISTER_FILE                   SIGSEGV_CONTEXT_REGS
324	>	#define SIGSEGV_SKIP_INSTRUCTION                ia64_skip_instruction
325		#endif
326		#if (defined(powerpc) || defined(__powerpc__))
327		#include <sys/ucontext.h>
#	Line 348 | Line 362 | static void powerpc_decode_instruction(i
362		#define SIGSEGV_FAULT_HANDLER_ARGS              &scs
363		#define SIGSEGV_FAULT_ADDRESS                   scp->cr2
364		#define SIGSEGV_FAULT_INSTRUCTION               scp->eip
365	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)scp
365	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)scp
366		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
367		#endif
368		#if (defined(sparc) || defined(__sparc__))
#	Line 469 | Line 483 | static sigsegv_address_t get_fault_addre
483		#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp, addr
484		#define SIGSEGV_FAULT_ADDRESS                   addr
485		#define SIGSEGV_FAULT_INSTRUCTION               scp->sc_eip
486	<	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&scp->sc_edi)
486	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&scp->sc_edi)
487		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
488		#endif
489		#if (defined(alpha) || defined(__alpha__))
#	Line 532 | Line 546 | static sigsegv_address_t get_fault_addre
546		#include <windows.h>
547		#include <winerror.h>
548
549	+	#if defined(_M_IX86)
550		#define SIGSEGV_FAULT_HANDLER_ARGLIST   EXCEPTION_POINTERS *ExceptionInfo
551		#define SIGSEGV_FAULT_HANDLER_ARGS              ExceptionInfo
552		#define SIGSEGV_FAULT_ADDRESS                   ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
553		#define SIGSEGV_CONTEXT_REGS                    ExceptionInfo->ContextRecord
554		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS->Eip
555	<	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&SIGSEGV_CONTEXT_REGS->Edi)
555	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Edi)
556		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
557		#endif
558	+	#if defined(_M_X64)
559	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST   EXCEPTION_POINTERS *ExceptionInfo
560	+	#define SIGSEGV_FAULT_HANDLER_ARGS              ExceptionInfo
561	+	#define SIGSEGV_FAULT_ADDRESS                   ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
562	+	#define SIGSEGV_CONTEXT_REGS                    ExceptionInfo->ContextRecord
563	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS->Rip
564	+	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Rax)
565	+	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
566	+	#endif
567	+	#endif
568
569		#if HAVE_MACH_EXCEPTIONS
570
#	Line 602 | Line 627 | if (ret != KERN_SUCCESS) { \
627		}
628
629		#ifdef __ppc__
630	+	#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE
631	+	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
632	+	#endif
633		#define SIGSEGV_EXCEPTION_STATE_TYPE    ppc_exception_state_t
634		#define SIGSEGV_EXCEPTION_STATE_FLAVOR  PPC_EXCEPTION_STATE
635		#define SIGSEGV_EXCEPTION_STATE_COUNT   PPC_EXCEPTION_STATE_COUNT
636	<	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.dar
636	>	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(dar)
637		#define SIGSEGV_THREAD_STATE_TYPE               ppc_thread_state_t
638		#define SIGSEGV_THREAD_STATE_FLAVOR             PPC_THREAD_STATE
639		#define SIGSEGV_THREAD_STATE_COUNT              PPC_THREAD_STATE_COUNT
640	<	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.srr0
640	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(srr0)
641		#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
642	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIP->thr_state.srr0, (unsigned long *)&SIP->thr_state.r0
642	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(r0)
643		#endif
644		#ifdef __ppc64__
645	+	#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE64
646	+	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
647	+	#endif
648		#define SIGSEGV_EXCEPTION_STATE_TYPE    ppc_exception_state64_t
649		#define SIGSEGV_EXCEPTION_STATE_FLAVOR  PPC_EXCEPTION_STATE64
650		#define SIGSEGV_EXCEPTION_STATE_COUNT   PPC_EXCEPTION_STATE64_COUNT
651	<	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.dar
651	>	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(dar)
652		#define SIGSEGV_THREAD_STATE_TYPE               ppc_thread_state64_t
653		#define SIGSEGV_THREAD_STATE_FLAVOR             PPC_THREAD_STATE64
654		#define SIGSEGV_THREAD_STATE_COUNT              PPC_THREAD_STATE64_COUNT
655	<	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.srr0
655	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(srr0)
656		#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
657	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIP->thr_state.srr0, (unsigned long *)&SIP->thr_state.r0
657	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(r0)
658		#endif
659		#ifdef __i386__
660	<	#define SIGSEGV_EXCEPTION_STATE_TYPE    struct i386_exception_state
660	>	#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE32
661	>	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
662	>	#endif
663	>	#define SIGSEGV_EXCEPTION_STATE_TYPE    i386_exception_state_t
664		#define SIGSEGV_EXCEPTION_STATE_FLAVOR  i386_EXCEPTION_STATE
665		#define SIGSEGV_EXCEPTION_STATE_COUNT   i386_EXCEPTION_STATE_COUNT
666	<	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.faultvaddr
667	<	#define SIGSEGV_THREAD_STATE_TYPE               struct i386_thread_state
666	>	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(faultvaddr)
667	>	#define SIGSEGV_THREAD_STATE_TYPE               i386_thread_state_t
668		#define SIGSEGV_THREAD_STATE_FLAVOR             i386_THREAD_STATE
669		#define SIGSEGV_THREAD_STATE_COUNT              i386_THREAD_STATE_COUNT
670	<	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.eip
670	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(eip)
671		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
672	<	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&SIP->thr_state.eax) /* EAX is the first GPR we consider */
672	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIP->thr_state.MACH_FIELD_NAME(eax)) /* EAX is the first GPR we consider */
673		#endif
674		#ifdef __x86_64__
675	<	#define SIGSEGV_EXCEPTION_STATE_TYPE    struct x86_exception_state64
675	>	#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE64
676	>	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
677	>	#endif
678	>	#define SIGSEGV_EXCEPTION_STATE_TYPE    x86_exception_state64_t
679		#define SIGSEGV_EXCEPTION_STATE_FLAVOR  x86_EXCEPTION_STATE64
680		#define SIGSEGV_EXCEPTION_STATE_COUNT   x86_EXCEPTION_STATE64_COUNT
681	<	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.faultvaddr
682	<	#define SIGSEGV_THREAD_STATE_TYPE               struct x86_thread_state64
681	>	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(faultvaddr)
682	>	#define SIGSEGV_THREAD_STATE_TYPE               x86_thread_state64_t
683		#define SIGSEGV_THREAD_STATE_FLAVOR             x86_THREAD_STATE64
684		#define SIGSEGV_THREAD_STATE_COUNT              x86_THREAD_STATE64_COUNT
685	<	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.rip
685	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(rip)
686		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
687	<	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&SIP->thr_state.rax) /* RAX is the first GPR we consider */
687	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIP->thr_state.MACH_FIELD_NAME(rax)) /* RAX is the first GPR we consider */
688		#endif
689		#define SIGSEGV_FAULT_ADDRESS_FAST              code[1]
690		#define SIGSEGV_FAULT_INSTRUCTION_FAST  SIGSEGV_INVALID_ADDRESS
691		#define SIGSEGV_FAULT_HANDLER_ARGLIST   mach_port_t thread, exception_data_t code
692		#define SIGSEGV_FAULT_HANDLER_ARGS              thread, code
693
694	+	#ifndef MACH_FIELD_NAME
695	+	#define MACH_FIELD_NAME(X) X
696	+	#endif
697	+
698		// Since there can only be one exception thread running at any time
699		// this is not a problem.
700		#define MSG_SIZE 512
#	Line 705 | Line 746 | handleExceptions(void *priv)
746		*  Instruction skipping
747		*/
748
749	+	#ifndef SIGSEGV_REGISTER_TYPE
750	+	#define SIGSEGV_REGISTER_TYPE sigsegv_uintptr_t
751	+	#endif
752	+
753		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
754		// Decode and skip X86 instruction
755	<	#if (defined(i386) || defined(__i386__)) || defined(__x86_64__)
755	>	#if (defined(i386) || defined(__i386__)) || (defined(__x86_64__) || defined(_M_X64))
756		#if defined(__linux__)
757		enum {
758		#if (defined(i386) || defined(__i386__))
#	Line 858 | Line 903 | enum {
903		#endif
904		#if defined(_WIN32)
905		enum {
906	<	#if (defined(i386) || defined(__i386__))
906	>	#if defined(_M_IX86)
907		X86_REG_EIP = 7,
908		X86_REG_EAX = 5,
909		X86_REG_ECX = 4,
#	Line 869 | Line 914 | enum {
914		X86_REG_ESI = 1,
915		X86_REG_EDI = 0
916		#endif
917	+	#if defined(_M_X64)
918	+	X86_REG_EAX = 0,
919	+	X86_REG_ECX = 1,
920	+	X86_REG_EDX = 2,
921	+	X86_REG_EBX = 3,
922	+	X86_REG_ESP = 4,
923	+	X86_REG_EBP = 5,
924	+	X86_REG_ESI = 6,
925	+	X86_REG_EDI = 7,
926	+	X86_REG_R8  = 8,
927	+	X86_REG_R9  = 9,
928	+	X86_REG_R10 = 10,
929	+	X86_REG_R11 = 11,
930	+	X86_REG_R12 = 12,
931	+	X86_REG_R13 = 13,
932	+	X86_REG_R14 = 14,
933	+	X86_REG_R15 = 15,
934	+	X86_REG_EIP = 16
935	+	#endif
936		};
937		#endif
938		// FIXME: this is partly redundant with the instruction decoding phase
#	Line 905 | Line 969 | static inline int ix86_step_over_modrm(u
969		return offset;
970		}
971
972	<	static bool ix86_skip_instruction(unsigned long * regs)
972	>	static bool ix86_skip_instruction(SIGSEGV_REGISTER_TYPE * regs)
973		{
974		unsigned char * eip = (unsigned char *)regs[X86_REG_EIP];
975
#	Line 941 | Line 1005 | static bool ix86_skip_instruction(unsign
1005		}
1006
1007		// REX prefix
1008	<	#if defined(__x86_64__)
1008	>	#if defined(__x86_64__) || defined(_M_X64)
1009		struct rex_t {
1010		unsigned char W;
1011		unsigned char R;
#	Line 993 | Line 1057 | static bool ix86_skip_instruction(unsign
1057		goto do_transfer_load;
1058		}
1059		break;
1060	<	#if defined(__x86_64__)
1060	>	#if defined(__x86_64__) || defined(_M_X64)
1061		case 0x63: // MOVSXD r64, r/m32
1062		if (has_rex && rex.W) {
1063		transfer_size = SIZE_LONG;
#	Line 1064 | Line 1128 | static bool ix86_skip_instruction(unsign
1128		return false;
1129		}
1130
1131	<	#if defined(__x86_64__)
1131	>	#if defined(__x86_64__) || defined(_M_X64)
1132		if (rex.R)
1133		reg += 8;
1134		#endif
#	Line 1073 | Line 1137 | static bool ix86_skip_instruction(unsign
1137		static const int x86_reg_map[] = {
1138		X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, X86_REG_EBX,
1139		X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI,
1140	<	#if defined(__x86_64__)
1140	>	#if defined(__x86_64__) || defined(_M_X64)
1141		X86_REG_R8,  X86_REG_R9,  X86_REG_R10, X86_REG_R11,
1142		X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15,
1143		#endif
#	Line 1160 | Line 1224 | static bool ix86_skip_instruction(unsign
1224		}
1225		#endif
1226
1227	+	// Decode and skip IA-64 instruction
1228	+	#if defined(__ia64__)
1229	+	typedef uint64_t ia64_bundle_t[2];
1230	+	#if defined(__linux__)
1231	+	// We can directly patch the slot number
1232	+	#define IA64_CAN_PATCH_IP_SLOT  1
1233	+	// Helper macros to access the machine context
1234	+	#define IA64_CONTEXT_TYPE               struct sigcontext *
1235	+	#define IA64_CONTEXT                    scp
1236	+	#define IA64_GET_IP()                   (IA64_CONTEXT->sc_ip)
1237	+	#define IA64_SET_IP(V)                  (IA64_CONTEXT->sc_ip = (V))
1238	+	#define IA64_GET_PR(P)                  ((IA64_CONTEXT->sc_pr >> (P)) & 1)
1239	+	#define IA64_GET_NAT(I)                 ((IA64_CONTEXT->sc_nat >> (I)) & 1)
1240	+	#define IA64_GET_GR(R)                  (IA64_CONTEXT->sc_gr[(R)])
1241	+	#define _IA64_SET_GR(R,V)               (IA64_CONTEXT->sc_gr[(R)] = (V))
1242	+	#define _IA64_SET_NAT(I,V)              (IA64_CONTEXT->sc_nat = (IA64_CONTEXT->sc_nat & ~(1ull << (I))) | (((uint64_t)!!(V)) << (I)))
1243	+	#define IA64_SET_GR(R,V,N)              (_IA64_SET_GR(R,V), _IA64_SET_NAT(R,N))
1244	+
1245	+	// Load bundle (in little-endian)
1246	+	static inline void ia64_load_bundle(ia64_bundle_t bundle, uint64_t raw_ip)
1247	+	{
1248	+	uint64_t *ip = (uint64_t *)(raw_ip & ~3ull);
1249	+	bundle[0] = ip[0];
1250	+	bundle[1] = ip[1];
1251	+	}
1252	+	#endif
1253	+
1254	+	// Instruction operations
1255	+	enum {
1256	+	IA64_INST_UNKNOWN = 0,
1257	+	IA64_INST_LD1,                          // ld1 op0=[op1]
1258	+	IA64_INST_LD1_UPDATE,           // ld1 op0=[op1],op2
1259	+	IA64_INST_LD2,                          // ld2 op0=[op1]
1260	+	IA64_INST_LD2_UPDATE,           // ld2 op0=[op1],op2
1261	+	IA64_INST_LD4,                          // ld4 op0=[op1]
1262	+	IA64_INST_LD4_UPDATE,           // ld4 op0=[op1],op2
1263	+	IA64_INST_LD8,                          // ld8 op0=[op1]
1264	+	IA64_INST_LD8_UPDATE,           // ld8 op0=[op1],op2
1265	+	IA64_INST_ST1,                          // st1 [op0]=op1
1266	+	IA64_INST_ST1_UPDATE,           // st1 [op0]=op1,op2
1267	+	IA64_INST_ST2,                          // st2 [op0]=op1
1268	+	IA64_INST_ST2_UPDATE,           // st2 [op0]=op1,op2
1269	+	IA64_INST_ST4,                          // st4 [op0]=op1
1270	+	IA64_INST_ST4_UPDATE,           // st4 [op0]=op1,op2
1271	+	IA64_INST_ST8,                          // st8 [op0]=op1
1272	+	IA64_INST_ST8_UPDATE,           // st8 [op0]=op1,op2
1273	+	IA64_INST_ADD,                          // add op0=op1,op2,op3
1274	+	IA64_INST_SUB,                          // sub op0=op1,op2,op3
1275	+	IA64_INST_SHLADD,                       // shladd op0=op1,op3,op2
1276	+	IA64_INST_AND,                          // and op0=op1,op2
1277	+	IA64_INST_ANDCM,                        // andcm op0=op1,op2
1278	+	IA64_INST_OR,                           // or op0=op1,op2
1279	+	IA64_INST_XOR,                          // xor op0=op1,op2
1280	+	IA64_INST_SXT1,                         // sxt1 op0=op1
1281	+	IA64_INST_SXT2,                         // sxt2 op0=op1
1282	+	IA64_INST_SXT4,                         // sxt4 op0=op1
1283	+	IA64_INST_ZXT1,                         // zxt1 op0=op1
1284	+	IA64_INST_ZXT2,                         // zxt2 op0=op1
1285	+	IA64_INST_ZXT4,                         // zxt4 op0=op1
1286	+	IA64_INST_NOP                           // nop op0
1287	+	};
1288	+
1289	+	const int IA64_N_OPERANDS = 4;
1290	+
1291	+	// Decoded operand type
1292	+	struct ia64_operand_t {
1293	+	uint8_t commit;                         // commit result of operation to register file?
1294	+	uint8_t valid;                          // XXX: not really used, can be removed (debug)
1295	+	int8_t index;                           // index of GPR, or -1 if immediate value
1296	+	uint8_t nat;                            // NaT state before operation
1297	+	uint64_t value;                         // register contents or immediate value
1298	+	};
1299	+
1300	+	// Decoded instruction type
1301	+	struct ia64_instruction_t {
1302	+	uint8_t mnemo;                          // operation to perform
1303	+	uint8_t pred;                           // predicate register to check
1304	+	uint8_t no_memory;                      // used to emulated main fault instruction
1305	+	uint64_t inst;                          // the raw instruction bits (41-bit wide)
1306	+	ia64_operand_t operands[IA64_N_OPERANDS];
1307	+	};
1308	+
1309	+	// Get immediate sign-bit
1310	+	static inline int ia64_inst_get_sbit(uint64_t inst)
1311	+	{
1312	+	return (inst >> 36) & 1;
1313	+	}
1314	+
1315	+	// Get 8-bit immediate value (A3, A8, I27, M30)
1316	+	static inline uint64_t ia64_inst_get_imm8(uint64_t inst)
1317	+	{
1318	+	uint64_t value = (inst >> 13) & 0x7full;
1319	+	if (ia64_inst_get_sbit(inst))
1320	+	value |= ~0x7full;
1321	+	return value;
1322	+	}
1323	+
1324	+	// Get 9-bit immediate value (M3)
1325	+	static inline uint64_t ia64_inst_get_imm9b(uint64_t inst)
1326	+	{
1327	+	uint64_t value = (((inst >> 27) & 1) << 7) | ((inst >> 13) & 0x7f);
1328	+	if (ia64_inst_get_sbit(inst))
1329	+	value |= ~0xffull;
1330	+	return value;
1331	+	}
1332	+
1333	+	// Get 9-bit immediate value (M5)
1334	+	static inline uint64_t ia64_inst_get_imm9a(uint64_t inst)
1335	+	{
1336	+	uint64_t value = (((inst >> 27) & 1) << 7) | ((inst >> 6) & 0x7f);
1337	+	if (ia64_inst_get_sbit(inst))
1338	+	value |= ~0xffull;
1339	+	return value;
1340	+	}
1341	+
1342	+	// Get 14-bit immediate value (A4)
1343	+	static inline uint64_t ia64_inst_get_imm14(uint64_t inst)
1344	+	{
1345	+	uint64_t value = (((inst >> 27) & 0x3f) << 7) | (inst & 0x7f);
1346	+	if (ia64_inst_get_sbit(inst))
1347	+	value |= ~0x1ffull;
1348	+	return value;
1349	+	}
1350	+
1351	+	// Get 22-bit immediate value (A5)
1352	+	static inline uint64_t ia64_inst_get_imm22(uint64_t inst)
1353	+	{
1354	+	uint64_t value = ((((inst >> 22) & 0x1f) << 16) |
1355	+	(((inst >> 27) & 0x1ff) << 7) |
1356	+	(inst & 0x7f));
1357	+	if (ia64_inst_get_sbit(inst))
1358	+	value |= ~0x1fffffull;
1359	+	return value;
1360	+	}
1361	+
1362	+	// Get 21-bit immediate value (I19)
1363	+	static inline uint64_t ia64_inst_get_imm21(uint64_t inst)
1364	+	{
1365	+	return (((inst >> 36) & 1) << 20) | ((inst >> 6) & 0xfffff);
1366	+	}
1367	+
1368	+	// Get 2-bit count value (A2)
1369	+	static inline int ia64_inst_get_count2(uint64_t inst)
1370	+	{
1371	+	return (inst >> 27) & 0x3;
1372	+	}
1373	+
1374	+	// Get bundle template
1375	+	static inline unsigned int ia64_get_template(uint64_t ip)
1376	+	{
1377	+	ia64_bundle_t bundle;
1378	+	ia64_load_bundle(bundle, ip);
1379	+	return bundle[0] & 0x1f;
1380	+	}
1381	+
1382	+	// Get specified instruction in bundle
1383	+	static uint64_t ia64_get_instruction(uint64_t ip, int slot)
1384	+	{
1385	+	uint64_t inst;
1386	+	ia64_bundle_t bundle;
1387	+	ia64_load_bundle(bundle, ip);
1388	+	#if DEBUG
1389	+	printf("Bundle: %016llx%016llx\n", bundle[1], bundle[0]);
1390	+	#endif
1391	+
1392	+	switch (slot) {
1393	+	case 0:
1394	+	inst = (bundle[0] >> 5) & 0x1ffffffffffull;
1395	+	break;
1396	+	case 1:
1397	+	inst = ((bundle[1] & 0x7fffffull) << 18) | ((bundle[0] >> 46) & 0x3ffffull);
1398	+	break;
1399	+	case 2:
1400	+	inst = (bundle[1] >> 23) & 0x1ffffffffffull;
1401	+	break;
1402	+	case 3:
1403	+	fprintf(stderr, "ERROR: ia64_get_instruction(), invalid slot number %d\n", slot);
1404	+	abort();
1405	+	break;
1406	+	}
1407	+
1408	+	#if DEBUG
1409	+	printf(" Instruction %d: 0x%016llx\n", slot, inst);
1410	+	#endif
1411	+	return inst;
1412	+	}
1413	+
1414	+	// Decode group 0 instructions
1415	+	static bool ia64_decode_instruction_0(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1416	+	{
1417	+	const int r1 = (inst->inst >>  6) & 0x7f;
1418	+	const int r3 = (inst->inst >> 20) & 0x7f;
1419	+
1420	+	const int x3 = (inst->inst >> 33) & 0x07;
1421	+	const int x6 = (inst->inst >> 27) & 0x3f;
1422	+	const int x2 = (inst->inst >> 31) & 0x03;
1423	+	const int x4 = (inst->inst >> 27) & 0x0f;
1424	+
1425	+	if (x3 == 0) {
1426	+	switch (x6) {
1427	+	case 0x01:                                              // nop.i (I19)
1428	+	inst->mnemo = IA64_INST_NOP;
1429	+	inst->operands[0].valid = true;
1430	+	inst->operands[0].index = -1;
1431	+	inst->operands[0].value = ia64_inst_get_imm21(inst->inst);
1432	+	return true;
1433	+	case 0x14:                                              // sxt1 (I29)
1434	+	case 0x15:                                              // sxt2 (I29)
1435	+	case 0x16:                                              // sxt4 (I29)
1436	+	case 0x10:                                              // zxt1 (I29)
1437	+	case 0x11:                                              // zxt2 (I29)
1438	+	case 0x12:                                              // zxt4 (I29)
1439	+	switch (x6) {
1440	+	case 0x14: inst->mnemo = IA64_INST_SXT1; break;
1441	+	case 0x15: inst->mnemo = IA64_INST_SXT2; break;
1442	+	case 0x16: inst->mnemo = IA64_INST_SXT4; break;
1443	+	case 0x10: inst->mnemo = IA64_INST_ZXT1; break;
1444	+	case 0x11: inst->mnemo = IA64_INST_ZXT2; break;
1445	+	case 0x12: inst->mnemo = IA64_INST_ZXT4; break;
1446	+	default: abort();
1447	+	}
1448	+	inst->operands[0].valid = true;
1449	+	inst->operands[0].index = r1;
1450	+	inst->operands[1].valid = true;
1451	+	inst->operands[1].index = r3;
1452	+	inst->operands[1].value = IA64_GET_GR(r3);
1453	+	inst->operands[1].nat   = IA64_GET_NAT(r3);
1454	+	return true;
1455	+	}
1456	+	}
1457	+	return false;
1458	+	}
1459	+
1460	+	// Decode group 4 instructions (load/store instructions)
1461	+	static bool ia64_decode_instruction_4(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1462	+	{
1463	+	const int r1 = (inst->inst >> 6) & 0x7f;
1464	+	const int r2 = (inst->inst >> 13) & 0x7f;
1465	+	const int r3 = (inst->inst >> 20) & 0x7f;
1466	+
1467	+	const int m  = (inst->inst >> 36) & 1;
1468	+	const int x  = (inst->inst >> 27) & 1;
1469	+	const int x6 = (inst->inst >> 30) & 0x3f;
1470	+
1471	+	switch (x6) {
1472	+	case 0x00:
1473	+	case 0x01:
1474	+	case 0x02:
1475	+	case 0x03:
1476	+	if (x == 0) {
1477	+	inst->operands[0].valid = true;
1478	+	inst->operands[0].index = r1;
1479	+	inst->operands[1].valid = true;
1480	+	inst->operands[1].index = r3;
1481	+	inst->operands[1].value = IA64_GET_GR(r3);
1482	+	inst->operands[1].nat   = IA64_GET_NAT(r3);
1483	+	if (m == 0) {
1484	+	switch (x6) {
1485	+	case 0x00: inst->mnemo = IA64_INST_LD1; break;
1486	+	case 0x01: inst->mnemo = IA64_INST_LD2; break;
1487	+	case 0x02: inst->mnemo = IA64_INST_LD4; break;
1488	+	case 0x03: inst->mnemo = IA64_INST_LD8; break;
1489	+	}
1490	+	}
1491	+	else {
1492	+	inst->operands[2].valid = true;
1493	+	inst->operands[2].index = r2;
1494	+	inst->operands[2].value = IA64_GET_GR(r2);
1495	+	inst->operands[2].nat   = IA64_GET_NAT(r2);
1496	+	switch (x6) {
1497	+	case 0x00: inst->mnemo = IA64_INST_LD1_UPDATE; break;
1498	+	case 0x01: inst->mnemo = IA64_INST_LD2_UPDATE; break;
1499	+	case 0x02: inst->mnemo = IA64_INST_LD4_UPDATE; break;
1500	+	case 0x03: inst->mnemo = IA64_INST_LD8_UPDATE; break;
1501	+	}
1502	+	}
1503	+	return true;
1504	+	}
1505	+	break;
1506	+	case 0x30:
1507	+	case 0x31:
1508	+	case 0x32:
1509	+	case 0x33:
1510	+	if (m == 0 && x == 0) {
1511	+	inst->operands[0].valid = true;
1512	+	inst->operands[0].index = r3;
1513	+	inst->operands[0].value = IA64_GET_GR(r3);
1514	+	inst->operands[0].nat   = IA64_GET_NAT(r3);
1515	+	inst->operands[1].valid = true;
1516	+	inst->operands[1].index = r2;
1517	+	inst->operands[1].value = IA64_GET_GR(r2);
1518	+	inst->operands[1].nat   = IA64_GET_NAT(r2);
1519	+	switch (x6) {
1520	+	case 0x30: inst->mnemo = IA64_INST_ST1; break;
1521	+	case 0x31: inst->mnemo = IA64_INST_ST2; break;
1522	+	case 0x32: inst->mnemo = IA64_INST_ST4; break;
1523	+	case 0x33: inst->mnemo = IA64_INST_ST8; break;
1524	+	}
1525	+	return true;
1526	+	}
1527	+	break;
1528	+	}
1529	+	return false;
1530	+	}
1531	+
1532	+	// Decode group 5 instructions (load/store instructions)
1533	+	static bool ia64_decode_instruction_5(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1534	+	{
1535	+	const int r1 = (inst->inst >> 6) & 0x7f;
1536	+	const int r2 = (inst->inst >> 13) & 0x7f;
1537	+	const int r3 = (inst->inst >> 20) & 0x7f;
1538	+
1539	+	const int x6 = (inst->inst >> 30) & 0x3f;
1540	+
1541	+	switch (x6) {
1542	+	case 0x00:
1543	+	case 0x01:
1544	+	case 0x02:
1545	+	case 0x03:
1546	+	inst->operands[0].valid = true;
1547	+	inst->operands[0].index = r1;
1548	+	inst->operands[1].valid = true;
1549	+	inst->operands[1].index = r3;
1550	+	inst->operands[1].value = IA64_GET_GR(r3);
1551	+	inst->operands[1].nat   = IA64_GET_NAT(r3);
1552	+	inst->operands[2].valid = true;
1553	+	inst->operands[2].index = -1;
1554	+	inst->operands[2].value = ia64_inst_get_imm9b(inst->inst);
1555	+	inst->operands[2].nat   = 0;
1556	+	switch (x6) {
1557	+	case 0x00: inst->mnemo = IA64_INST_LD1_UPDATE; break;
1558	+	case 0x01: inst->mnemo = IA64_INST_LD2_UPDATE; break;
1559	+	case 0x02: inst->mnemo = IA64_INST_LD4_UPDATE; break;
1560	+	case 0x03: inst->mnemo = IA64_INST_LD8_UPDATE; break;
1561	+	}
1562	+	return true;
1563	+	case 0x30:
1564	+	case 0x31:
1565	+	case 0x32:
1566	+	case 0x33:
1567	+	inst->operands[0].valid = true;
1568	+	inst->operands[0].index = r3;
1569	+	inst->operands[0].value = IA64_GET_GR(r3);
1570	+	inst->operands[0].nat   = IA64_GET_NAT(r3);
1571	+	inst->operands[1].valid = true;
1572	+	inst->operands[1].index = r2;
1573	+	inst->operands[1].value = IA64_GET_GR(r2);
1574	+	inst->operands[1].nat   = IA64_GET_NAT(r2);
1575	+	inst->operands[2].valid = true;
1576	+	inst->operands[2].index = -1;
1577	+	inst->operands[2].value = ia64_inst_get_imm9a(inst->inst);
1578	+	inst->operands[2].nat   = 0;
1579	+	switch (x6) {
1580	+	case 0x30: inst->mnemo = IA64_INST_ST1_UPDATE; break;
1581	+	case 0x31: inst->mnemo = IA64_INST_ST2_UPDATE; break;
1582	+	case 0x32: inst->mnemo = IA64_INST_ST4_UPDATE; break;
1583	+	case 0x33: inst->mnemo = IA64_INST_ST8_UPDATE; break;
1584	+	}
1585	+	return true;
1586	+	}
1587	+	return false;
1588	+	}
1589	+
1590	+	// Decode group 8 instructions (ALU integer)
1591	+	static bool ia64_decode_instruction_8(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1592	+	{
1593	+	const int r1  = (inst->inst >> 6) & 0x7f;
1594	+	const int r2  = (inst->inst >> 13) & 0x7f;
1595	+	const int r3  = (inst->inst >> 20) & 0x7f;
1596	+
1597	+	const int x2a = (inst->inst >> 34) & 0x3;
1598	+	const int x2b = (inst->inst >> 27) & 0x3;
1599	+	const int x4  = (inst->inst >> 29) & 0xf;
1600	+	const int ve  = (inst->inst >> 33) & 0x1;
1601	+
1602	+	// destination register (r1) is always valid in this group
1603	+	inst->operands[0].valid = true;
1604	+	inst->operands[0].index = r1;
1605	+
1606	+	// source register (r3) is always valid in this group
1607	+	inst->operands[2].valid = true;
1608	+	inst->operands[2].index = r3;
1609	+	inst->operands[2].value = IA64_GET_GR(r3);
1610	+	inst->operands[2].nat   = IA64_GET_NAT(r3);
1611	+
1612	+	if (x2a == 0 && ve == 0) {
1613	+	inst->operands[1].valid = true;
1614	+	inst->operands[1].index = r2;
1615	+	inst->operands[1].value = IA64_GET_GR(r2);
1616	+	inst->operands[1].nat   = IA64_GET_NAT(r2);
1617	+	switch (x4) {
1618	+	case 0x0:                               // add (A1)
1619	+	inst->mnemo = IA64_INST_ADD;
1620	+	inst->operands[3].valid = true;
1621	+	inst->operands[3].index = -1;
1622	+	inst->operands[3].value = x2b == 1;
1623	+	return true;
1624	+	case 0x1:                               // add (A1)
1625	+	inst->mnemo = IA64_INST_SUB;
1626	+	inst->operands[3].valid = true;
1627	+	inst->operands[3].index = -1;
1628	+	inst->operands[3].value = x2b == 0;
1629	+	return true;
1630	+	case 0x4:                               // shladd (A2)
1631	+	inst->mnemo = IA64_INST_SHLADD;
1632	+	inst->operands[3].valid = true;
1633	+	inst->operands[3].index = -1;
1634	+	inst->operands[3].value = ia64_inst_get_count2(inst->inst);
1635	+	return true;
1636	+	case 0x9:
1637	+	if (x2b == 1) {
1638	+	inst->mnemo = IA64_INST_SUB;
1639	+	inst->operands[1].index = -1;
1640	+	inst->operands[1].value = ia64_inst_get_imm8(inst->inst);
1641	+	inst->operands[1].nat   = 0;
1642	+	return true;
1643	+	}
1644	+	break;
1645	+	case 0xb:
1646	+	inst->operands[1].index = -1;
1647	+	inst->operands[1].value = ia64_inst_get_imm8(inst->inst);
1648	+	inst->operands[1].nat   = 0;
1649	+	// fall-through
1650	+	case 0x3:
1651	+	switch (x2b) {
1652	+	case 0: inst->mnemo = IA64_INST_AND;   break;
1653	+	case 1: inst->mnemo = IA64_INST_ANDCM; break;
1654	+	case 2: inst->mnemo = IA64_INST_OR;    break;
1655	+	case 3: inst->mnemo = IA64_INST_XOR;   break;
1656	+	}
1657	+	return true;
1658	+	}
1659	+	}
1660	+	return false;
1661	+	}
1662	+
1663	+	// Decode instruction
1664	+	static bool ia64_decode_instruction(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1665	+	{
1666	+	const int major = (inst->inst >> 37) & 0xf;
1667	+
1668	+	inst->mnemo = IA64_INST_UNKNOWN;
1669	+	inst->pred  = inst->inst & 0x3f;
1670	+	memset(&inst->operands[0], 0, sizeof(inst->operands));
1671	+
1672	+	switch (major) {
1673	+	case 0x0: return ia64_decode_instruction_0(inst, IA64_CONTEXT);
1674	+	case 0x4: return ia64_decode_instruction_4(inst, IA64_CONTEXT);
1675	+	case 0x5: return ia64_decode_instruction_5(inst, IA64_CONTEXT);
1676	+	case 0x8: return ia64_decode_instruction_8(inst, IA64_CONTEXT);
1677	+	}
1678	+	return false;
1679	+	}
1680	+
1681	+	static bool ia64_emulate_instruction(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1682	+	{
1683	+	// XXX: handle Register NaT Consumption fault?
1684	+	// XXX: this simple emulator assumes instructions in a bundle
1685	+	// don't depend on effects of other instructions in the same
1686	+	// bundle. It probably would be simpler to JIT-generate code to be
1687	+	// executed natively but probably more costly (inject/extract CPU state)
1688	+	if (inst->mnemo == IA64_INST_UNKNOWN)
1689	+	return false;
1690	+	if (inst->pred && !IA64_GET_PR(inst->pred))
1691	+	return true;
1692	+
1693	+	uint8_t nat, nat2;
1694	+	uint64_t dst, dst2, src1, src2, src3;
1695	+
1696	+	switch (inst->mnemo) {
1697	+	case IA64_INST_NOP:
1698	+	break;
1699	+	case IA64_INST_ADD:
1700	+	case IA64_INST_SUB:
1701	+	case IA64_INST_SHLADD:
1702	+	src3 = inst->operands[3].value;
1703	+	// fall-through
1704	+	case IA64_INST_AND:
1705	+	case IA64_INST_ANDCM:
1706	+	case IA64_INST_OR:
1707	+	case IA64_INST_XOR:
1708	+	src1 = inst->operands[1].value;
1709	+	src2 = inst->operands[2].value;
1710	+	switch (inst->mnemo) {
1711	+	case IA64_INST_ADD:   dst = src1 + src2 + src3; break;
1712	+	case IA64_INST_SUB:   dst = src1 - src2 - src3; break;
1713	+	case IA64_INST_SHLADD: dst = (src1 << src3) + src2; break;
1714	+	case IA64_INST_AND:   dst = src1 & src2;                break;
1715	+	case IA64_INST_ANDCM: dst = src1 &~ src2;               break;
1716	+	case IA64_INST_OR:    dst = src1 | src2;                break;
1717	+	case IA64_INST_XOR:   dst = src1 ^ src2;                break;
1718	+	}
1719	+	inst->operands[0].commit = true;
1720	+	inst->operands[0].value  = dst;
1721	+	inst->operands[0].nat    = inst->operands[1].nat | inst->operands[2].nat;
1722	+	break;
1723	+	case IA64_INST_SXT1:
1724	+	case IA64_INST_SXT2:
1725	+	case IA64_INST_SXT4:
1726	+	case IA64_INST_ZXT1:
1727	+	case IA64_INST_ZXT2:
1728	+	case IA64_INST_ZXT4:
1729	+	src1 = inst->operands[1].value;
1730	+	switch (inst->mnemo) {
1731	+	case IA64_INST_SXT1: dst = (int64_t)(int8_t)src1;               break;
1732	+	case IA64_INST_SXT2: dst = (int64_t)(int16_t)src1;              break;
1733	+	case IA64_INST_SXT4: dst = (int64_t)(int32_t)src1;              break;
1734	+	case IA64_INST_ZXT1: dst = (uint8_t)src1;                               break;
1735	+	case IA64_INST_ZXT2: dst = (uint16_t)src1;                              break;
1736	+	case IA64_INST_ZXT4: dst = (uint32_t)src1;                              break;
1737	+	}
1738	+	inst->operands[0].commit = true;
1739	+	inst->operands[0].value  = dst;
1740	+	inst->operands[0].nat    = inst->operands[1].nat;
1741	+	break;
1742	+	case IA64_INST_LD1_UPDATE:
1743	+	case IA64_INST_LD2_UPDATE:
1744	+	case IA64_INST_LD4_UPDATE:
1745	+	case IA64_INST_LD8_UPDATE:
1746	+	inst->operands[1].commit = true;
1747	+	dst2 = inst->operands[1].value + inst->operands[2].value;
1748	+	nat2 = inst->operands[2].nat ? inst->operands[2].nat : 0;
1749	+	// fall-through
1750	+	case IA64_INST_LD1:
1751	+	case IA64_INST_LD2:
1752	+	case IA64_INST_LD4:
1753	+	case IA64_INST_LD8:
1754	+	src1 = inst->operands[1].value;
1755	+	if (inst->no_memory)
1756	+	dst = 0;
1757	+	else {
1758	+	switch (inst->mnemo) {
1759	+	case IA64_INST_LD1: case IA64_INST_LD1_UPDATE: dst = *((uint8_t *)src1);        break;
1760	+	case IA64_INST_LD2: case IA64_INST_LD2_UPDATE: dst = *((uint16_t *)src1);       break;
1761	+	case IA64_INST_LD4: case IA64_INST_LD4_UPDATE: dst = *((uint32_t *)src1);       break;
1762	+	case IA64_INST_LD8: case IA64_INST_LD8_UPDATE: dst = *((uint64_t *)src1);       break;
1763	+	}
1764	+	}
1765	+	inst->operands[0].commit = true;
1766	+	inst->operands[0].value  = dst;
1767	+	inst->operands[0].nat    = 0;
1768	+	inst->operands[1].value  = dst2;
1769	+	inst->operands[1].nat    = nat2;
1770	+	break;
1771	+	case IA64_INST_ST1_UPDATE:
1772	+	case IA64_INST_ST2_UPDATE:
1773	+	case IA64_INST_ST4_UPDATE:
1774	+	case IA64_INST_ST8_UPDATE:
1775	+	inst->operands[0].commit = 0;
1776	+	dst2 = inst->operands[0].value + inst->operands[2].value;
1777	+	nat2 = inst->operands[2].nat ? inst->operands[2].nat : 0;
1778	+	// fall-through
1779	+	case IA64_INST_ST1:
1780	+	case IA64_INST_ST2:
1781	+	case IA64_INST_ST4:
1782	+	case IA64_INST_ST8:
1783	+	dst  = inst->operands[0].value;
1784	+	src1 = inst->operands[1].value;
1785	+	if (!inst->no_memory) {
1786	+	switch (inst->mnemo) {
1787	+	case IA64_INST_ST1: case IA64_INST_ST1_UPDATE: *((uint8_t *)dst) = src1;        break;
1788	+	case IA64_INST_ST2: case IA64_INST_ST2_UPDATE: *((uint16_t *)dst) = src1;       break;
1789	+	case IA64_INST_ST4: case IA64_INST_ST4_UPDATE: *((uint32_t *)dst) = src1;       break;
1790	+	case IA64_INST_ST8: case IA64_INST_ST8_UPDATE: *((uint64_t *)dst) = src1;       break;
1791	+	}
1792	+	}
1793	+	inst->operands[0].value  = dst2;
1794	+	inst->operands[0].nat    = nat2;
1795	+	break;
1796	+	default:
1797	+	return false;
1798	+	}
1799	+
1800	+	for (int i = 0; i < IA64_N_OPERANDS; i++) {
1801	+	ia64_operand_t const & op = inst->operands[i];
1802	+	if (!op.commit)
1803	+	continue;
1804	+	if (op.index == -1)
1805	+	return false; // XXX: internal error
1806	+	IA64_SET_GR(op.index, op.value, op.nat);
1807	+	}
1808	+	return true;
1809	+	}
1810	+
1811	+	static bool ia64_emulate_instruction(uint64_t raw_inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1812	+	{
1813	+	ia64_instruction_t inst;
1814	+	memset(&inst, 0, sizeof(inst));
1815	+	inst.inst = raw_inst;
1816	+	if (!ia64_decode_instruction(&inst, IA64_CONTEXT))
1817	+	return false;
1818	+	return ia64_emulate_instruction(&inst, IA64_CONTEXT);
1819	+	}
1820	+
1821	+	static bool ia64_skip_instruction(IA64_CONTEXT_TYPE IA64_CONTEXT)
1822	+	{
1823	+	uint64_t ip = IA64_GET_IP();
1824	+	#if DEBUG
1825	+	printf("IP: 0x%016llx\n", ip);
1826	+	#if 0
1827	+	printf(" Template 0x%02x\n", ia64_get_template(ip));
1828	+	ia64_get_instruction(ip, 0);
1829	+	ia64_get_instruction(ip, 1);
1830	+	ia64_get_instruction(ip, 2);
1831	+	#endif
1832	+	#endif
1833	+
1834	+	// Select which decode switch to use
1835	+	ia64_instruction_t inst;
1836	+	inst.inst = ia64_get_instruction(ip, ip & 3);
1837	+	if (!ia64_decode_instruction(&inst, IA64_CONTEXT)) {
1838	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): could not decode instruction\n");
1839	+	return false;
1840	+	}
1841	+
1842	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1843	+	transfer_size_t transfer_size = SIZE_UNKNOWN;
1844	+
1845	+	switch (inst.mnemo) {
1846	+	case IA64_INST_LD1:
1847	+	case IA64_INST_LD2:
1848	+	case IA64_INST_LD4:
1849	+	case IA64_INST_LD8:
1850	+	case IA64_INST_LD1_UPDATE:
1851	+	case IA64_INST_LD2_UPDATE:
1852	+	case IA64_INST_LD4_UPDATE:
1853	+	case IA64_INST_LD8_UPDATE:
1854	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1855	+	break;
1856	+	case IA64_INST_ST1:
1857	+	case IA64_INST_ST2:
1858	+	case IA64_INST_ST4:
1859	+	case IA64_INST_ST8:
1860	+	case IA64_INST_ST1_UPDATE:
1861	+	case IA64_INST_ST2_UPDATE:
1862	+	case IA64_INST_ST4_UPDATE:
1863	+	case IA64_INST_ST8_UPDATE:
1864	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1865	+	break;
1866	+	}
1867	+
1868	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1869	+	// Unknown machine code, let it crash. Then patch the decoder
1870	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): not a load/store instruction\n");
1871	+	return false;
1872	+	}
1873	+
1874	+	switch (inst.mnemo) {
1875	+	case IA64_INST_LD1:
1876	+	case IA64_INST_LD1_UPDATE:
1877	+	case IA64_INST_ST1:
1878	+	case IA64_INST_ST1_UPDATE:
1879	+	transfer_size = SIZE_BYTE;
1880	+	break;
1881	+	case IA64_INST_LD2:
1882	+	case IA64_INST_LD2_UPDATE:
1883	+	case IA64_INST_ST2:
1884	+	case IA64_INST_ST2_UPDATE:
1885	+	transfer_size = SIZE_WORD;
1886	+	break;
1887	+	case IA64_INST_LD4:
1888	+	case IA64_INST_LD4_UPDATE:
1889	+	case IA64_INST_ST4:
1890	+	case IA64_INST_ST4_UPDATE:
1891	+	transfer_size = SIZE_LONG;
1892	+	break;
1893	+	case IA64_INST_LD8:
1894	+	case IA64_INST_LD8_UPDATE:
1895	+	case IA64_INST_ST8:
1896	+	case IA64_INST_ST8_UPDATE:
1897	+	transfer_size = SIZE_QUAD;
1898	+	break;
1899	+	}
1900	+
1901	+	if (transfer_size == SIZE_UNKNOWN) {
1902	+	// Unknown machine code, let it crash. Then patch the decoder
1903	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): unknown transfer size\n");
1904	+	return false;
1905	+	}
1906	+
1907	+	inst.no_memory = true;
1908	+	if (!ia64_emulate_instruction(&inst, IA64_CONTEXT)) {
1909	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): could not emulate fault instruction\n");
1910	+	return false;
1911	+	}
1912	+
1913	+	int slot = ip & 3;
1914	+	bool emulate_next = false;
1915	+	switch (slot) {
1916	+	case 0:
1917	+	switch (ia64_get_template(ip)) {
1918	+	case 0x2: // MI;I
1919	+	case 0x3: // MI;I;
1920	+	emulate_next = true;
1921	+	slot = 2;
1922	+	break;
1923	+	case 0xa: // M;MI
1924	+	case 0xb: // M;MI;
1925	+	emulate_next = true;
1926	+	slot = 1;
1927	+	break;
1928	+	}
1929	+	break;
1930	+	}
1931	+	if (emulate_next && !IA64_CAN_PATCH_IP_SLOT) {
1932	+	while (slot < 3) {
1933	+	if (!ia64_emulate_instruction(ia64_get_instruction(ip, slot), IA64_CONTEXT)) {
1934	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): could not emulate instruction\n");
1935	+	return false;
1936	+	}
1937	+	++slot;
1938	+	}
1939	+	}
1940	+
1941	+	#if IA64_CAN_PATCH_IP_SLOT
1942	+	if ((slot = ip & 3) < 2)
1943	+	IA64_SET_IP((ip & ~3ull) + (slot + 1));
1944	+	else
1945	+	#endif
1946	+	IA64_SET_IP((ip & ~3ull) + 16);
1947	+	#if DEBUG
1948	+	printf("IP: 0x%016llx\n", IA64_GET_IP());
1949	+	#endif
1950	+	return true;
1951	+	}
1952	+	#endif
1953	+
1954		// Decode and skip PPC instruction
1955		#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__) || defined(__ppc64__))
1956		static bool powerpc_skip_instruction(unsigned long * nip_p, unsigned long * regs)
#	Line 1718 | Line 2509 | sigsegv_address_t sigsegv_get_fault_addr
2509		mach_get_exception_state(SIP);
2510
2511		sigsegv_address_t addr = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS;
2512	<	if (use_fast_path < 0)
2513	<	use_fast_path = addr == SIP->addr;
2512	>	if (use_fast_path < 0) {
2513	>	const char *machfault = getenv("SIGSEGV_MACH_FAULT");
2514	>	if (machfault) {
2515	>	if (strcmp(machfault, "fast") == 0)
2516	>	use_fast_path = 1;
2517	>	else if (strcmp(machfault, "slow") == 0)
2518	>	use_fast_path = 0;
2519	>	}
2520	>	if (use_fast_path < 0)
2521	>	use_fast_path = addr == SIP->addr;
2522	>	}
2523		SIP->addr = addr;
2524		}
2525		#endif
#	Line 2248 | Line 3048 | void sigsegv_set_dump_state(sigsegv_stat
3048		const int REF_INDEX = 123;
3049		const int REF_VALUE = 45;
3050
3051	<	static int page_size;
3051	>	static sigsegv_uintptr_t page_size;
3052		static volatile char * page = 0;
3053		static volatile int handler_called = 0;
3054
#	Line 2286 | Line 3086 | static sigsegv_return_t sigsegv_test_han
3086		(instruction_address >= (sigsegv_address_t)e_region)))
3087		exit(11);
3088		#endif
3089	<	if (vm_protect((char *)((unsigned long)fault_address & -page_size), page_size, VM_PAGE_READ | VM_PAGE_WRITE) != 0)
3089	>	if (vm_protect((char *)((sigsegv_uintptr_t)fault_address & -page_size), page_size, VM_PAGE_READ | VM_PAGE_WRITE) != 0)
3090		exit(12);
3091		return SIGSEGV_RETURN_SUCCESS;
3092		}
#	Line 2299 | Line 3099 | static sigsegv_return_t sigsegv_insn_han
3099		#if DEBUG
3100		printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address);
3101		#endif
3102	<	if (((unsigned long)fault_address - (unsigned long)page) < page_size) {
3102	>	if (((sigsegv_uintptr_t)fault_address - (sigsegv_uintptr_t)page) < page_size) {
3103		#ifdef __GNUC__
3104		// Make sure reported fault instruction address falls into
3105		// expected code range
#	Line 2317 | Line 3117 | static sigsegv_return_t sigsegv_insn_han
3117		// More sophisticated tests for instruction skipper
3118		static bool arch_insn_skipper_tests()
3119		{
3120	<	#if (defined(i386) || defined(__i386__)) || defined(__x86_64__)
3120	>	#if (defined(i386) || defined(__i386__)) || (defined(__x86_64__) || defined(_M_X64))
3121		static const unsigned char code[] = {
3122		0x8a, 0x00,                    // mov    (%eax),%al
3123		0x8a, 0x2c, 0x18,              // mov    (%eax,%ebx,1),%ch
#	Line 2331 | Line 3131 | static bool arch_insn_skipper_tests()
3131		0x8b, 0x0c, 0x18,              // mov    (%eax,%ebx,1),%ecx
3132		0x89, 0x00,                    // mov    %eax,(%eax)
3133		0x89, 0x0c, 0x18,              // mov    %ecx,(%eax,%ebx,1)
3134	<	#if defined(__x86_64__)
3134	>	#if defined(__x86_64__) || defined(_M_X64)
3135		0x44, 0x8a, 0x00,              // mov    (%rax),%r8b
3136		0x44, 0x8a, 0x20,              // mov    (%rax),%r12b
3137		0x42, 0x8a, 0x3c, 0x10,        // mov    (%rax,%r10,1),%dil
#	Line 2360 | Line 3160 | static bool arch_insn_skipper_tests()
3160		0                              // end
3161		};
3162		const int N_REGS = 20;
3163	<	unsigned long regs[N_REGS];
3163	>	SIGSEGV_REGISTER_TYPE regs[N_REGS];
3164		for (int i = 0; i < N_REGS; i++)
3165		regs[i] = i;
3166	<	const unsigned long start_code = (unsigned long)&code;
3166	>	const sigsegv_uintptr_t start_code = (sigsegv_uintptr_t)&code;
3167		regs[X86_REG_EIP] = start_code;
3168		while ((regs[X86_REG_EIP] - start_code) < (sizeof(code) - 1)
3169		&& ix86_skip_instruction(regs))
#	Line 2389 | Line 3189 | int main(void)
3189
3190		if (!sigsegv_install_handler(sigsegv_test_handler))
3191		return 4;
3192	<
3192	>
3193		#ifdef __GNUC__
3194		b_region = &&L_b_region1;
3195		e_region = &&L_e_region1;
3196		#endif
3197	<	L_b_region1:
3198	<	page[REF_INDEX] = REF_VALUE;
3199	<	if (page[REF_INDEX] != REF_VALUE)
3200	<	exit(20);
3201	<	page[REF_INDEX] = REF_VALUE;
3202	<	BARRIER();
3203	<	L_e_region1:
3197	>	/* This is a really awful hack but otherwise gcc is smart enough
3198	>	* (or bug'ous enough?) to optimize the labels and place them
3199	>	* e.g. at the "main" entry point, which is wrong.
3200	>	*/
3201	>	volatile int label_hack = 1;
3202	>	switch (label_hack) {
3203	>	case 1:
3204	>	L_b_region1:
3205	>	page[REF_INDEX] = REF_VALUE;
3206	>	if (page[REF_INDEX] != REF_VALUE)
3207	>	exit(20);
3208	>	page[REF_INDEX] = REF_VALUE;
3209	>	BARRIER();
3210	>	// fall-through
3211	>	case 2:
3212	>	L_e_region1:
3213	>	BARRIER();
3214	>	break;
3215	>	}
3216
3217		if (handler_called != 1)
3218		return 5;
#	Line 2431 | Line 3243 | int main(void)
3243		b_region = &&L_b_region2;
3244		e_region = &&L_e_region2;
3245		#endif
3246	<	L_b_region2:
3247	<	TEST_SKIP_INSTRUCTION(unsigned char);
3248	<	TEST_SKIP_INSTRUCTION(unsigned short);
3249	<	TEST_SKIP_INSTRUCTION(unsigned int);
3250	<	TEST_SKIP_INSTRUCTION(unsigned long);
3251	<	TEST_SKIP_INSTRUCTION(signed char);
3252	<	TEST_SKIP_INSTRUCTION(signed short);
3253	<	TEST_SKIP_INSTRUCTION(signed int);
3254	<	TEST_SKIP_INSTRUCTION(signed long);
3255	<	BARRIER();
3256	<	L_e_region2:
3257	<
3246	>	switch (label_hack) {
3247	>	case 1:
3248	>	L_b_region2:
3249	>	TEST_SKIP_INSTRUCTION(unsigned char);
3250	>	TEST_SKIP_INSTRUCTION(unsigned short);
3251	>	TEST_SKIP_INSTRUCTION(unsigned int);
3252	>	TEST_SKIP_INSTRUCTION(unsigned long);
3253	>	TEST_SKIP_INSTRUCTION(signed char);
3254	>	TEST_SKIP_INSTRUCTION(signed short);
3255	>	TEST_SKIP_INSTRUCTION(signed int);
3256	>	TEST_SKIP_INSTRUCTION(signed long);
3257	>	BARRIER();
3258	>	// fall-through
3259	>	case 2:
3260	>	L_e_region2:
3261	>	BARRIER();
3262	>	break;
3263	>	}
3264		if (!arch_insn_skipper_tests())
3265		return 20;
3266		#endif

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